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IntelSiliconPkg/Vtd: Add more debug info. 

Add more debug info for reason code.

Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
This commit is contained in:
Jiewen Yao 2018-03-18 23:39:13 +08:00
parent 5aef7ba3ce
commit 8d8c487fb9
1 changed files with 1 additions and 1 deletions
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2
IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c
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@ -481,7 +481,7 @@ DumpVtdRegs (
SourceId.Uint16 = (UINT16)FrcdReg.Bits.SID; SourceId.Uint16 = (UINT16)FrcdReg.Bits.SID;
DEBUG((DEBUG_INFO, " Source - B%02x D%02x F%02x\n", SourceId.Bits.Bus, SourceId.Bits.Device, SourceId.Bits.Function)); DEBUG((DEBUG_INFO, " Source - B%02x D%02x F%02x\n", SourceId.Bits.Bus, SourceId.Bits.Device, SourceId.Bits.Function));
DEBUG((DEBUG_INFO, " Type - %x (%a)\n", FrcdReg.Bits.T, FrcdReg.Bits.T ? "read" : "write")); DEBUG((DEBUG_INFO, " Type - %x (%a)\n", FrcdReg.Bits.T, FrcdReg.Bits.T ? "read" : "write"));
DEBUG((DEBUG_INFO, " Reason - %x\n", FrcdReg.Bits.FR)); DEBUG((DEBUG_INFO, " Reason - %x (Refer to VTd Spec, Appendix A)\n", FrcdReg.Bits.FR));
} }
} }