mirror of https://github.com/acidanthera/audk.git
ShellPkg: remove unreachable break statements
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> Reviewed-by: Jaben Carsey <jaben.carsey@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15108 6f19259b-4bc3-4df7-8a09-765794883524
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@ -5274,66 +5274,48 @@ PrintPciExtendedCapabilityDetails(
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switch (HeaderAddress->CapabilityId){
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case PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_ID:
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return PrintInterpretedExtendedCompatibilityAer(HeaderAddress, HeadersBaseAddress);
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break;
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case PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_ID:
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return PrintInterpretedExtendedCompatibilityLinkControl(HeaderAddress, HeadersBaseAddress);
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break;
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case PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_ID:
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return PrintInterpretedExtendedCompatibilityLinkDeclaration(HeaderAddress, HeadersBaseAddress);
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break;
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case PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_ID:
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return PrintInterpretedExtendedCompatibilitySerialNumber(HeaderAddress, HeadersBaseAddress);
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break;
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case PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_ID:
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return PrintInterpretedExtendedCompatibilityPowerBudgeting(HeaderAddress, HeadersBaseAddress);
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break;
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case PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_ID:
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return PrintInterpretedExtendedCompatibilityAcs(HeaderAddress, HeadersBaseAddress);
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break;
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case PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_ID:
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return PrintInterpretedExtendedCompatibilityLatencyToleranceReporting(HeaderAddress, HeadersBaseAddress);
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break;
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case PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_ID:
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return PrintInterpretedExtendedCompatibilityAri(HeaderAddress, HeadersBaseAddress);
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break;
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case PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_ID:
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return PrintInterpretedExtendedCompatibilityRcrb(HeaderAddress, HeadersBaseAddress);
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break;
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case PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_ID:
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return PrintInterpretedExtendedCompatibilityVendorSpecific(HeaderAddress, HeadersBaseAddress);
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break;
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case PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_ID:
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return PrintInterpretedExtendedCompatibilityDynamicPowerAllocation(HeaderAddress, HeadersBaseAddress);
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break;
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case PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_ID:
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return PrintInterpretedExtendedCompatibilityECEA(HeaderAddress, HeadersBaseAddress);
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break;
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case PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_ID:
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case PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_ID:
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return PrintInterpretedExtendedCompatibilityVirtualChannel(HeaderAddress, HeadersBaseAddress);
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break;
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case PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_ID:
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//
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// should only be present if PCIE_CAP_DEVICEPORT_TYPE(PciExpressCapPtr->PcieCapReg) == 0100b, 0101b, or 0110b
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//
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return PrintInterpretedExtendedCompatibilityMulticast(HeaderAddress, HeadersBaseAddress, PciExpressCapPtr);
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break;
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case PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID:
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return PrintInterpretedExtendedCompatibilityResizeableBar(HeaderAddress, HeadersBaseAddress);
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break;
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case PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_ID:
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return PrintInterpretedExtendedCompatibilityTph(HeaderAddress, HeadersBaseAddress);
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break;
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case PCI_EXPRESS_EXTENDED_CAPABILITY_SECONDARY_PCIE_ID:
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return PrintInterpretedExtendedCompatibilitySecondary(HeaderAddress, HeadersBaseAddress, PciExpressCapPtr);
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break;
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default:
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ShellPrintEx (-1, -1,
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L"Unknown PCIe extended capability ID (%04xh). No interpretation available.\r\n",
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HeaderAddress->CapabilityId
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);
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return EFI_SUCCESS;
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break;
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};
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}
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