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BaseTools: Remove unused logic from C tools 

https://bugzilla.tianocore.org/show_bug.cgi?id=1350
Remove IA64 support from BaseTools C code.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Jaben Carsey <jaben.carsey@intel.com>
This commit is contained in:
Feng, Bob C 2019-01-09 16:34:29 +08:00
parent 39879ef267
commit 8daa4278e8
11 changed files with 10 additions and 353 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
BaseTools/Source/C/Common/BasePeCoff.c
View File

@ -56,13 +56,6 @@ PeCoffLoaderRelocateIa32Image (
IN UINT64 Adjust
);
RETURN_STATUS
PeCoffLoaderRelocateIpfImage (
IN UINT16 *Reloc,
IN OUT CHAR8 *Fixup,
IN OUT CHAR8 **FixupData,
IN UINT64 Adjust
);
RETURN_STATUS
PeCoffLoaderRelocateArmImage (
@ -184,7 +177,6 @@ Returns:
}
if (ImageContext->Machine != EFI_IMAGE_MACHINE_IA32 && \
ImageContext->Machine != EFI_IMAGE_MACHINE_IA64 && \
ImageContext->Machine != EFI_IMAGE_MACHINE_X64 && \
ImageContext->Machine != EFI_IMAGE_MACHINE_ARMT && \
ImageContext->Machine != EFI_IMAGE_MACHINE_EBC && \
@ -816,9 +808,6 @@ Returns:
case EFI_IMAGE_MACHINE_ARMT:
Status = PeCoffLoaderRelocateArmImage (&Reloc, Fixup, &FixupData, Adjust);
break;
case EFI_IMAGE_MACHINE_IA64:
Status = PeCoffLoaderRelocateIpfImage (Reloc, Fixup, &FixupData, Adjust);
break;
default:
Status = RETURN_UNSUPPORTED;
break;
@ -1319,9 +1308,8 @@ PeCoffLoaderGetPdbPointer (
Magic = EFI_IMAGE_NT_OPTIONAL_HDR32_MAGIC;
break;
case EFI_IMAGE_MACHINE_X64:
case EFI_IMAGE_MACHINE_IPF:
//
// Assume PE32+ image with X64 or IPF Machine field
// Assume PE32+ image with X64 Machine field
//
Magic = EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC;
break;

162
BaseTools/Source/C/Common/PeCoffLoaderEx.c
View File

@ -1,5 +1,5 @@
/** @file
IA32, X64 and IPF Specific relocation fixups
IA32 and X64 Specific relocation fixups
Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
@ -99,166 +99,6 @@ Returns:
return RETURN_UNSUPPORTED;
}
RETURN_STATUS
PeCoffLoaderRelocateIpfImage (
IN UINT16 *Reloc,
IN OUT CHAR8 *Fixup,
IN OUT CHAR8 **FixupData,
IN UINT64 Adjust
)
/*++
Routine Description:
Performs an Itanium-based specific relocation fixup
Arguments:
Reloc - Pointer to the relocation record
Fixup - Pointer to the address to fix up
FixupData - Pointer to a buffer to log the fixups
Adjust - The offset to adjust the fixup
Returns:
Status code
--*/
{
UINT64 *F64;
UINT64 FixupVal;
switch ((*Reloc) >> 12) {
case EFI_IMAGE_REL_BASED_IA64_IMM64:
//
// Align it to bundle address before fixing up the
// 64-bit immediate value of the movl instruction.
//
Fixup = (CHAR8 *)((UINTN) Fixup & (UINTN) ~(15));
FixupVal = (UINT64)0;
//
// Extract the lower 32 bits of IMM64 from bundle
//
EXT_IMM64(FixupVal,
(UINT32 *)Fixup + IMM64_IMM7B_INST_WORD_X,
IMM64_IMM7B_SIZE_X,
IMM64_IMM7B_INST_WORD_POS_X,
IMM64_IMM7B_VAL_POS_X
);
EXT_IMM64(FixupVal,
(UINT32 *)Fixup + IMM64_IMM9D_INST_WORD_X,
IMM64_IMM9D_SIZE_X,
IMM64_IMM9D_INST_WORD_POS_X,
IMM64_IMM9D_VAL_POS_X
);
EXT_IMM64(FixupVal,
(UINT32 *)Fixup + IMM64_IMM5C_INST_WORD_X,
IMM64_IMM5C_SIZE_X,
IMM64_IMM5C_INST_WORD_POS_X,
IMM64_IMM5C_VAL_POS_X
);
EXT_IMM64(FixupVal,
(UINT32 *)Fixup + IMM64_IC_INST_WORD_X,
IMM64_IC_SIZE_X,
IMM64_IC_INST_WORD_POS_X,
IMM64_IC_VAL_POS_X
);
EXT_IMM64(FixupVal,
(UINT32 *)Fixup + IMM64_IMM41a_INST_WORD_X,
IMM64_IMM41a_SIZE_X,
IMM64_IMM41a_INST_WORD_POS_X,
IMM64_IMM41a_VAL_POS_X
);
//
// Update 64-bit address
//
FixupVal += Adjust;
//
// Insert IMM64 into bundle
//
INS_IMM64(FixupVal,
((UINT32 *)Fixup + IMM64_IMM7B_INST_WORD_X),
IMM64_IMM7B_SIZE_X,
IMM64_IMM7B_INST_WORD_POS_X,
IMM64_IMM7B_VAL_POS_X
);
INS_IMM64(FixupVal,
((UINT32 *)Fixup + IMM64_IMM9D_INST_WORD_X),
IMM64_IMM9D_SIZE_X,
IMM64_IMM9D_INST_WORD_POS_X,
IMM64_IMM9D_VAL_POS_X
);
INS_IMM64(FixupVal,
((UINT32 *)Fixup + IMM64_IMM5C_INST_WORD_X),
IMM64_IMM5C_SIZE_X,
IMM64_IMM5C_INST_WORD_POS_X,
IMM64_IMM5C_VAL_POS_X
);
INS_IMM64(FixupVal,
((UINT32 *)Fixup + IMM64_IC_INST_WORD_X),
IMM64_IC_SIZE_X,
IMM64_IC_INST_WORD_POS_X,
IMM64_IC_VAL_POS_X
);
INS_IMM64(FixupVal,
((UINT32 *)Fixup + IMM64_IMM41a_INST_WORD_X),
IMM64_IMM41a_SIZE_X,
IMM64_IMM41a_INST_WORD_POS_X,
IMM64_IMM41a_VAL_POS_X
);
INS_IMM64(FixupVal,
((UINT32 *)Fixup + IMM64_IMM41b_INST_WORD_X),
IMM64_IMM41b_SIZE_X,
IMM64_IMM41b_INST_WORD_POS_X,
IMM64_IMM41b_VAL_POS_X
);
INS_IMM64(FixupVal,
((UINT32 *)Fixup + IMM64_IMM41c_INST_WORD_X),
IMM64_IMM41c_SIZE_X,
IMM64_IMM41c_INST_WORD_POS_X,
IMM64_IMM41c_VAL_POS_X
);
INS_IMM64(FixupVal,
((UINT32 *)Fixup + IMM64_SIGN_INST_WORD_X),
IMM64_SIGN_SIZE_X,
IMM64_SIGN_INST_WORD_POS_X,
IMM64_SIGN_VAL_POS_X
);
F64 = (UINT64 *) Fixup;
if (*FixupData != NULL) {
*FixupData = ALIGN_POINTER(*FixupData, sizeof(UINT64));
*(UINT64 *)(*FixupData) = *F64;
*FixupData = *FixupData + sizeof(UINT64);
}
break;
default:
return RETURN_UNSUPPORTED;
}
return RETURN_SUCCESS;
}
/**
Pass in a pointer to an ARM MOVT or MOVW immediate instruciton and

3
BaseTools/Source/C/EfiRom/EfiRom.h
View File

@ -115,9 +115,8 @@ typedef struct {
//
static STRING_LOOKUP mMachineTypes[] = {
{ EFI_IMAGE_MACHINE_IA32, "IA32" },
{ EFI_IMAGE_MACHINE_IA64, "IA64" },
{ EFI_IMAGE_MACHINE_EBC, "EBC" },
{ EFI_IMAGE_MACHINE_X64, "X64" },
{ EFI_IMAGE_MACHINE_EBC, "EBC" },
{ EFI_IMAGE_MACHINE_ARMT, "ARM" },
{ EFI_IMAGE_MACHINE_AARCH64, "AA64" },
{ 0, NULL }

70
BaseTools/Source/C/GenFv/GenFvInternalLib.c
View File

@ -905,15 +905,7 @@ Returns:
fprintf (FvMapFile, "BaseAddress=0x%010llx, ", (unsigned long long) (ImageBaseAddress + Offset));
}
if (FfsFile->Type != EFI_FV_FILETYPE_SECURITY_CORE && pImageContext->Machine == EFI_IMAGE_MACHINE_IA64) {
//
// Process IPF PLABEL to get the real address after the image has been rebased.
// PLABEL structure is got by AddressOfEntryPoint offset to ImageBuffer stored in pImageContext->Handle.
//
fprintf (FvMapFile, "EntryPoint=0x%010llx", (unsigned long long) (*(UINT64 *)((UINTN) pImageContext->Handle + (UINTN) AddressOfEntryPoint)));
} else {
fprintf (FvMapFile, "EntryPoint=0x%010llx", (unsigned long long) (ImageBaseAddress + AddressOfEntryPoint));
}
fprintf (FvMapFile, ")\n");
fprintf (FvMapFile, "(GUID=%s", FileGuidName);
@ -1541,7 +1533,6 @@ Returns:
UINT16 MachineType;
EFI_PHYSICAL_ADDRESS PeiCorePhysicalAddress;
EFI_PHYSICAL_ADDRESS SecCorePhysicalAddress;
EFI_PHYSICAL_ADDRESS *SecCoreEntryAddressPtr;
INT32 Ia32SecEntryOffset;
UINT32 *Ia32ResetAddressPtr;
UINT8 *BytePointer;
@ -1551,8 +1542,6 @@ Returns:
UINT32 IpiVector;
UINTN Index;
EFI_FFS_FILE_STATE SavedState;
UINT64 FitAddress;
FIT_TABLE *FitTablePtr;
BOOLEAN Vtf0Detected;
UINT32 FfsHeaderSize;
UINT32 SecHeaderSize;
@ -1692,62 +1681,7 @@ Returns:
DebugMsg (NULL, 0, 9, "PeiCore physical entry point address", "Address = 0x%llX", (unsigned long long) PeiCorePhysicalAddress);
}
if (MachineType == EFI_IMAGE_MACHINE_IA64) {
//
// Update PEI_CORE address
//
//
// Set the uncached attribute bit in the physical address
//
PeiCorePhysicalAddress |= 0x8000000000000000ULL;
//
// Check if address is aligned on a 16 byte boundary
//
if (PeiCorePhysicalAddress & 0xF) {
Error (NULL, 0, 3000, "Invalid",
"PEI_CORE entry point is not aligned on a 16 byte boundary, address specified is %llXh.",
(unsigned long long) PeiCorePhysicalAddress
);
return EFI_ABORTED;
}
//
// First Get the FIT table address
//
FitAddress = (*(UINT64 *) (FvImage->Eof - IPF_FIT_ADDRESS_OFFSET)) & 0xFFFFFFFF;
FitTablePtr = (FIT_TABLE *) (FvImage->FileImage + (FitAddress - FvInfo->BaseAddress));
Status = UpdatePeiCoreEntryInFit (FitTablePtr, PeiCorePhysicalAddress);
if (!EFI_ERROR (Status)) {
UpdateFitCheckSum (FitTablePtr);
}
//
// Update SEC_CORE address
//
//
// Set the uncached attribute bit in the physical address
//
SecCorePhysicalAddress |= 0x8000000000000000ULL;
//
// Check if address is aligned on a 16 byte boundary
//
if (SecCorePhysicalAddress & 0xF) {
Error (NULL, 0, 3000, "Invalid",
"SALE_ENTRY entry point is not aligned on a 16 byte boundary, address specified is %llXh.",
(unsigned long long) SecCorePhysicalAddress
);
return EFI_ABORTED;
}
//
// Update the address
//
SecCoreEntryAddressPtr = (EFI_PHYSICAL_ADDRESS *) ((UINTN) FvImage->Eof - IPF_SALE_ENTRY_ADDRESS_OFFSET);
*SecCoreEntryAddressPtr = SecCorePhysicalAddress;
} else if (MachineType == EFI_IMAGE_MACHINE_IA32 || MachineType == EFI_IMAGE_MACHINE_X64) {
if (MachineType == EFI_IMAGE_MACHINE_IA32 || MachineType == EFI_IMAGE_MACHINE_X64) {
if (PeiCorePhysicalAddress != 0) {
//
// Get the location to update
@ -2436,7 +2370,7 @@ Returns:
//
// Verify machine type is supported
//
if ((*MachineType != EFI_IMAGE_MACHINE_IA32) && (*MachineType != EFI_IMAGE_MACHINE_IA64) && (*MachineType != EFI_IMAGE_MACHINE_X64) && (*MachineType != EFI_IMAGE_MACHINE_EBC) &&
if ((*MachineType != EFI_IMAGE_MACHINE_IA32) && (*MachineType != EFI_IMAGE_MACHINE_X64) && (*MachineType != EFI_IMAGE_MACHINE_EBC) &&
(*MachineType != EFI_IMAGE_MACHINE_ARMT) && (*MachineType != EFI_IMAGE_MACHINE_AARCH64)) {
Error (NULL, 0, 3000, "Invalid", "Unrecognized machine type in the PE32 file.");
return EFI_UNSUPPORTED;

10
BaseTools/Source/C/GenFv/GenFvInternalLib.h
View File

@ -173,16 +173,6 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
#define IA32_SEC_CORE_ENTRY_OFFSET 0xD
//
// Defines to calculate the FIT table
//
#define IPF_FIT_ADDRESS_OFFSET 0x20
//
// Defines to calculate the offset for SALE_ENTRY
//
#define IPF_SALE_ENTRY_ADDRESS_OFFSET 0x18
//
// Symbol file definitions, current max size if 512K
//

5
BaseTools/Source/C/GenFw/Elf64Convert.c
View File

@ -486,7 +486,6 @@ ScanSections64 (
mNtHdrOffset = mCoffOffset;
switch (mEhdr->e_machine) {
case EM_X86_64:
case EM_IA_64:
case EM_AARCH64:
mCoffOffset += sizeof (EFI_IMAGE_NT_HEADERS64);
break;
@ -693,10 +692,6 @@ ScanSections64 (
NtHdr->Pe32Plus.FileHeader.Machine = EFI_IMAGE_MACHINE_X64;
NtHdr->Pe32Plus.OptionalHeader.Magic = EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC;
break;
case EM_IA_64:
NtHdr->Pe32Plus.FileHeader.Machine = EFI_IMAGE_MACHINE_IPF;
NtHdr->Pe32Plus.OptionalHeader.Magic = EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC;
break;
case EM_AARCH64:
NtHdr->Pe32Plus.FileHeader.Machine = EFI_IMAGE_MACHINE_AARCH64;
NtHdr->Pe32Plus.OptionalHeader.Magic = EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC;

6
BaseTools/Source/C/GenFw/GenFw.c
View File

@ -1014,7 +1014,7 @@ Returns:
//
// Update Image Base Address
//
if ((ImgHdr->Pe32.OptionalHeader.Magic == EFI_IMAGE_NT_OPTIONAL_HDR32_MAGIC) && (ImgHdr->Pe32.FileHeader.Machine != IMAGE_FILE_MACHINE_IA64)) {
if ((ImgHdr->Pe32.OptionalHeader.Magic == EFI_IMAGE_NT_OPTIONAL_HDR32_MAGIC)) {
ImgHdr->Pe32.OptionalHeader.ImageBase = (UINT32) NewPe32BaseAddress;
} else if (ImgHdr->Pe32Plus.OptionalHeader.Magic == EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC) {
ImgHdr->Pe32Plus.OptionalHeader.ImageBase = NewPe32BaseAddress;
@ -2180,7 +2180,7 @@ Returns:
// Set new base address into image
//
if (mOutImageType == FW_REBASE_IMAGE || mOutImageType == FW_SET_ADDRESS_IMAGE) {
if ((PeHdr->Pe32.OptionalHeader.Magic == EFI_IMAGE_NT_OPTIONAL_HDR32_MAGIC) && (PeHdr->Pe32.FileHeader.Machine != IMAGE_FILE_MACHINE_IA64)) {
if ((PeHdr->Pe32.OptionalHeader.Magic == EFI_IMAGE_NT_OPTIONAL_HDR32_MAGIC)) {
if (NewBaseAddress >= 0x100000000ULL) {
Error (NULL, 0, 3000, "Invalid", "New base address is larger than 4G for 32bit PE image");
goto Finish;
@ -2451,7 +2451,7 @@ Returns:
// Zero the .pdata section for X64 machine and don't check the Debug Directory is empty
// For Itaninum and X64 Image, remove .pdata section.
//
if ((!KeepExceptionTableFlag && PeHdr->Pe32.FileHeader.Machine == IMAGE_FILE_MACHINE_X64) || PeHdr->Pe32.FileHeader.Machine == IMAGE_FILE_MACHINE_IA64) {
if ((!KeepExceptionTableFlag && PeHdr->Pe32.FileHeader.Machine == IMAGE_FILE_MACHINE_X64)) {
if (Optional64->NumberOfRvaAndSizes > EFI_IMAGE_DIRECTORY_ENTRY_EXCEPTION &&
Optional64->DataDirectory[EFI_IMAGE_DIRECTORY_ENTRY_EXCEPTION].VirtualAddress != 0 &&
Optional64->DataDirectory[EFI_IMAGE_DIRECTORY_ENTRY_EXCEPTION].Size != 0) {

85
BaseTools/Source/C/GenFw/elf_common.h
View File

@ -170,7 +170,6 @@ typedef struct {
#define EM_H8_300H 47 /* Hitachi H8/300H. */
#define EM_H8S 48 /* Hitachi H8S. */
#define EM_H8_500 49 /* Hitachi H8/500. */
#define EM_IA_64 50 /* Intel IA-64 Processor. */
#define EM_MIPS_X 51 /* Stanford MIPS-X. */
#define EM_COLDFIRE 52 /* Motorola ColdFire. */
#define EM_68HC12 53 /* Motorola M68HC12. */
@ -775,90 +774,6 @@ typedef struct {
#define R_ARM_RPC24 254
#define R_ARM_RBASE 255
/* Name Value Field Calculation */
#define R_IA_64_NONE 0 /* None */
#define R_IA_64_IMM14 0x21 /* immediate14 S + A */
#define R_IA_64_IMM22 0x22 /* immediate22 S + A */
#define R_IA_64_IMM64 0x23 /* immediate64 S + A */
#define R_IA_64_DIR32MSB 0x24 /* word32 MSB S + A */
#define R_IA_64_DIR32LSB 0x25 /* word32 LSB S + A */
#define R_IA_64_DIR64MSB 0x26 /* word64 MSB S + A */
#define R_IA_64_DIR64LSB 0x27 /* word64 LSB S + A */
#define R_IA_64_GPREL22 0x2a /* immediate22 @gprel(S + A) */
#define R_IA_64_GPREL64I 0x2b /* immediate64 @gprel(S + A) */
#define R_IA_64_GPREL32MSB 0x2c /* word32 MSB @gprel(S + A) */
#define R_IA_64_GPREL32LSB 0x2d /* word32 LSB @gprel(S + A) */
#define R_IA_64_GPREL64MSB 0x2e /* word64 MSB @gprel(S + A) */
#define R_IA_64_GPREL64LSB 0x2f /* word64 LSB @gprel(S + A) */
#define R_IA_64_LTOFF22 0x32 /* immediate22 @ltoff(S + A) */
#define R_IA_64_LTOFF64I 0x33 /* immediate64 @ltoff(S + A) */
#define R_IA_64_PLTOFF22 0x3a /* immediate22 @pltoff(S + A) */
#define R_IA_64_PLTOFF64I 0x3b /* immediate64 @pltoff(S + A) */
#define R_IA_64_PLTOFF64MSB 0x3e /* word64 MSB @pltoff(S + A) */
#define R_IA_64_PLTOFF64LSB 0x3f /* word64 LSB @pltoff(S + A) */
#define R_IA_64_FPTR64I 0x43 /* immediate64 @fptr(S + A) */
#define R_IA_64_FPTR32MSB 0x44 /* word32 MSB @fptr(S + A) */
#define R_IA_64_FPTR32LSB 0x45 /* word32 LSB @fptr(S + A) */
#define R_IA_64_FPTR64MSB 0x46 /* word64 MSB @fptr(S + A) */
#define R_IA_64_FPTR64LSB 0x47 /* word64 LSB @fptr(S + A) */
#define R_IA_64_PCREL60B 0x48 /* immediate60 form1 S + A - P */
#define R_IA_64_PCREL21B 0x49 /* immediate21 form1 S + A - P */
#define R_IA_64_PCREL21M 0x4a /* immediate21 form2 S + A - P */
#define R_IA_64_PCREL21F 0x4b /* immediate21 form3 S + A - P */
#define R_IA_64_PCREL32MSB 0x4c /* word32 MSB S + A - P */
#define R_IA_64_PCREL32LSB 0x4d /* word32 LSB S + A - P */
#define R_IA_64_PCREL64MSB 0x4e /* word64 MSB S + A - P */
#define R_IA_64_PCREL64LSB 0x4f /* word64 LSB S + A - P */
#define R_IA_64_LTOFF_FPTR22 0x52 /* immediate22 @ltoff(@fptr(S + A)) */
#define R_IA_64_LTOFF_FPTR64I 0x53 /* immediate64 @ltoff(@fptr(S + A)) */
#define R_IA_64_LTOFF_FPTR32MSB 0x54 /* word32 MSB @ltoff(@fptr(S + A)) */
#define R_IA_64_LTOFF_FPTR32LSB 0x55 /* word32 LSB @ltoff(@fptr(S + A)) */
#define R_IA_64_LTOFF_FPTR64MSB 0x56 /* word64 MSB @ltoff(@fptr(S + A)) */
#define R_IA_64_LTOFF_FPTR64LSB 0x57 /* word64 LSB @ltoff(@fptr(S + A)) */
#define R_IA_64_SEGREL32MSB 0x5c /* word32 MSB @segrel(S + A) */
#define R_IA_64_SEGREL32LSB 0x5d /* word32 LSB @segrel(S + A) */
#define R_IA_64_SEGREL64MSB 0x5e /* word64 MSB @segrel(S + A) */
#define R_IA_64_SEGREL64LSB 0x5f /* word64 LSB @segrel(S + A) */
#define R_IA_64_SECREL32MSB 0x64 /* word32 MSB @secrel(S + A) */
#define R_IA_64_SECREL32LSB 0x65 /* word32 LSB @secrel(S + A) */
#define R_IA_64_SECREL64MSB 0x66 /* word64 MSB @secrel(S + A) */
#define R_IA_64_SECREL64LSB 0x67 /* word64 LSB @secrel(S + A) */
#define R_IA_64_REL32MSB 0x6c /* word32 MSB BD + A */
#define R_IA_64_REL32LSB 0x6d /* word32 LSB BD + A */
#define R_IA_64_REL64MSB 0x6e /* word64 MSB BD + A */
#define R_IA_64_REL64LSB 0x6f /* word64 LSB BD + A */
#define R_IA_64_LTV32MSB 0x74 /* word32 MSB S + A */
#define R_IA_64_LTV32LSB 0x75 /* word32 LSB S + A */
#define R_IA_64_LTV64MSB 0x76 /* word64 MSB S + A */
#define R_IA_64_LTV64LSB 0x77 /* word64 LSB S + A */
#define R_IA_64_PCREL21BI 0x79 /* immediate21 form1 S + A - P */
#define R_IA_64_PCREL22 0x7a /* immediate22 S + A - P */
#define R_IA_64_PCREL64I 0x7b /* immediate64 S + A - P */
#define R_IA_64_IPLTMSB 0x80 /* function descriptor MSB special */
#define R_IA_64_IPLTLSB 0x81 /* function descriptor LSB speciaal */
#define R_IA_64_SUB 0x85 /* immediate64 A - S */
#define R_IA_64_LTOFF22X 0x86 /* immediate22 special */
#define R_IA_64_LDXMOV 0x87 /* immediate22 special */
#define R_IA_64_TPREL14 0x91 /* imm14 @tprel(S + A) */
#define R_IA_64_TPREL22 0x92 /* imm22 @tprel(S + A) */
#define R_IA_64_TPREL64I 0x93 /* imm64 @tprel(S + A) */
#define R_IA_64_TPREL64MSB 0x96 /* word64 MSB @tprel(S + A) */
#define R_IA_64_TPREL64LSB 0x97 /* word64 LSB @tprel(S + A) */
#define R_IA_64_LTOFF_TPREL22 0x9a /* imm22 @ltoff(@tprel(S+A)) */
#define R_IA_64_DTPMOD64MSB 0xa6 /* word64 MSB @dtpmod(S + A) */
#define R_IA_64_DTPMOD64LSB 0xa7 /* word64 LSB @dtpmod(S + A) */
#define R_IA_64_LTOFF_DTPMOD22 0xaa /* imm22 @ltoff(@dtpmod(S+A)) */
#define R_IA_64_DTPREL14 0xb1 /* imm14 @dtprel(S + A) */
#define R_IA_64_DTPREL22 0xb2 /* imm22 @dtprel(S + A) */
#define R_IA_64_DTPREL64I 0xb3 /* imm64 @dtprel(S + A) */
#define R_IA_64_DTPREL32MSB 0xb4 /* word32 MSB @dtprel(S + A) */
#define R_IA_64_DTPREL32LSB 0xb5 /* word32 LSB @dtprel(S + A) */
#define R_IA_64_DTPREL64MSB 0xb6 /* word64 MSB @dtprel(S + A) */
#define R_IA_64_DTPREL64LSB 0xb7 /* word64 LSB @dtprel(S + A) */
#define R_IA_64_LTOFF_DTPREL22 0xba /* imm22 @ltoff(@dtprel(S+A)) */
#define R_PPC_NONE 0 /* No relocation. */
#define R_PPC_ADDR32 1
#define R_PPC_ADDR24 2

3
BaseTools/Source/C/Include/IndustryStandard/PeImage.h
View File

@ -42,7 +42,6 @@
// PE32+ Machine type for EFI images
//
#define IMAGE_FILE_MACHINE_I386 0x014c
#define IMAGE_FILE_MACHINE_IA64 0x0200
#define IMAGE_FILE_MACHINE_EBC 0x0EBC
#define IMAGE_FILE_MACHINE_X64 0x8664
#define IMAGE_FILE_MACHINE_ARM 0x01c0 // Thumb only
@ -53,8 +52,6 @@
// Support old names for backward compatible
//
#define EFI_IMAGE_MACHINE_IA32 IMAGE_FILE_MACHINE_I386
#define EFI_IMAGE_MACHINE_IA64 IMAGE_FILE_MACHINE_IA64
#define EFI_IMAGE_MACHINE_IPF IMAGE_FILE_MACHINE_IA64
#define EFI_IMAGE_MACHINE_EBC IMAGE_FILE_MACHINE_EBC
#define EFI_IMAGE_MACHINE_X64 IMAGE_FILE_MACHINE_X64
#define EFI_IMAGE_MACHINE_ARMT IMAGE_FILE_MACHINE_ARMT

1
BaseTools/Source/C/Makefiles/header.makefile
View File

@ -3,7 +3,6 @@
# The makefile can be invoked with
# HOST_ARCH = x86_64 or x64 for EM64T build
# HOST_ARCH = ia32 or IA32 for IA32 build
# HOST_ARCH = ia64 or IA64 for IA64 build
# HOST_ARCH = Arm or ARM for ARM build
#
# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>

2
BaseTools/Source/C/VolInfo/VolInfo.c
View File

@ -1573,7 +1573,7 @@ Returns:
//
// Update Image Base Address
//
if ((ImgHdr->Pe32.OptionalHeader.Magic == EFI_IMAGE_NT_OPTIONAL_HDR32_MAGIC) && (ImgHdr->Pe32.FileHeader.Machine != IMAGE_FILE_MACHINE_IA64)) {
if ((ImgHdr->Pe32.OptionalHeader.Magic == EFI_IMAGE_NT_OPTIONAL_HDR32_MAGIC)) {
ImgHdr->Pe32.OptionalHeader.ImageBase = (UINT32) NewPe32BaseAddress;
} else if (ImgHdr->Pe32Plus.OptionalHeader.Magic == EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC) {
ImgHdr->Pe32Plus.OptionalHeader.ImageBase = NewPe32BaseAddress;