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Print resource allocation/bar programming when PciBus driver does PCI BUS enumeration. 

Signed-off-by: niruiyu
Reviewed-by: rsun3

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12087 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
niruiyu 2011-08-04 09:08:09 +00:00
parent 48c0731857
commit 8db6a82c50
6 changed files with 326 additions and 290 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h
View File

@ -1,7 +1,7 @@
/** @file
Header files and data structures needed by PCI Bus module.
Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -32,6 +32,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#include <Protocol/IncompatiblePciDeviceSupport.h>
#include <Protocol/PciOverride.h>
#include <Protocol/PciEnumerationComplete.h>
#include <Protocol/DevicePathToText.h>
#include <Library/DebugLib.h>
#include <Library/UefiDriverEntryPoint.h>
@ -127,6 +128,12 @@ struct _PCI_BAR {
#define PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE BIT8
#define PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE BIT9
#define RB_IO_RANGE 1
#define RB_MEM32_RANGE 2
#define RB_PMEM32_RANGE 3
#define RB_MEM64_RANGE 4
#define RB_PMEM64_RANGE 5
#define PPB_BAR_0 0
#define PPB_BAR_1 1
#define PPB_IO_RANGE 2

3
MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
View File

@ -5,7 +5,7 @@
# space for these devices. Please use PCD feature flag PcdPciBusHotplugDeviceSupport to enable
# hot plug supporting.
#
# Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@ -97,6 +97,7 @@
gEfiPciRootBridgeIoProtocolGuid ## CONSUMED
gEfiIncompatiblePciDeviceSupportProtocolGuid ## CONSUMED
gEfiLoadFile2ProtocolGuid ## CONSUMED
gEfiDevicePathToTextProtocolGuid ## CONSUMED
[FeaturePcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport

154
MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
View File

@ -1,7 +1,7 @@
/** @file
PCI emumeration support functions implementation for PCI Bus module.
Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -14,6 +14,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#include "PciBus.h"
extern CHAR16 *mBarTypeStr[];
/**
This routine is used to check whether the pci device is present.
@ -211,6 +213,15 @@ PciSearchDevice (
PciIoDevice = NULL;
DEBUG ((
EFI_D_INFO,
"PciBus: Discovered %s @ [%02x|%02x|%02x]\n",
IS_PCI_BRIDGE (Pci) ? L"PPB" :
IS_CARDBUS_BRIDGE (Pci) ? L"P2C" :
L"PCI",
Bus, Device, Func
));
if (!IS_PCI_BRIDGE (Pci)) {
if (IS_CARDBUS_BRIDGE (Pci)) {
@ -304,6 +315,46 @@ PciSearchDevice (
return EFI_SUCCESS;
}
/**
Dump the PCI BAR information.
@param PciIoDevice PCI IO instance.
**/
VOID
DumpPciBars (
IN PCI_IO_DEVICE *PciIoDevice
)
{
UINTN Index;
for (Index = 0; Index < PCI_MAX_BAR; Index++) {
if (PciIoDevice->PciBar[Index].BarType == PciBarTypeUnknown) {
continue;
}
DEBUG ((
EFI_D_INFO,
" BAR[%d]: Type = %s; Alignment = 0x%x;\tLength = 0x%x;\tOffset = 0x%02x\n",
Index, mBarTypeStr[MIN (PciIoDevice->PciBar[Index].BarType, PciBarTypeMaxType)],
PciIoDevice->PciBar[Index].Alignment, PciIoDevice->PciBar[Index].Length, PciIoDevice->PciBar[Index].Offset
));
}
for (Index = 0; Index < PCI_MAX_BAR; Index++) {
if ((PciIoDevice->VfPciBar[Index].BarType == PciBarTypeUnknown) && (PciIoDevice->VfPciBar[Index].Length == 0)) {
continue;
}
DEBUG ((
EFI_D_INFO,
" VFBAR[%d]: Type = %s; Alignment = 0x%x;\tLength = 0x%x;\tOffset = 0x%02x\n",
Index, mBarTypeStr[MIN (PciIoDevice->VfPciBar[Index].BarType, PciBarTypeMaxType)],
PciIoDevice->VfPciBar[Index].Alignment, PciIoDevice->VfPciBar[Index].Length, PciIoDevice->VfPciBar[Index].Offset
));
}
DEBUG ((EFI_D_INFO, "\n"));
}
/**
Create PCI device instance for PCI device.
@ -377,6 +428,8 @@ GatherDeviceInfo (
Offset = PciIovParseVfBar (PciIoDevice, Offset, BarIndex);
}
}
DEBUG_CODE (DumpPciBars (PciIoDevice););
return PciIoDevice;
}
@ -529,6 +582,8 @@ GatherPpbInfo (
GetResourcePaddingPpb (PciIoDevice);
DEBUG_CODE (DumpPciBars (PciIoDevice););
return PciIoDevice;
}
@ -598,6 +653,8 @@ GatherP2CInfo (
EFI_BRIDGE_PMEM32_DECODE_SUPPORTED |
EFI_BRIDGE_IO32_DECODE_SUPPORTED;
DEBUG_CODE (DumpPciBars (PciIoDevice););
return PciIoDevice;
}
@ -2035,22 +2092,15 @@ CreatePciIoDevice (
);
DEBUG ((
EFI_D_INFO,
"PCI B%x.D%x.F%x - ARI forwarding enabled\n",
(UINTN)Bridge->BusNumber,
(UINTN)Bridge->DeviceNumber,
(UINTN)Bridge->FunctionNumber
" ARI: forwarding enabled for PPB[%02x:%02x:%02x]\n",
Bridge->BusNumber,
Bridge->DeviceNumber,
Bridge->FunctionNumber
));
}
}
DEBUG ((
EFI_D_INFO,
"PCI ARI B%x.D%x.F%x - ARI Cap offset - 0x%x\n",
(UINTN)Bus,
(UINTN)Device,
(UINTN)Func,
(UINTN)PciIoDevice->AriCapabilityOffset
));
DEBUG ((EFI_D_INFO, " ARI: CapOffset = 0x%x\n", PciIoDevice->AriCapabilityOffset));
}
}
@ -2066,6 +2116,7 @@ CreatePciIoDevice (
NULL
);
if (!EFI_ERROR (Status)) {
UINT32 SupportedPageSize;
UINT16 VFStride;
UINT16 FirstVFOffset;
UINT16 Data16;
@ -2102,18 +2153,9 @@ CreatePciIoDevice (
EfiPciIoWidthUint32,
PciIoDevice->SrIovCapabilityOffset + EFI_PCIE_CAPABILITY_ID_SRIOV_SUPPORTED_PAGE_SIZE,
1,
&PciIoDevice->SystemPageSize
&SupportedPageSize
);
DEBUG ((
EFI_D_INFO,
"PCI SR-IOV B%x.D%x.F%x - SupportedPageSize - 0x%x\n",
(UINTN)Bus,
(UINTN)Device,
(UINTN)Func,
PciIoDevice->SystemPageSize
));
PciIoDevice->SystemPageSize = (PcdGet32 (PcdSrIovSystemPageSize) & PciIoDevice->SystemPageSize);
PciIoDevice->SystemPageSize = (PcdGet32 (PcdSrIovSystemPageSize) & SupportedPageSize);
ASSERT (PciIoDevice->SystemPageSize != 0);
PciIo->Pci.Write (
@ -2123,14 +2165,6 @@ CreatePciIoDevice (
1,
&PciIoDevice->SystemPageSize
);
DEBUG ((
EFI_D_INFO,
"PCI SR-IOV B%x.D%x.F%x - SystemPageSize - 0x%x\n",
(UINTN)Bus,
(UINTN)Device,
(UINTN)Func,
PciIoDevice->SystemPageSize
));
//
// Adjust SystemPageSize for Alignment usage later
//
@ -2150,15 +2184,6 @@ CreatePciIoDevice (
1,
&FirstVFOffset
);
DEBUG ((
EFI_D_INFO,
"PCI SR-IOV B%x.D%x.F%x - FirstVFOffset - 0x%x\n",
(UINTN)Bus,
(UINTN)Device,
(UINTN)Func,
(UINTN)FirstVFOffset
));
PciIo->Pci.Read (
PciIo,
EfiPciIoWidthUint16,
@ -2166,15 +2191,6 @@ CreatePciIoDevice (
1,
&PciIoDevice->InitialVFs
);
DEBUG ((
EFI_D_INFO,
"PCI SR-IOV B%x.D%x.F%x - InitialVFs - 0x%x\n",
(UINTN)Bus,
(UINTN)Device,
(UINTN)Func,
(UINTN)PciIoDevice->InitialVFs
));
PciIo->Pci.Read (
PciIo,
EfiPciIoWidthUint16,
@ -2182,15 +2198,6 @@ CreatePciIoDevice (
1,
&VFStride
);
DEBUG ((
EFI_D_INFO,
"PCI SR-IOV B%x.D%x.F%x - VFStride - 0x%x\n",
(UINTN)Bus,
(UINTN)Device,
(UINTN)Func,
(UINTN)VFStride
));
//
// Calculate LastVF
//
@ -2201,22 +2208,16 @@ CreatePciIoDevice (
// Calculate ReservedBusNum for this PF
//
PciIoDevice->ReservedBusNum = (UINT16)(EFI_PCI_BUS_OF_RID (LastVF) - Bus + 1);
DEBUG ((
EFI_D_INFO,
"PCI SR-IOV B%x.D%x.F%x - reserved bus number - 0x%x\n",
(UINTN)Bus,
(UINTN)Device,
(UINTN)Func,
(UINTN)PciIoDevice->ReservedBusNum
));
DEBUG ((
EFI_D_INFO,
"PCI SR-IOV B%x.D%x.F%x - SRIOV Cap offset - 0x%x\n",
(UINTN)Bus,
(UINTN)Device,
(UINTN)Func,
(UINTN)PciIoDevice->SrIovCapabilityOffset
" SR-IOV: SupportedPageSize = 0x%x; SystemPageSize = 0x%x; FirstVFOffset = 0x%x;\n",
SupportedPageSize, PciIoDevice->SystemPageSize >> 12, FirstVFOffset
));
DEBUG ((
EFI_D_INFO,
" InitialVFs = 0x%x; ReservedBusNum = 0x%x; CapOffset = 0x%x\n",
PciIoDevice->InitialVFs, PciIoDevice->ReservedBusNum, PciIoDevice->SrIovCapabilityOffset
));
}
}
@ -2229,14 +2230,7 @@ CreatePciIoDevice (
NULL
);
if (!EFI_ERROR (Status)) {
DEBUG ((
EFI_D_INFO,
"PCI MR-IOV B%x.D%x.F%x - MRIOV Cap offset - 0x%x\n",
(UINTN)Bus,
(UINTN)Device,
(UINTN)Func,
(UINTN)PciIoDevice->MrIovCapabilityOffset
));
DEBUG ((EFI_D_INFO, " MR-IOV: CapOffset = 0x%x\n", PciIoDevice->MrIovCapabilityOffset));
}
}

260
MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c
View File

@ -1,7 +1,7 @@
/** @file
Internal library implementation for PCI Bus module.
Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -14,6 +14,19 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#include "PciBus.h"
GLOBAL_REMOVE_IF_UNREFERENCED
CHAR16 *mBarTypeStr[] = {
L"Unknow",
L" Io16",
L" Io32",
L" Mem32",
L"PMem32",
L" Mem64",
L"PMem64",
L" Io",
L" Mem",
L"Unknow"
};
/**
Retrieve the PCI Card device BAR information via PciIo interface.
@ -153,6 +166,200 @@ RemoveRejectedPciDevices (
}
}
/**
Dump the resourc map of the bridge device.
@param[in] BridgeResource Resource descriptor of the bridge device.
**/
VOID
DumpBridgeResource (
IN PCI_RESOURCE_NODE *BridgeResource
)
{
LIST_ENTRY *Link;
PCI_RESOURCE_NODE *Resource;
PCI_BAR *Bar;
if ((BridgeResource != NULL) && (BridgeResource->Length != 0)) {
DEBUG ((
EFI_D_INFO, "Type = %s; Base = 0x%x;\tLength = 0x%x;\tAlignment = 0x%x\n",
mBarTypeStr[MIN (BridgeResource->ResType, PciBarTypeMaxType)],
BridgeResource->PciDev->PciBar[BridgeResource->Bar].BaseAddress,
BridgeResource->Length, BridgeResource->Alignment
));
for ( Link = BridgeResource->ChildList.ForwardLink
; Link != &BridgeResource->ChildList
; Link = Link->ForwardLink
) {
Resource = RESOURCE_NODE_FROM_LINK (Link);
if (Resource->ResourceUsage == PciResUsageTypical) {
Bar = Resource->Virtual ? Resource->PciDev->VfPciBar : Resource->PciDev->PciBar;
DEBUG ((
EFI_D_INFO, " Base = 0x%x;\tLength = 0x%x;\tAlignment = 0x%x;\tOwner = %s ",
Bar[Resource->Bar].BaseAddress, Resource->Length, Resource->Alignment,
IS_PCI_BRIDGE (&Resource->PciDev->Pci) ? L"PPB" :
IS_CARDBUS_BRIDGE (&Resource->PciDev->Pci) ? L"P2C" :
L"PCI"
));
if ((!IS_PCI_BRIDGE (&Resource->PciDev->Pci) && !IS_CARDBUS_BRIDGE (&Resource->PciDev->Pci)) ||
(IS_PCI_BRIDGE (&Resource->PciDev->Pci) && (Resource->Bar < PPB_IO_RANGE)) ||
(IS_CARDBUS_BRIDGE (&Resource->PciDev->Pci) && (Resource->Bar < P2C_MEM_1))
) {
//
// The resource requirement comes from the device itself.
//
DEBUG ((
EFI_D_INFO, " [%02x|%02x|%02x:%02x]\n",
Resource->PciDev->BusNumber, Resource->PciDev->DeviceNumber,
Resource->PciDev->FunctionNumber, Bar[Resource->Bar].Offset
));
} else {
//
// The resource requirement comes from the subordinate devices.
//
DEBUG ((
EFI_D_INFO, " [%02x|%02x|%02x:**]\n",
Resource->PciDev->BusNumber, Resource->PciDev->DeviceNumber,
Resource->PciDev->FunctionNumber
));
}
} else {
DEBUG ((EFI_D_INFO, " Padding:Length = 0x%x;\tAlignment = 0x%x\n", Resource->Length, Resource->Alignment));
}
}
}
}
/**
Find the corresponding resource node for the Device in child list of BridgeResource.
@param[in] Device Pointer to PCI_IO_DEVICE.
@param[in] BridgeResource Pointer to PCI_RESOURCE_NODE.
@return !NULL The corresponding resource node for the Device.
@return NULL No corresponding resource node for the Device.
**/
PCI_RESOURCE_NODE *
FindResourceNode (
IN PCI_IO_DEVICE *Device,
IN PCI_RESOURCE_NODE *BridgeResource
)
{
LIST_ENTRY *Link;
PCI_RESOURCE_NODE *Resource;
for ( Link = BridgeResource->ChildList.ForwardLink
; Link != &BridgeResource->ChildList
; Link = Link->ForwardLink
) {
Resource = RESOURCE_NODE_FROM_LINK (Link);
if (Resource->PciDev == Device) {
return Resource;
}
}
return NULL;
}
/**
Dump the resource map of all the devices under Bridge.
@param[in] Bridge Bridge device instance.
@param[in] IoNode IO resource descriptor for the bridge device.
@param[in] Mem32Node Mem32 resource descriptor for the bridge device.
@param[in] PMem32Node PMem32 resource descriptor for the bridge device.
@param[in] Mem64Node Mem64 resource descriptor for the bridge device.
@param[in] PMem64Node PMem64 resource descriptor for the bridge device.
**/
VOID
DumpResourceMap (
IN PCI_IO_DEVICE *Bridge,
IN PCI_RESOURCE_NODE *IoNode,
IN PCI_RESOURCE_NODE *Mem32Node,
IN PCI_RESOURCE_NODE *PMem32Node,
IN PCI_RESOURCE_NODE *Mem64Node,
IN PCI_RESOURCE_NODE *PMem64Node
)
{
EFI_STATUS Status;
LIST_ENTRY *Link;
PCI_IO_DEVICE *Device;
PCI_RESOURCE_NODE *ChildIoNode;
PCI_RESOURCE_NODE *ChildMem32Node;
PCI_RESOURCE_NODE *ChildPMem32Node;
PCI_RESOURCE_NODE *ChildMem64Node;
PCI_RESOURCE_NODE *ChildPMem64Node;
EFI_DEVICE_PATH_TO_TEXT_PROTOCOL *ToText;
CHAR16 *Str;
DEBUG ((EFI_D_INFO, "PciBus: Resource Map for "));
Status = gBS->OpenProtocol (
Bridge->Handle,
&gEfiPciRootBridgeIoProtocolGuid,
NULL,
NULL,
NULL,
EFI_OPEN_PROTOCOL_TEST_PROTOCOL
);
if (EFI_ERROR (Status)) {
DEBUG ((
EFI_D_INFO, "Bridge [%02x|%02x|%02x]\n",
Bridge->BusNumber, Bridge->DeviceNumber, Bridge->FunctionNumber
));
} else {
Status = gBS->LocateProtocol (
&gEfiDevicePathToTextProtocolGuid,
NULL,
(VOID **) &ToText
);
Str = NULL;
if (!EFI_ERROR (Status)) {
Str = ToText->ConvertDevicePathToText (
DevicePathFromHandle (Bridge->Handle),
FALSE,
FALSE
);
}
DEBUG ((EFI_D_INFO, "Root Bridge %s\n", Str != NULL ? Str : L""));
if (Str != NULL) {
FreePool (Str);
}
}
DumpBridgeResource (IoNode);
DumpBridgeResource (Mem32Node);
DumpBridgeResource (PMem32Node);
DumpBridgeResource (Mem64Node);
DumpBridgeResource (PMem64Node);
DEBUG ((EFI_D_INFO, "\n"));
for ( Link = Bridge->ChildList.ForwardLink
; Link != &Bridge->ChildList
; Link = Link->ForwardLink
) {
Device = PCI_IO_DEVICE_FROM_LINK (Link);
if (IS_PCI_BRIDGE (&Device->Pci)) {
ChildIoNode = (IoNode == NULL ? NULL : FindResourceNode (Device, IoNode));
ChildMem32Node = (Mem32Node == NULL ? NULL : FindResourceNode (Device, Mem32Node));
ChildPMem32Node = (PMem32Node == NULL ? NULL : FindResourceNode (Device, PMem32Node));
ChildMem64Node = (Mem64Node == NULL ? NULL : FindResourceNode (Device, Mem64Node));
ChildPMem64Node = (PMem64Node == NULL ? NULL : FindResourceNode (Device, PMem64Node));
DumpResourceMap (
Device,
ChildIoNode,
ChildMem32Node,
ChildPMem32Node,
ChildMem64Node,
ChildPMem64Node
);
}
}
}
/**
Submits the I/O and memory resource requirements for the specified PCI Host Bridge.
@ -244,7 +451,7 @@ PciHostBridgeResourceAllocator (
RootBridgeDev,
0,
FeaturePcdGet (PcdPciBridgeIoAlignmentProbe) ? 0x1FF: 0xFFF,
0,
RB_IO_RANGE,
PciBarTypeIo16,
PciResUsageTypical
);
@ -253,7 +460,7 @@ PciHostBridgeResourceAllocator (
RootBridgeDev,
0,
0xFFFFF,
0,
RB_MEM32_RANGE,
PciBarTypeMem32,
PciResUsageTypical
);
@ -262,7 +469,7 @@ PciHostBridgeResourceAllocator (
RootBridgeDev,
0,
0xFFFFF,
0,
RB_PMEM32_RANGE,
PciBarTypePMem32,
PciResUsageTypical
);
@ -271,7 +478,7 @@ PciHostBridgeResourceAllocator (
RootBridgeDev,
0,
0xFFFFF,
0,
RB_MEM64_RANGE,
PciBarTypeMem64,
PciResUsageTypical
);
@ -280,7 +487,7 @@ PciHostBridgeResourceAllocator (
RootBridgeDev,
0,
0xFFFFF,
0,
RB_PMEM64_RANGE,
PciBarTypePMem64,
PciResUsageTypical
);
@ -597,19 +804,11 @@ PciHostBridgeResourceAllocator (
// Create the entire system resource map from the information collected by
// enumerator. Several resource tree was created
//
GetResourceMap (
RootBridgeDev,
&IoBridge,
&Mem32Bridge,
&PMem32Bridge,
&Mem64Bridge,
&PMem64Bridge,
&IoPool,
&Mem32Pool,
&PMem32Pool,
&Mem64Pool,
&PMem64Pool
);
IoBridge = FindResourceNode (RootBridgeDev, &IoPool);
Mem32Bridge = FindResourceNode (RootBridgeDev, &Mem32Pool);
PMem32Bridge = FindResourceNode (RootBridgeDev, &PMem32Pool);
Mem64Bridge = FindResourceNode (RootBridgeDev, &Mem64Pool);
PMem64Bridge = FindResourceNode (RootBridgeDev, &PMem64Pool);
//
// Program IO resources
@ -651,6 +850,26 @@ PciHostBridgeResourceAllocator (
PMem64Bridge
);
IoBridge ->PciDev->PciBar[IoBridge ->Bar].BaseAddress = IoBase;
Mem32Bridge ->PciDev->PciBar[Mem32Bridge ->Bar].BaseAddress = Mem32Base;
PMem32Bridge->PciDev->PciBar[PMem32Bridge->Bar].BaseAddress = PMem32Base;
Mem64Bridge ->PciDev->PciBar[Mem64Bridge ->Bar].BaseAddress = Mem64Base;
PMem64Bridge->PciDev->PciBar[PMem64Bridge->Bar].BaseAddress = PMem64Base;
//
// Dump the resource map for current root bridge
//
DEBUG_CODE (
DumpResourceMap (
RootBridgeDev,
IoBridge,
Mem32Bridge,
PMem32Bridge,
Mem64Bridge,
PMem64Bridge
);
);
FreePool (AcpiConfig);
}
@ -741,8 +960,6 @@ PciScanBus (
continue;
}
DEBUG((EFI_D_INFO, "Found DEV(%02d,%02d,%02d)\n", StartBusNumber, Device, Func ));
//
// Get the PCI device information
//
@ -930,7 +1147,6 @@ PciScanBus (
EfiPciBeforeChildBusEnumeration
);
DEBUG((EFI_D_INFO, "Scan PPB(%02d,%02d,%02d)\n", PciDevice->BusNumber, PciDevice->DeviceNumber,PciDevice->FunctionNumber));
Status = PciScanBus (
PciDevice,
(UINT8) (SecondBus),

152
MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c
View File

@ -1,7 +1,7 @@
/** @file
PCI resouces support functions implemntation for PCI Bus module.
Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -724,17 +724,6 @@ CreateVfResourceNode (
{
PCI_RESOURCE_NODE *Node;
DEBUG ((
EFI_D_INFO,
"PCI-IOV B%x.D%x.F%x - VfResource (Bar - 0x%x) (Type - 0x%x) (Length - 0x%x)\n",
(UINTN)PciDev->BusNumber,
(UINTN)PciDev->DeviceNumber,
(UINTN)PciDev->FunctionNumber,
(UINTN)Bar,
(UINTN)ResType,
(UINTN)Length
));
Node = CreateResourceNode (PciDev, Length, Alignment, Bar, ResType, ResUsage);
if (Node == NULL) {
return Node;
@ -1403,17 +1392,6 @@ ProgramVfBar (
);
Node->PciDev->VfPciBar[Node->Bar].BaseAddress = Address;
DEBUG ((
EFI_D_INFO,
"PCI-IOV B%x.D%x.F%x - VF Bar (Offset - 0x%x) 32Mem (Address - 0x%x)\n",
(UINTN)Node->PciDev->BusNumber,
(UINTN)Node->PciDev->DeviceNumber,
(UINTN)Node->PciDev->FunctionNumber,
(UINTN)(Node->PciDev->VfPciBar[Node->Bar]).Offset,
(UINTN)Address
));
break;
case PciBarTypeMem64:
@ -1440,17 +1418,6 @@ ProgramVfBar (
);
Node->PciDev->VfPciBar[Node->Bar].BaseAddress = Address;
DEBUG ((
EFI_D_INFO,
"PCI-IOV B%x.D%x.F%x - VF Bar (Offset - 0x%x) 64Mem (Address - 0x%lx)\n",
(UINTN)Node->PciDev->BusNumber,
(UINTN)Node->PciDev->DeviceNumber,
(UINTN)Node->PciDev->FunctionNumber,
(UINTN)(Node->PciDev->VfPciBar[Node->Bar]).Offset,
(UINT64)Address
));
break;
case PciBarTypeIo16:
@ -1727,123 +1694,6 @@ InitializeResourcePool (
InitializeListHead (&ResourcePool->ChildList);
}
/**
Get all resource information for given Pci device.
@param PciDev Pci device instance.
@param IoBridge Io resource node.
@param Mem32Bridge 32-bit memory node.
@param PMem32Bridge 32-bit Pmemory node.
@param Mem64Bridge 64-bit memory node.
@param PMem64Bridge 64-bit PMemory node.
@param IoPool Link list header for Io resource.
@param Mem32Pool Link list header for 32-bit memory.
@param PMem32Pool Link list header for 32-bit Prefetchable memory.
@param Mem64Pool Link list header for 64-bit memory.
@param PMem64Pool Link list header for 64-bit Prefetchable memory.
**/
VOID
GetResourceMap (
IN PCI_IO_DEVICE *PciDev,
IN PCI_RESOURCE_NODE **IoBridge,
IN PCI_RESOURCE_NODE **Mem32Bridge,
IN PCI_RESOURCE_NODE **PMem32Bridge,
IN PCI_RESOURCE_NODE **Mem64Bridge,
IN PCI_RESOURCE_NODE **PMem64Bridge,
IN PCI_RESOURCE_NODE *IoPool,
IN PCI_RESOURCE_NODE *Mem32Pool,
IN PCI_RESOURCE_NODE *PMem32Pool,
IN PCI_RESOURCE_NODE *Mem64Pool,
IN PCI_RESOURCE_NODE *PMem64Pool
)
{
PCI_RESOURCE_NODE *Temp;
LIST_ENTRY *CurrentLink;
CurrentLink = IoPool->ChildList.ForwardLink;
//
// Get Io resource map
//
while (CurrentLink != &IoPool->ChildList) {
Temp = RESOURCE_NODE_FROM_LINK (CurrentLink);
if (Temp->PciDev == PciDev) {
*IoBridge = Temp;
}
CurrentLink = CurrentLink->ForwardLink;
}
//
// Get Mem32 resource map
//
CurrentLink = Mem32Pool->ChildList.ForwardLink;
while (CurrentLink != &Mem32Pool->ChildList) {
Temp = RESOURCE_NODE_FROM_LINK (CurrentLink);
if (Temp->PciDev == PciDev) {
*Mem32Bridge = Temp;
}
CurrentLink = CurrentLink->ForwardLink;
}
//
// Get Pmem32 resource map
//
CurrentLink = PMem32Pool->ChildList.ForwardLink;
while (CurrentLink != &PMem32Pool->ChildList) {
Temp = RESOURCE_NODE_FROM_LINK (CurrentLink);
if (Temp->PciDev == PciDev) {
*PMem32Bridge = Temp;
}
CurrentLink = CurrentLink->ForwardLink;
}
//
// Get Mem64 resource map
//
CurrentLink = Mem64Pool->ChildList.ForwardLink;
while (CurrentLink != &Mem64Pool->ChildList) {
Temp = RESOURCE_NODE_FROM_LINK (CurrentLink);
if (Temp->PciDev == PciDev) {
*Mem64Bridge = Temp;
}
CurrentLink = CurrentLink->ForwardLink;
}
//
// Get Pmem64 resource map
//
CurrentLink = PMem64Pool->ChildList.ForwardLink;
while (CurrentLink != &PMem64Pool->ChildList) {
Temp = RESOURCE_NODE_FROM_LINK (CurrentLink);
if (Temp->PciDev == PciDev) {
*PMem64Bridge = Temp;
}
CurrentLink = CurrentLink->ForwardLink;
}
}
/**
Destory given resource tree.

38
MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.h
View File

@ -1,7 +1,7 @@
/** @file
PCI resouces support functions declaration for PCI Bus module.
Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -16,9 +16,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#define _EFI_PCI_RESOURCE_SUPPORT_H_
typedef enum {
PciResUsageTypical = 0,
PciResUsagePadding,
PciResUsageOptionRomProcessing
PciResUsageTypical,
PciResUsagePadding
} PCI_RESOURCE_USAGE;
#define PCI_RESOURCE_SIGNATURE SIGNATURE_32 ('p', 'c', 'r', 'c')
@ -382,37 +381,6 @@ InitializeResourcePool (
IN PCI_BAR_TYPE ResourceType
);
/**
Get all resource information for given Pci device.
@param PciDev Pci device instance.
@param IoBridge Io resource node.
@param Mem32Bridge 32-bit memory node.
@param PMem32Bridge 32-bit Pmemory node.
@param Mem64Bridge 64-bit memory node.
@param PMem64Bridge 64-bit PMemory node.
@param IoPool Link list header for Io resource.
@param Mem32Pool Link list header for 32-bit memory.
@param PMem32Pool Link list header for 32-bit Prefetchable memory.
@param Mem64Pool Link list header for 64-bit memory.
@param PMem64Pool Link list header for 64-bit Prefetchable memory.
**/
VOID
GetResourceMap (
IN PCI_IO_DEVICE *PciDev,
IN PCI_RESOURCE_NODE **IoBridge,
IN PCI_RESOURCE_NODE **Mem32Bridge,
IN PCI_RESOURCE_NODE **PMem32Bridge,
IN PCI_RESOURCE_NODE **Mem64Bridge,
IN PCI_RESOURCE_NODE **PMem64Bridge,
IN PCI_RESOURCE_NODE *IoPool,
IN PCI_RESOURCE_NODE *Mem32Pool,
IN PCI_RESOURCE_NODE *PMem32Pool,
IN PCI_RESOURCE_NODE *Mem64Pool,
IN PCI_RESOURCE_NODE *PMem64Pool
);
/**
Destory given resource tree.