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UefiCpuPkg/CpuCacheInfoLib: Correct logical for identifying cache type 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3265

Correct the logical for identifying "Direct mapped" cache type.

Signed-off-by: Jason Lou <yun.lou@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
This commit is contained in:
Jason 2021-08-13 10:05:28 +08:00 committed by mergify[bot]
parent ef56f55d19
commit 8dd4fc5be6
1 changed files with 1 additions and 1 deletions
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UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c
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@ -237,7 +237,7 @@ CpuCacheInfoCollectCoreAndCacheData (
CacheData[CacheParamLeafIndex].CacheType = (UINT8)CacheParamEax.Bits.CacheType;
CacheData[CacheParamLeafIndex].CacheWays = (UINT16)CacheParamEbx.Bits.Ways;
CacheData[CacheParamLeafIndex].FullyAssociativeCache = (UINT8)CacheParamEax.Bits.FullyAssociativeCache;
CacheData[CacheParamLeafIndex].DirectMappedCache = (UINT8)CacheParamEdx.Bits.ComplexCacheIndexing;
CacheData[CacheParamLeafIndex].DirectMappedCache = (UINT8)(CacheParamEdx.Bits.ComplexCacheIndexing == 0);
CacheData[CacheParamLeafIndex].CacheShareBits = (UINT16)CacheParamEax.Bits.MaximumAddressableIdsForLogicalProcessors;
CacheData[CacheParamLeafIndex].CacheSizeinKB = (CacheParamEbx.Bits.Ways + 1) *
(CacheParamEbx.Bits.LinePartitions + 1) * (CacheParamEbx.Bits.LineSize + 1) * (CacheParamEcx + 1) / SIZE_1KB;