mirror of https://github.com/acidanthera/audk.git
Resolved several warnings generated by GCC.
In PcatPciRootBridge.c -> GetPciExpressBaseAddressForRootBridge, fixed a hang condition if the PCI Express Base Address HOB is not present. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@6684 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
jljusten
parent
d4f59c13fb
commit
8e53d24672
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@ -1,6 +1,6 @@
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/*++
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Copyright (c) 2006, Intel Corporation
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Copyright (c) 2006 - 2008, Intel Corporation
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All rights reserved. This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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@ -141,7 +141,7 @@ Returns:
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Status = Private->PciRootBridgeIo->CopyMem (
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Private->PciRootBridgeIo,
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(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
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(UINT64) Buffer,
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(UINT64)(UINTN) Buffer,
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Address,
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Count
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);
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@ -206,7 +206,7 @@ Returns:
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Private->PciRootBridgeIo,
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(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
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Address,
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(UINT64) Buffer,
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(UINT64)(UINTN) Buffer,
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Count
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);
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} else {
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@ -1,6 +1,6 @@
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/*++
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Copyright (c) 2005 - 2006, Intel Corporation
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Copyright (c) 2005 - 2008, Intel Corporation
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All rights reserved. This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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@ -608,7 +608,7 @@ ScanPciRootBridgeForRoms(
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mPciOptionRomTableInstalled = TRUE;
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}
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Status = IoDev->Configuration(IoDev, &Descriptors);
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Status = IoDev->Configuration(IoDev, (VOID **)&Descriptors);
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if (EFI_ERROR (Status) || Descriptors == NULL) {
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return EFI_NOT_FOUND;
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}
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@ -632,7 +632,7 @@ ScanPciRootBridgeForRoms(
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//
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// Find Memory Descriptors that are less than 4GB, so the PPB Memory Window can be used for downstream devices
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//
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if (Descriptors->AddrRangeMax < 0x100000000) {
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if (Descriptors->AddrRangeMax < 0x100000000ULL) {
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//
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// Find the largest Non-Prefetchable Memory Descriptor that is less than 4GB
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//
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@ -679,7 +679,7 @@ ScanPciRootBridgeForRoms(
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Status = gBS->AllocatePool(
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EfiBootServicesData,
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sizeof(UINT16) * (MaxBus - MinBus + 1) * (PCI_MAX_DEVICE+1) * (PCI_MAX_FUNC+1),
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&Context.CommandRegisterBuffer
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(VOID **)&Context.CommandRegisterBuffer
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);
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if (EFI_ERROR (Status)) {
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@ -1,6 +1,6 @@
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/*++
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Copyright (c) 2005 - 2006, Intel Corporation
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Copyright (c) 2005 - 2008, Intel Corporation
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All rights reserved. This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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@ -62,7 +62,7 @@ Returns:
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//
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// Initialize gCpuIo now since the chipset init code requires it.
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//
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Status = gBS->LocateProtocol (&gEfiCpuIoProtocolGuid, NULL, &gCpuIo);
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Status = gBS->LocateProtocol (&gEfiCpuIoProtocolGuid, NULL, (VOID **)&gCpuIo);
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ASSERT_EFI_ERROR (Status);
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//
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@ -79,7 +79,7 @@ Returns:
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Status = gBS->AllocatePool(
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EfiBootServicesData,
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sizeof (PCAT_PCI_ROOT_BRIDGE_INSTANCE),
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&PrivateData
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(VOID **)&PrivateData
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);
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if (EFI_ERROR (Status)) {
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goto Done;
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@ -104,10 +104,10 @@ Returns:
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PrivateData->IoBase = 0xffffffff;
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PrivateData->MemBase = 0xffffffff;
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PrivateData->Mem32Base = 0xffffffffffffffff;
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PrivateData->Pmem32Base = 0xffffffffffffffff;
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PrivateData->Mem64Base = 0xffffffffffffffff;
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PrivateData->Pmem64Base = 0xffffffffffffffff;
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PrivateData->Mem32Base = 0xffffffffffffffffULL;
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PrivateData->Pmem32Base = 0xffffffffffffffffULL;
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PrivateData->Mem64Base = 0xffffffffffffffffULL;
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PrivateData->Pmem64Base = 0xffffffffffffffffULL;
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//
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// The default mechanism for performing PCI Configuration cycles is to
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@ -217,6 +217,7 @@ Returns:
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break;
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}
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//
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// Increment the number of PCI device found on the primary bus of the PCI root bridge
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//
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@ -592,7 +593,7 @@ Returns:
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Status = gBS->AllocatePool (
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EfiBootServicesData,
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sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR),
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&PrivateData->Configuration
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(VOID **)&PrivateData->Configuration
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);
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if (EFI_ERROR (Status )) {
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return Status;
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@ -621,7 +622,7 @@ Returns:
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Status = gBS->AllocatePool (
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EfiBootServicesData,
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sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * NumConfig + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR),
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&PrivateData->Configuration
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(VOID **)&PrivateData->Configuration
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);
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if (EFI_ERROR (Status )) {
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return Status;
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@ -974,24 +975,14 @@ Returns:
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UINTN BufferSize;
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UINT32 Index;
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UINT32 Number;
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VOID *HobList;
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EFI_STATUS Status;
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EFI_PEI_HOB_POINTERS GuidHob;
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//
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// Get Hob List from configuration table
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//
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Status = EfiGetSystemConfigurationTable (&gEfiHobListGuid, &HobList);
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if (EFI_ERROR (Status)) {
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return 0;
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}
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//
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// Get PciExpressAddressInfo Hob
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//
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PciExpressBaseAddressInfo = NULL;
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BufferSize = 0;
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GuidHob.Raw = GetNextGuidHob (&gEfiPciExpressBaseAddressGuid, &HobList);
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GuidHob.Raw = GetFirstGuidHob (&gEfiPciExpressBaseAddressGuid);
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if (GuidHob.Raw != NULL) {
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PciExpressBaseAddressInfo = GET_GUID_HOB_DATA (GuidHob.Guid);
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BufferSize = GET_GUID_HOB_DATA_SIZE (GuidHob.Guid);
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@ -1,6 +1,6 @@
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/*++
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Copyright (c) 2005 - 2007, Intel Corporation
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Copyright (c) 2005 - 2008, Intel Corporation
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All rights reserved. This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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@ -635,7 +635,7 @@ PcatRootBridgeIoMap (
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// map the DMA transfer to a buffer below 4GB.
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//
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PhysicalAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)HostAddress;
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if ((PhysicalAddress + *NumberOfBytes) > 0x100000000) {
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if ((PhysicalAddress + *NumberOfBytes) > 0x100000000ULL) {
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//
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// Common Buffer operations can not be remapped. If the common buffer
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@ -653,7 +653,7 @@ PcatRootBridgeIoMap (
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Status = gBS->AllocatePool (
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EfiBootServicesData,
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sizeof(MAP_INFO),
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&MapInfo
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(VOID **)&MapInfo
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);
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if (EFI_ERROR (Status)) {
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*NumberOfBytes = 0;
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@ -706,7 +706,7 @@ PcatRootBridgeIoMap (
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Status =gBS->AllocatePool (
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EfiBootServicesData,
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sizeof(MAP_INFO_INSTANCE),
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&MapInstance
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(VOID **)&MapInstance
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);
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if (EFI_ERROR(Status)) {
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gBS->FreePages (MapInfo->MappedHostAddress,MapInfo->NumberOfPages);
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