mirror of https://github.com/acidanthera/audk.git
SecurityPkg: Add TPM PTP detection in TPM12 device lib.
The TPM RequestUseTpm API can only set register to use the hardware, but it can not be used to distinguish TPM12 or TPM2 device. TPM PTP defines same address with TIS, so we need detect the TPM device is PTP or TIS in RequestUseTpm. Also, Tcg2Config driver call RequestUseTpm to detect TPM hardware device. So we have to add check here. There is no need to support PTP CRB style SubmitCommand(), because TPM2 device can not accept TPM12 style command. This patch also uses TpmTis.h instead of duplicate definition. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com> Reviewed-by: "Zhang, Chao B" <chao.b.zhang@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19742 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Yao, Jiewen
jyao1
parent
d967d6d96f
commit
8e997ab8d3
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@ -1,7 +1,7 @@
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/** @file
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TIS (TPM Interface Specification) functions used by TPM1.2.
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Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.<BR>
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(C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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@ -23,164 +23,15 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#include <Library/Tpm12CommandLib.h>
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#include <Library/PcdLib.h>
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//
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// Set structure alignment to 1-byte
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//
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#pragma pack (1)
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#include <IndustryStandard/TpmPtp.h>
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#include <IndustryStandard/TpmTis.h>
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//
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// Register set map as specified in TIS specification Chapter 10
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//
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typedef struct {
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///
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/// Used to gain ownership for this particular port.
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///
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UINT8 Access; // 0
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UINT8 Reserved1[7]; // 1
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///
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/// Controls interrupts.
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///
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UINT32 IntEnable; // 8
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///
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/// SIRQ vector to be used by the TPM.
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///
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UINT8 IntVector; // 0ch
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UINT8 Reserved2[3]; // 0dh
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///
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/// What caused interrupt.
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///
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UINT32 IntSts; // 10h
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///
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/// Shows which interrupts are supported by that particular TPM.
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///
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UINT32 IntfCapability; // 14h
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///
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/// Status Register. Provides status of the TPM.
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///
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UINT8 Status; // 18h
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///
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/// Number of consecutive writes that can be done to the TPM.
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///
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UINT16 BurstCount; // 19h
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UINT8 Reserved3[9];
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///
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/// Read or write FIFO, depending on transaction.
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///
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UINT32 DataFifo; // 24h
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UINT8 Reserved4[0xed8]; // 28h
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///
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/// Vendor ID
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///
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UINT16 Vid; // 0f00h
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///
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/// Device ID
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///
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UINT16 Did; // 0f02h
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///
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/// Revision ID
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///
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UINT8 Rid; // 0f04h
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///
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/// TCG defined configuration registers.
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///
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UINT8 TcgDefined[0x7b]; // 0f05h
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///
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/// Alias to I/O legacy space.
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///
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UINT32 LegacyAddress1; // 0f80h
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///
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/// Additional 8 bits for I/O legacy space extension.
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///
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UINT32 LegacyAddress1Ex; // 0f84h
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///
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/// Alias to second I/O legacy space.
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///
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UINT32 LegacyAddress2; // 0f88h
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///
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/// Additional 8 bits for second I/O legacy space extension.
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///
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UINT32 LegacyAddress2Ex; // 0f8ch
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///
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/// Vendor-defined configuration registers.
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///
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UINT8 VendorDefined[0x70];// 0f90h
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} TIS_PC_REGISTERS;
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//
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// Restore original structure alignment
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//
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#pragma pack ()
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//
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// Define pointer types used to access TIS registers on PC
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//
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typedef TIS_PC_REGISTERS *TIS_PC_REGISTERS_PTR;
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//
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// Define bits of ACCESS and STATUS registers
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//
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///
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/// This bit is a 1 to indicate that the other bits in this register are valid.
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///
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#define TIS_PC_VALID BIT7
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///
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/// Indicate that this locality is active.
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///
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#define TIS_PC_ACC_ACTIVE BIT5
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///
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/// Set to 1 to indicate that this locality had the TPM taken away while
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/// this locality had the TIS_PC_ACC_ACTIVE bit set.
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///
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#define TIS_PC_ACC_SEIZED BIT4
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///
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/// Set to 1 to indicate that TPM MUST reset the
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/// TIS_PC_ACC_ACTIVE bit and remove ownership for localities less than the
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/// locality that is writing this bit.
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///
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#define TIS_PC_ACC_SEIZE BIT3
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///
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/// When this bit is 1, another locality is requesting usage of the TPM.
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///
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#define TIS_PC_ACC_PENDIND BIT2
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///
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/// Set to 1 to indicate that this locality is requesting to use TPM.
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///
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#define TIS_PC_ACC_RQUUSE BIT1
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///
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/// A value of 1 indicates that a T/OS has not been established on the platform
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///
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#define TIS_PC_ACC_ESTABLISH BIT0
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///
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/// When this bit is 1, TPM is in the Ready state,
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/// indicating it is ready to receive a new command.
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///
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#define TIS_PC_STS_READY BIT6
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///
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/// Write a 1 to this bit to cause the TPM to execute that command.
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///
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#define TIS_PC_STS_GO BIT5
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///
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/// This bit indicates that the TPM has data available as a response.
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///
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#define TIS_PC_STS_DATA BIT4
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///
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/// The TPM sets this bit to a value of 1 when it expects another byte of data for a command.
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///
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#define TIS_PC_STS_EXPECT BIT3
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///
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/// Writes a 1 to this bit to force the TPM to re-send the response.
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///
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#define TIS_PC_STS_RETRY BIT1
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//
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// Default TimeOut value
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//
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#define TIS_TIMEOUT_A (750 * 1000) // 750ms
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#define TIS_TIMEOUT_B (2000 * 1000) // 2s
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#define TIS_TIMEOUT_C (750 * 1000) // 750ms
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#define TIS_TIMEOUT_D (750 * 1000) // 750ms
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typedef enum {
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PtpInterfaceTis,
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PtpInterfaceFifo,
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PtpInterfaceCrb,
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PtpInterfaceMax,
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} PTP_INTERFACE_TYPE;
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//
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// Max TPM command/reponse length
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@ -551,6 +402,103 @@ Tpm12SubmitCommand (
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);
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}
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/**
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Return PTP interface type.
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@param[in] Register Pointer to PTP register.
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@return PTP interface type.
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**/
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PTP_INTERFACE_TYPE
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Tpm12GetPtpInterface (
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IN VOID *Register
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)
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{
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PTP_CRB_INTERFACE_IDENTIFIER InterfaceId;
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PTP_FIFO_INTERFACE_CAPABILITY InterfaceCapability;
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if (!Tpm12TisPcPresenceCheck (Register)) {
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return PtpInterfaceMax;
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}
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//
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// Check interface id
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//
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InterfaceId.Uint32 = MmioRead32 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->InterfaceId);
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InterfaceCapability.Uint32 = MmioRead32 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->InterfaceCapability);
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if ((InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_CRB) &&
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(InterfaceId.Bits.InterfaceVersion == PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_CRB) &&
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(InterfaceId.Bits.CapCRB != 0)) {
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return PtpInterfaceCrb;
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}
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if ((InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_FIFO) &&
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(InterfaceId.Bits.InterfaceVersion == PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_FIFO) &&
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(InterfaceId.Bits.CapFIFO != 0) &&
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(InterfaceCapability.Bits.InterfaceVersion == INTERFACE_CAPABILITY_INTERFACE_VERSION_PTP)) {
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return PtpInterfaceFifo;
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}
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return PtpInterfaceTis;
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}
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/**
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Check whether the value of a TPM chip register satisfies the input BIT setting.
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@param[in] Register Address port of register to be checked.
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@param[in] BitSet Check these data bits are set.
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@param[in] BitClear Check these data bits are clear.
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@param[in] TimeOut The max wait time (unit MicroSecond) when checking register.
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@retval EFI_SUCCESS The register satisfies the check bit.
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@retval EFI_TIMEOUT The register can't run into the expected status in time.
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**/
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EFI_STATUS
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Tpm12PtpCrbWaitRegisterBits (
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IN UINT32 *Register,
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IN UINT32 BitSet,
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IN UINT32 BitClear,
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IN UINT32 TimeOut
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)
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{
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UINT32 RegRead;
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UINT32 WaitTime;
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for (WaitTime = 0; WaitTime < TimeOut; WaitTime += 30){
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RegRead = MmioRead32 ((UINTN)Register);
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if ((RegRead & BitSet) == BitSet && (RegRead & BitClear) == 0) {
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return EFI_SUCCESS;
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}
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MicroSecondDelay (30);
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}
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return EFI_TIMEOUT;
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}
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/**
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Get the control of TPM chip.
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@param[in] CrbReg Pointer to CRB register.
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@retval EFI_SUCCESS Get the control of TPM chip.
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@retval EFI_INVALID_PARAMETER CrbReg is NULL.
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@retval EFI_NOT_FOUND TPM chip doesn't exit.
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@retval EFI_TIMEOUT Can't get the TPM control in time.
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**/
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EFI_STATUS
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Tpm12PtpCrbRequestUseTpm (
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IN PTP_CRB_REGISTERS_PTR CrbReg
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)
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{
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EFI_STATUS Status;
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MmioWrite32((UINTN)&CrbReg->LocalityControl, PTP_CRB_LOCALITY_CONTROL_REQUEST_ACCESS);
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Status = Tpm12PtpCrbWaitRegisterBits (
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&CrbReg->LocalityStatus,
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PTP_CRB_LOCALITY_STATUS_GRANTED,
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0,
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PTP_TIMEOUT_A
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);
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return Status;
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}
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/**
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This service requests use TPM12.
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@ -564,5 +512,20 @@ Tpm12RequestUseTpm (
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VOID
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)
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{
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return Tpm12TisPcRequestUseTpm ((TIS_PC_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress));
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PTP_INTERFACE_TYPE PtpInterface;
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//
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// Special handle for TPM1.2 to check PTP too, because PTP/TIS share same register address.
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// Some other program might leverage this function to check the existence of TPM chip.
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//
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PtpInterface = Tpm12GetPtpInterface ((VOID *) (UINTN) PcdGet64 (PcdTpmBaseAddress));
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switch (PtpInterface) {
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case PtpInterfaceCrb:
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return Tpm12PtpCrbRequestUseTpm ((PTP_CRB_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress));
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case PtpInterfaceFifo:
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case PtpInterfaceTis:
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return Tpm12TisPcRequestUseTpm ((TIS_PC_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress));
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default:
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return EFI_NOT_FOUND;
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}
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}
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