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OvmfPkg/PlatformInitLib: allow PhysBits larger than 48

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If GuestPhysBits reports more than 48 phys-bits can be used allow
to go beyond that limit.

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
This commit is contained in:
Gerd Hoffmann 2024-03-01 11:28:34 +01:00 committed by mergify[bot]
parent 603ad2d6ae
commit 90cb1ec332
1 changed files with 5 additions and 5 deletions
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10
OvmfPkg/Library/PlatformInitLib/MemDetect.c
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@ -706,7 +706,7 @@ PlatformAddressWidthFromCpuid (
* and a 56 bit wide address space with 5 paging levels. * and a 56 bit wide address space with 5 paging levels.
*/ */
if (Cr4.Bits.LA57) { if (Cr4.Bits.LA57) {
if (PhysBits > 48) { if ((PhysBits > 48) && !GuestPhysBits) {
/* /*
* Some Intel CPUs support 5-level paging, have more than 48 * Some Intel CPUs support 5-level paging, have more than 48
* phys-bits but support only 4-level EPT, which effectively * phys-bits but support only 4-level EPT, which effectively
@ -716,11 +716,11 @@ PlatformAddressWidthFromCpuid (
* problem: They can handle guest phys-bits larger than 48 * problem: They can handle guest phys-bits larger than 48
* only in case the host runs in 5-level paging mode. * only in case the host runs in 5-level paging mode.
* *
* Until we have some way to communicate that kind of * GuestPhysBits is used to communicate that kind of
* limitations from hypervisor to guest, limit phys-bits * limitations from hypervisor to guest. If GuestPhysBits is
* to 48 unconditionally. * not set play safe and limit phys-bits to 48.
*/ */
DEBUG ((DEBUG_INFO, "%a: limit PhysBits to 48 (5-level paging)\n", __func__)); DEBUG ((DEBUG_INFO, "%a: limit PhysBits to 48 (5-level paging, no GuestPhysBits)\n", __func__));
PhysBits = 48; PhysBits = 48;
} }
} else { } else {