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ArmPkg: Introduce ArmCpuLib to abstract ARM Cpu specific initialization

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Every CPUs have their own initialization requirements.
This library allows to allows to abstract these initialization requirements
into the ARM Platform common components.



git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12448 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin 2011-09-27 16:22:09 +00:00
parent 607599bf3d
commit 90d6a1bbf1
12 changed files with 240 additions and 277 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
ArmPkg/ArmPkg.dsc
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@ -96,9 +96,6 @@
ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf
ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf
ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf
ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLib.inf
ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLibPrePi.inf
ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLibSec.inf
ArmPkg/Library/ArmLib/Null/NullArmLib.inf ArmPkg/Library/ArmLib/Null/NullArmLib.inf
ArmPkg/Library/ArmTrustZoneLib/ArmTrustZoneLib.inf ArmPkg/Library/ArmTrustZoneLib/ArmTrustZoneLib.inf
ArmPkg/Library/BaseMemoryLibStm/BaseMemoryLibStm.inf ArmPkg/Library/BaseMemoryLibStm/BaseMemoryLibStm.inf
@ -115,6 +112,9 @@
ArmPkg/Library/SemihostLib/SemihostLib.inf ArmPkg/Library/SemihostLib/SemihostLib.inf
ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
ArmPkg/Drivers/ArmCpuLib/ArmCortexA8Lib/ArmCortexA8Lib.inf
ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.inf
ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Lib.inf
ArmPkg/Drivers/CpuDxe/CpuDxe.inf ArmPkg/Drivers/CpuDxe/CpuDxe.inf
ArmPkg/Drivers/CpuPei/CpuPei.inf ArmPkg/Drivers/CpuPei/CpuPei.inf
ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf

1
ArmPlatformPkg/ArmPlatformPkg.dec
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@ -55,7 +55,6 @@
[PcdsFixedAtBuild.common] [PcdsFixedAtBuild.common]
# These PCDs should be FeaturePcds. But we used these PCDs as an '#if' in an ASM file. # These PCDs should be FeaturePcds. But we used these PCDs as an '#if' in an ASM file.
# Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor. # Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.
gArmPlatformTokenSpaceGuid.PcdMPCoreSupport|0|UINT32|0x00000003
gArmPlatformTokenSpaceGuid.PcdClusterCount|1|UINT32|0x00000038 gArmPlatformTokenSpaceGuid.PcdClusterCount|1|UINT32|0x00000038
# Stack for CPU Cores in Secure Mode # Stack for CPU Cores in Secure Mode

3
ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A8.dsc
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@ -31,6 +31,7 @@
[LibraryClasses.common] [LibraryClasses.common]
ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf
ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexA8Lib/ArmCortexA8Lib.inf
ArmPlatformLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbLib.inf ArmPlatformLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbLib.inf
# ARM PL390 General Interrupt Driver in Secure and Non-secure # ARM PL390 General Interrupt Driver in Secure and Non-secure
@ -44,7 +45,7 @@
[BuildOptions] [BuildOptions]
RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu Cortex-A8 --fpu=softvfp -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu Cortex-A8 --fpu=softvfp -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform
GCC:*_*_ARM_PLATFORM_FLAGS == -march=armv7-a -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform GCC:*_*_ARM_PLATFORM_FLAGS == -mcpu=cortex-a8 -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform
XCODE:*_*_ARM_PLATFORM_FLAGS == -arch armv7 -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform XCODE:*_*_ARM_PLATFORM_FLAGS == -arch armv7 -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform

5
ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A9x2.dsc
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@ -31,6 +31,7 @@
[LibraryClasses.common] [LibraryClasses.common]
ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLib.inf ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLib.inf
ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.inf
ArmPlatformLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbLib.inf ArmPlatformLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbLib.inf
# ARM PL390 General Interrupt Driver in Secure and Non-secure # ARM PL390 General Interrupt Driver in Secure and Non-secure
@ -44,7 +45,7 @@
[BuildOptions] [BuildOptions]
RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu Cortex-A9 --fpu=softvfp -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu Cortex-A9 --fpu=softvfp -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform
GCC:*_*_ARM_PLATFORM_FLAGS == -march=armv7-a -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform GCC:*_*_ARM_PLATFORM_FLAGS == -mcpu=cortex-a9 -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform
XCODE:*_*_ARM_PLATFORM_FLAGS == -arch armv7 -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform XCODE:*_*_ARM_PLATFORM_FLAGS == -arch armv7 -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform
@ -79,8 +80,6 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x43FE0000 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x43FE0000
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00020000 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00020000
gArmPlatformTokenSpaceGuid.PcdMPCoreSupport|1
# Stacks for MPCores in Secure World # Stacks for MPCores in Secure World
gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0x4B000000 gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0x4B000000
# Stacks for MPCores in Monitor Mode # Stacks for MPCores in Monitor Mode

2
ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.dsc
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@ -35,6 +35,7 @@
[LibraryClasses.common] [LibraryClasses.common]
ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLib.inf ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLib.inf
ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.inf
ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressLib.inf ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressLib.inf
ArmTrustZoneLib|ArmPkg/Library/ArmTrustZoneLib/ArmTrustZoneLib.inf ArmTrustZoneLib|ArmPkg/Library/ArmTrustZoneLib/ArmTrustZoneLib.inf
@ -174,7 +175,6 @@
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20 gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0 gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0
gArmPlatformTokenSpaceGuid.PcdMPCoreSupport|1
gArmTokenSpaceGuid.PcdVFPEnabled|1 gArmTokenSpaceGuid.PcdVFPEnabled|1
# Stacks for MPCores in Secure World # Stacks for MPCores in Secure World

2
ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-A9x4.dsc
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@ -31,6 +31,7 @@
[LibraryClasses.common] [LibraryClasses.common]
ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLib.inf ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLib.inf
ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.inf
ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf
ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf
@ -89,7 +90,6 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x0FFE0000 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x0FFE0000
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00010000 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00010000
gArmPlatformTokenSpaceGuid.PcdMPCoreSupport|1
gArmTokenSpaceGuid.PcdVFPEnabled|1 gArmTokenSpaceGuid.PcdVFPEnabled|1
# Stacks for MPCores in Secure World # Stacks for MPCores in Secure World

1
ArmPlatformPkg/Documentation/ArmPlatformPkg.txt
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@ -31,7 +31,6 @@ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize : Size of the sta
# CPU / Architectural controllers # CPU / Architectural controllers
gArmTokenSpaceGuid.PcdGicDistributorBase : Base address of the Distributor of your General Interrupt Controller gArmTokenSpaceGuid.PcdGicDistributorBase : Base address of the Distributor of your General Interrupt Controller
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase : Base address of the Interface of your General Interrupt Controller gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase : Base address of the Interface of your General Interrupt Controller
gArmPlatformTokenSpaceGuid.PcdMPCoreSupport : Set to 1 when MP Core platforms
# Memory Regions # Memory Regions
gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize : Size of the region reserve for PI & UEFI gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize : Size of the region reserve for PI & UEFI

65
ArmPlatformPkg/Sec/Sec.c
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@ -14,13 +14,12 @@
**/ **/
#include <Library/DebugAgentLib.h> #include <Library/DebugAgentLib.h>
#include <Library/PcdLib.h>
#include <Library/PrintLib.h> #include <Library/PrintLib.h>
#include <Library/BaseMemoryLib.h> #include <Library/BaseMemoryLib.h>
#include <Library/ArmLib.h>
#include <Library/SerialPortLib.h> #include <Library/SerialPortLib.h>
#include <Library/ArmPlatformLib.h> #include <Library/ArmPlatformLib.h>
#include <Library/ArmGicLib.h> #include <Library/ArmGicLib.h>
#include <Library/ArmCpuLib.h>
#include "SecInternal.h" #include "SecInternal.h"
@ -39,8 +38,10 @@ CEntryPoint (
// Primary CPU clears out the SCU tag RAMs, secondaries wait // Primary CPU clears out the SCU tag RAMs, secondaries wait
if (IS_PRIMARY_CORE(MpId)) { if (IS_PRIMARY_CORE(MpId)) {
if (FixedPcdGet32(PcdMPCoreSupport)) { ArmCpuSetup (MpId);
ArmInvalidScu ();
if (ArmIsMpCore()) {
ArmCpuSynchronizeSignal (ARM_CPU_EVENT_BOOT_MEM_INIT);
} }
// SEC phase needs to run library constructors by hand. This assumes we are linked against the SerialLib // SEC phase needs to run library constructors by hand. This assumes we are linked against the SerialLib
@ -58,6 +59,15 @@ CEntryPoint (
// Now we've got UART, make the check: // Now we've got UART, make the check:
// - The Vector table must be 32-byte aligned // - The Vector table must be 32-byte aligned
ASSERT(((UINT32)SecVectorTable & ((1 << 5)-1)) == 0); ASSERT(((UINT32)SecVectorTable & ((1 << 5)-1)) == 0);
// Enable the GIC distributor and CPU Interface
// - no other Interrupts are enabled, doesn't have to worry about the priority.
// - all the cores are in secure state, use secure SGI's
ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase));
ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
} else {
// Enable the GIC CPU Interface
ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
} }
// Invalidate the data cache. Doesn't have to do the Data cache clean. // Invalidate the data cache. Doesn't have to do the Data cache clean.
@ -72,13 +82,7 @@ CEntryPoint (
// Enable Full Access to CoProcessors // Enable Full Access to CoProcessors
ArmWriteCPACR (CPACR_CP_FULL_ACCESS); ArmWriteCPACR (CPACR_CP_FULL_ACCESS);
// Enable SWP instructions if (FixedPcdGet32 (PcdVFPEnabled)) {
ArmEnableSWPInstruction ();
// Enable program flow prediction, if supported.
ArmEnableBranchPrediction ();
if (FixedPcdGet32(PcdVFPEnabled)) {
ArmEnableVFP(); ArmEnableVFP();
} }
@ -89,7 +93,7 @@ CEntryPoint (
// If we skip the PEI Core we could want to initialize the DRAM in the SEC phase. // If we skip the PEI Core we could want to initialize the DRAM in the SEC phase.
// If we are in standalone, we need the initialization to copy the UEFI firmware into DRAM // If we are in standalone, we need the initialization to copy the UEFI firmware into DRAM
if (FeaturePcdGet(PcdSystemMemoryInitializeInSec)) { if (FeaturePcdGet (PcdSystemMemoryInitializeInSec)) {
// Initialize system memory (DRAM) // Initialize system memory (DRAM)
ArmPlatformInitializeSystemMemory (); ArmPlatformInitializeSystemMemory ();
} }
@ -104,9 +108,9 @@ CEntryPoint (
ASSERT(PcdGet32(PcdCPUCoresSecMonStackBase) != 0); ASSERT(PcdGet32(PcdCPUCoresSecMonStackBase) != 0);
ASSERT(PcdGet32(PcdCPUCoreSecMonStackSize) != 0); ASSERT(PcdGet32(PcdCPUCoreSecMonStackSize) != 0);
if (FixedPcdGet32(PcdMPCoreSupport)) { if (ArmIsMpCore()) {
// Setup SMP in Non Secure world // Setup SMP in Non Secure world
ArmSetupSmpNonSecure (GET_CORE_ID(MpId)); ArmCpuSetupSmpNonSecure (GET_CORE_ID(MpId));
} }
// Enter Monitor Mode // Enter Monitor Mode
@ -120,35 +124,18 @@ CEntryPoint (
if (IS_PRIMARY_CORE(MpId)) { if (IS_PRIMARY_CORE(MpId)) {
ArmPlatformTrustzoneInit (); ArmPlatformTrustzoneInit ();
// Wake up the secondary cores by sending a interrupt to everyone else // Waiting for the Primary Core to have finished to initialize the Secure World
// NOTE 1: The Software Generated Interrupts are always enabled on Cortex-A9 ArmCpuSynchronizeSignal (ARM_CPU_EVENT_SECURE_INIT);
// MPcore test chip on Versatile Express board, So the Software doesn't have to
// enable SGI's explicitly.
// 2: As no other Interrupts are enabled, doesn't have to worry about the priority.
// 3: As all the cores are in secure state, use secure SGI's
//
ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase));
ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
// Send SGI to all Secondary core to wake them up from WFI state.
ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
} else { } else {
// The secondary cores need to wait until the Trustzone chipsets configuration is done // The secondary cores need to wait until the Trustzone chipsets configuration is done
// before switching to Non Secure World // before switching to Non Secure World
// Enabled GIC CPU Interface // Waiting for the Primary Core to have finished to initialize the Secure World
ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase)); ArmCpuSynchronizeWait (ARM_CPU_EVENT_SECURE_INIT);
// Waiting for the SGI from the primary core
ArmCallWFI();
// Acknowledge the interrupt and send End of Interrupt signal.
ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);
} }
// Transfer the interrupt to Non-secure World // Transfer the interrupt to Non-secure World
ArmGicSetupNonSecure (PcdGet32(PcdGicDistributorBase),PcdGet32(PcdGicInterruptInterfaceBase)); ArmGicSetupNonSecure (PcdGet32(PcdGicDistributorBase), PcdGet32(PcdGicInterruptInterfaceBase));
// Write to CP15 Non-secure Access Control Register : // Write to CP15 Non-secure Access Control Register :
// - Enable CP10 and CP11 accesses in NS World // - Enable CP10 and CP11 accesses in NS World
@ -165,12 +152,6 @@ CEntryPoint (
SerialPrint ("Trust Zone Configuration is disabled\n\r"); SerialPrint ("Trust Zone Configuration is disabled\n\r");
} }
// Trustzone is not enabled, just enable the Distributor and CPU interface
if (IS_PRIMARY_CORE(MpId)) {
ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase));
}
ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
// With Trustzone support the transition from Sec to Normal world is done by return_from_exception(). // With Trustzone support the transition from Sec to Normal world is done by return_from_exception().
// If we want to keep this function call we need to ensure the SVC's SPSR point to the same Program // If we want to keep this function call we need to ensure the SVC's SPSR point to the same Program
// Status Register as the the current one (CPSR). // Status Register as the the current one (CPSR).

140
ArmPlatformPkg/Sec/Sec.inf
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@ -1,70 +1,70 @@
#/** @file #/** @file
# SEC - Reset vector code that jumps to C and loads DXE core # SEC - Reset vector code that jumps to C and loads DXE core
# #
# Copyright (c) 2011, ARM Limited. All rights reserved. # Copyright (c) 2011, ARM Limited. All rights reserved.
# #
# This program and the accompanying materials # This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License # are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at # which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php # http://opensource.org/licenses/bsd-license.php
# #
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
# #
#**/ #**/
[Defines] [Defines]
INF_VERSION = 0x00010005 INF_VERSION = 0x00010005
BASE_NAME = ArmPlatformSec BASE_NAME = ArmPlatformSec
FILE_GUID = c536bbfe-c813-4e48-9f90-01fe1ecf9d54 FILE_GUID = c536bbfe-c813-4e48-9f90-01fe1ecf9d54
MODULE_TYPE = SEC MODULE_TYPE = SEC
VERSION_STRING = 1.0 VERSION_STRING = 1.0
[Sources.ARM] [Sources.ARM]
Helper.asm | RVCT Helper.asm | RVCT
Helper.S | GCC Helper.S | GCC
Sec.c Sec.c
SecEntryPoint.S | GCC SecEntryPoint.S | GCC
SecEntryPoint.asm | RVCT SecEntryPoint.asm | RVCT
Exception.asm | RVCT Exception.asm | RVCT
Exception.S | GCC Exception.S | GCC
[Packages] [Packages]
MdePkg/MdePkg.dec MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec MdeModulePkg/MdeModulePkg.dec
ArmPkg/ArmPkg.dec ArmPkg/ArmPkg.dec
ArmPlatformPkg/ArmPlatformPkg.dec ArmPlatformPkg/ArmPlatformPkg.dec
[LibraryClasses] [LibraryClasses]
ArmLib ArmCpuLib
ArmPlatformLib ArmLib
BaseLib ArmPlatformLib
DebugLib BaseLib
DebugAgentLib DebugLib
IoLib DebugAgentLib
ArmGicSecLib IoLib
PrintLib ArmGicSecLib
SerialPortLib PrintLib
SerialPortLib
[FeaturePcd]
gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec [FeaturePcd]
gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec
[FixedPcd]
gArmTokenSpaceGuid.PcdVFPEnabled [FixedPcd]
gArmPlatformTokenSpaceGuid.PcdMPCoreSupport gArmTokenSpaceGuid.PcdVFPEnabled
gArmTokenSpaceGuid.PcdArmPrimaryCoreMask gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
gArmTokenSpaceGuid.PcdArmPrimaryCore gArmTokenSpaceGuid.PcdArmPrimaryCore
gArmTokenSpaceGuid.PcdFvBaseAddress gArmTokenSpaceGuid.PcdFvBaseAddress
gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize
gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize
gArmTokenSpaceGuid.PcdGicDistributorBase gArmTokenSpaceGuid.PcdGicDistributorBase
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
gArmPlatformTokenSpaceGuid.PcdSecGlobalVariableSize gArmPlatformTokenSpaceGuid.PcdSecGlobalVariableSize

26
ArmPlatformPkg/Sec/SecEntryPoint.S
View File

@ -13,15 +13,11 @@
#include <AutoGen.h> #include <AutoGen.h>
#include <AsmMacroIoLib.h> #include <AsmMacroIoLib.h>
#include <Base.h> #include "SecInternal.h"
#include <Library/PcdLib.h>
#include <Library/ArmPlatformLib.h>
.text .text
.align 3 .align 3
GCC_ASM_EXPORT(_ModuleEntryPoint)
GCC_ASM_IMPORT(CEntryPoint) GCC_ASM_IMPORT(CEntryPoint)
GCC_ASM_IMPORT(ArmPlatformSecBootAction) GCC_ASM_IMPORT(ArmPlatformSecBootAction)
GCC_ASM_IMPORT(ArmPlatformInitializeBootMemory) GCC_ASM_IMPORT(ArmPlatformInitializeBootMemory)
@ -30,13 +26,10 @@ GCC_ASM_IMPORT(ArmDisableCachesAndMmu)
GCC_ASM_IMPORT(ArmWriteVBar) GCC_ASM_IMPORT(ArmWriteVBar)
GCC_ASM_IMPORT(ArmReadMpidr) GCC_ASM_IMPORT(ArmReadMpidr)
GCC_ASM_IMPORT(SecVectorTable) GCC_ASM_IMPORT(SecVectorTable)
GCC_ASM_IMPORT(ArmCpuSynchronizeWait)
#if (FixedPcdGet32(PcdMPCoreSupport)) GCC_ASM_EXPORT(_ModuleEntryPoint)
GCC_ASM_IMPORT(ArmIsScuEnable)
#endif
StartupAddr: .word ASM_PFX(CEntryPoint) StartupAddr: .word ASM_PFX(CEntryPoint)
SecVectorTableAddr: .word ASM_PFX(SecVectorTable)
ASM_PFX(_ModuleEntryPoint): ASM_PFX(_ModuleEntryPoint):
// First ensure all interrupts are disabled // First ensure all interrupts are disabled
@ -65,14 +58,11 @@ _IdentifyCpu:
// Only the primary core initialize the memory (SMC) // Only the primary core initialize the memory (SMC)
beq _InitMem beq _InitMem
#if (FixedPcdGet32(PcdMPCoreSupport)) _WaitInitMem:
// ... The secondary cores wait for SCU to be enabled mov r0, #ARM_CPU_EVENT_BOOT_MEM_INIT
_WaitForEnabledScu: bl ASM_PFX(ArmCpuSynchronizeWait)
bl ASM_PFX(ArmIsScuEnable) // Now the Init Mem is initialized, we setup the secondary core stacks
tst r1, #1
beq _WaitForEnabledScu
b _SetupSecondaryCoreStack b _SetupSecondaryCoreStack
#endif
_InitMem: _InitMem:
// Initialize Init Boot Memory // Initialize Init Boot Memory
@ -110,7 +100,7 @@ _SetupSecondaryCoreStack:
// Get the base of the stack for the secondary cores // Get the base of the stack for the secondary cores
LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1) LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)
LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2) LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize), r2)
add r1, r1, r2 add r1, r1, r2
// StackOffset = CorePos * StackSize // StackOffset = CorePos * StackSize

260
ArmPlatformPkg/Sec/SecEntryPoint.asm
View File

@ -1,134 +1,126 @@
// //
// Copyright (c) 2011, ARM Limited. All rights reserved. // Copyright (c) 2011, ARM Limited. All rights reserved.
// //
// This program and the accompanying materials // This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License // are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at // which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php // http://opensource.org/licenses/bsd-license.php
// //
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
// //
// //
#include <AutoGen.h> #include <AutoGen.h>
#include <AsmMacroIoLib.h> #include <AsmMacroIoLib.h>
#include <Base.h> #include "SecInternal.h"
#include <Library/PcdLib.h>
#include <Library/ArmPlatformLib.h> INCLUDE AsmMacroIoLib.inc
INCLUDE AsmMacroIoLib.inc IMPORT CEntryPoint
IMPORT ArmPlatformSecBootAction
IMPORT CEntryPoint IMPORT ArmPlatformInitializeBootMemory
IMPORT ArmPlatformSecBootAction IMPORT ArmDisableInterrupts
IMPORT ArmPlatformInitializeBootMemory IMPORT ArmDisableCachesAndMmu
IMPORT ArmDisableInterrupts IMPORT ArmWriteVBar
IMPORT ArmDisableCachesAndMmu IMPORT ArmReadMpidr
IMPORT ArmWriteVBar IMPORT SecVectorTable
IMPORT ArmReadMpidr IMPORT ArmCpuSynchronizeWait
IMPORT SecVectorTable EXPORT _ModuleEntryPoint
EXPORT _ModuleEntryPoint
PRESERVE8
#if (FixedPcdGet32(PcdMPCoreSupport)) AREA SecEntryPoint, CODE, READONLY
IMPORT ArmIsScuEnable
#endif StartupAddr DCD CEntryPoint
PRESERVE8 _ModuleEntryPoint
AREA SecEntryPoint, CODE, READONLY // First ensure all interrupts are disabled
blx ArmDisableInterrupts
StartupAddr DCD CEntryPoint
// Ensure that the MMU and caches are off
_ModuleEntryPoint blx ArmDisableCachesAndMmu
// First ensure all interrupts are disabled
blx ArmDisableInterrupts // Jump to Platform Specific Boot Action function
blx ArmPlatformSecBootAction
// Ensure that the MMU and caches are off
blx ArmDisableCachesAndMmu // Set VBAR to the start of the exception vectors in Secure Mode
ldr r0, =SecVectorTable
// Jump to Platform Specific Boot Action function blx ArmWriteVBar
blx ArmPlatformSecBootAction
_IdentifyCpu
// Set VBAR to the start of the exception vectors in Secure Mode // Identify CPU ID
ldr r0, =SecVectorTable bl ArmReadMpidr
blx ArmWriteVBar // Get ID of this CPU in Multicore system
LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)
_IdentifyCpu and r5, r0, r1
// Identify CPU ID
bl ArmReadMpidr // Is it the Primary Core ?
// Get ID of this CPU in Multicore system LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r1)
LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1) cmp r5, r1
and r5, r0, r1 // Only the primary core initialize the memory (SMC)
beq _InitMem
// Is it the Primary Core ?
LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r1) _WaitInitMem
cmp r5, r1 mov r0, #ARM_CPU_EVENT_BOOT_MEM_INIT
// Only the primary core initialize the memory (SMC) bl ArmCpuSynchronizeWait
beq _InitMem // Now the Init Mem is initialized, we setup the secondary core stacks
b _SetupSecondaryCoreStack
#if (FixedPcdGet32(PcdMPCoreSupport))
// ... The secondary cores wait for SCU to be enabled _InitMem
_WaitForEnabledScu // Initialize Init Boot Memory
bl ArmIsScuEnable bl ArmPlatformInitializeBootMemory
tst r1, #1
beq _WaitForEnabledScu // Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack)
b _SetupSecondaryCoreStack LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r5)
#endif
_SetupPrimaryCoreStack
_InitMem LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r2)
// Initialize Init Boot Memory LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r3)
bl ArmPlatformInitializeBootMemory // Calculate the Top of the Stack
add r2, r2, r3
// Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack) LoadConstantToReg (FixedPcdGet32(PcdSecGlobalVariableSize), r3)
LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r5)
// The reserved space for global variable must be 8-bytes aligned for pushing
_SetupPrimaryCoreStack // 64-bit variable on the stack
LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r2) SetPrimaryStack (r2, r3, r1)
LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r3)
// Calculate the Top of the Stack // Set all the SEC global variables to 0
add r2, r2, r3 mov r3, sp
LoadConstantToReg (FixedPcdGet32(PcdSecGlobalVariableSize), r3) mov r1, #0x0
_InitGlobals
// The reserved space for global variable must be 8-bytes aligned for pushing str r1, [r3], #4
// 64-bit variable on the stack cmp r3, r2
SetPrimaryStack (r2, r3, r1) blt _InitGlobals
// Set all the SEC global variables to 0 b _PrepareArguments
mov r3, sp
mov r1, #0x0 _SetupSecondaryCoreStack
_InitGlobals // Get the Core Position (ClusterId * 4) + CoreId
str r1, [r3], #4 GetCorePositionInStack(r0, r5, r1)
cmp r3, r2 // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack
blt _InitGlobals add r0, r0, #1
b _PrepareArguments // Get the base of the stack for the secondary cores
LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)
_SetupSecondaryCoreStack LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize), r2)
// Get the Core Position (ClusterId * 4) + CoreId add r1, r1, r2
GetCorePositionInStack(r0, r5, r1)
// The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack // StackOffset = CorePos * StackSize
add r0, r0, #1 mul r0, r0, r2
// SP = StackBase + StackOffset
// Get the base of the stack for the secondary cores add sp, r1, r0
LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)
LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize), r2)
add r1, r1, r2 _PrepareArguments
// Move sec startup address into a data register
// StackOffset = CorePos * StackSize // Ensure we're jumping to FV version of the code (not boot remapped alias)
mul r0, r0, r2 ldr r3, StartupAddr
// SP = StackBase + StackOffset
add sp, r1, r0 // Jump to SEC C code
// r0 = mp_id
mov r0, r5
_PrepareArguments blx r3
// Move sec startup address into a data register
// Ensure we're jumping to FV version of the code (not boot remapped alias) _NeverReturn
ldr r3, StartupAddr b _NeverReturn
END
// Jump to SEC C code
// r0 = mp_id
mov r0, r5
blx r3
_NeverReturn
b _NeverReturn
END

6
ArmPlatformPkg/Sec/SecInternal.h
View File

@ -17,10 +17,12 @@
#define __SEC_H__ #define __SEC_H__
#include <Base.h> #include <Base.h>
#include <Library/ArmLib.h>
#include <Library/ArmCpuLib.h>
#include <Library/ArmPlatformLib.h>
#include <Library/BaseLib.h> #include <Library/BaseLib.h>
#include <Library/DebugLib.h> #include <Library/DebugLib.h>
#include <Library/PcdLib.h>
#include <Chipset/ArmV7.h>
#define IS_ALIGNED(Address, Align) (((UINTN)Address & (Align-1)) == 0) #define IS_ALIGNED(Address, Align) (((UINTN)Address & (Align-1)) == 0)