tyler.durden/audk
1
0
Fork 0
mirror of https://github.com/acidanthera/audk.git synced 2025-07-26 15:14:02 +02:00
Code Issues Packages Projects Releases Wiki Activity

ArmPkg: Introduce ArmCpuLib to abstract ARM Cpu specific initialization

Browse Source 
Every CPUs have their own initialization requirements.
This library allows to allows to abstract these initialization requirements
into the ARM Platform common components.



git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12448 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin 2011-09-27 16:22:09 +00:00
parent 607599bf3d
commit 90d6a1bbf1
12 changed files with 240 additions and 277 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
ArmPkg/ArmPkg.dsc
View File

@ -96,9 +96,6 @@
ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf
ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf
ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf
ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLib.inf
ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLibPrePi.inf
ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLibSec.inf
ArmPkg/Library/ArmLib/Null/NullArmLib.inf
ArmPkg/Library/ArmTrustZoneLib/ArmTrustZoneLib.inf
ArmPkg/Library/BaseMemoryLibStm/BaseMemoryLibStm.inf
@ -115,6 +112,9 @@
ArmPkg/Library/SemihostLib/SemihostLib.inf
ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
ArmPkg/Drivers/ArmCpuLib/ArmCortexA8Lib/ArmCortexA8Lib.inf
ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.inf
ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Lib.inf
ArmPkg/Drivers/CpuDxe/CpuDxe.inf
ArmPkg/Drivers/CpuPei/CpuPei.inf
ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf

1
ArmPlatformPkg/ArmPlatformPkg.dec
View File

@ -55,7 +55,6 @@
[PcdsFixedAtBuild.common]
# These PCDs should be FeaturePcds. But we used these PCDs as an '#if' in an ASM file.
# Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.
gArmPlatformTokenSpaceGuid.PcdMPCoreSupport|0|UINT32|0x00000003
gArmPlatformTokenSpaceGuid.PcdClusterCount|1|UINT32|0x00000038
# Stack for CPU Cores in Secure Mode

3
ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A8.dsc
View File

@ -31,6 +31,7 @@
[LibraryClasses.common]
ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf
ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexA8Lib/ArmCortexA8Lib.inf
ArmPlatformLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbLib.inf
# ARM PL390 General Interrupt Driver in Secure and Non-secure
@ -44,7 +45,7 @@
[BuildOptions]
RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu Cortex-A8 --fpu=softvfp -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform
GCC:*_*_ARM_PLATFORM_FLAGS == -march=armv7-a -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform
GCC:*_*_ARM_PLATFORM_FLAGS == -mcpu=cortex-a8 -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform
XCODE:*_*_ARM_PLATFORM_FLAGS == -arch armv7 -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform

5
ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A9x2.dsc
View File

@ -31,6 +31,7 @@
[LibraryClasses.common]
ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLib.inf
ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.inf
ArmPlatformLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbLib.inf
# ARM PL390 General Interrupt Driver in Secure and Non-secure
@ -44,7 +45,7 @@
[BuildOptions]
RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu Cortex-A9 --fpu=softvfp -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform
GCC:*_*_ARM_PLATFORM_FLAGS == -march=armv7-a -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform
GCC:*_*_ARM_PLATFORM_FLAGS == -mcpu=cortex-a9 -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform
XCODE:*_*_ARM_PLATFORM_FLAGS == -arch armv7 -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform
@ -79,8 +80,6 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x43FE0000
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00020000
gArmPlatformTokenSpaceGuid.PcdMPCoreSupport|1
# Stacks for MPCores in Secure World
gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0x4B000000
# Stacks for MPCores in Monitor Mode

2
ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.dsc
View File

@ -35,6 +35,7 @@
[LibraryClasses.common]
ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLib.inf
ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.inf
ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressLib.inf
ArmTrustZoneLib|ArmPkg/Library/ArmTrustZoneLib/ArmTrustZoneLib.inf
@ -174,7 +175,6 @@
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0
gArmPlatformTokenSpaceGuid.PcdMPCoreSupport|1
gArmTokenSpaceGuid.PcdVFPEnabled|1
# Stacks for MPCores in Secure World

2
ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-A9x4.dsc
View File

@ -31,6 +31,7 @@
[LibraryClasses.common]
ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLib.inf
ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.inf
ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf
ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf
@ -89,7 +90,6 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x0FFE0000
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00010000
gArmPlatformTokenSpaceGuid.PcdMPCoreSupport|1
gArmTokenSpaceGuid.PcdVFPEnabled|1
# Stacks for MPCores in Secure World

1
ArmPlatformPkg/Documentation/ArmPlatformPkg.txt
View File

@ -31,7 +31,6 @@ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize : Size of the sta
# CPU / Architectural controllers
gArmTokenSpaceGuid.PcdGicDistributorBase : Base address of the Distributor of your General Interrupt Controller
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase : Base address of the Interface of your General Interrupt Controller
gArmPlatformTokenSpaceGuid.PcdMPCoreSupport : Set to 1 when MP Core platforms
# Memory Regions
gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize : Size of the region reserve for PI & UEFI

65
ArmPlatformPkg/Sec/Sec.c
View File

@ -14,13 +14,12 @@
**/
#include <Library/DebugAgentLib.h>
#include <Library/PcdLib.h>
#include <Library/PrintLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/ArmLib.h>
#include <Library/SerialPortLib.h>
#include <Library/ArmPlatformLib.h>
#include <Library/ArmGicLib.h>
#include <Library/ArmCpuLib.h>
#include "SecInternal.h"
@ -39,8 +38,10 @@ CEntryPoint (
// Primary CPU clears out the SCU tag RAMs, secondaries wait
if (IS_PRIMARY_CORE(MpId)) {
if (FixedPcdGet32(PcdMPCoreSupport)) {
ArmInvalidScu ();
ArmCpuSetup (MpId);
if (ArmIsMpCore()) {
ArmCpuSynchronizeSignal (ARM_CPU_EVENT_BOOT_MEM_INIT);
}
// SEC phase needs to run library constructors by hand. This assumes we are linked against the SerialLib
@ -58,6 +59,15 @@ CEntryPoint (
// Now we've got UART, make the check:
// - The Vector table must be 32-byte aligned
ASSERT(((UINT32)SecVectorTable & ((1 << 5)-1)) == 0);
// Enable the GIC distributor and CPU Interface
// - no other Interrupts are enabled, doesn't have to worry about the priority.
// - all the cores are in secure state, use secure SGI's
ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase));
ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
} else {
// Enable the GIC CPU Interface
ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
}
// Invalidate the data cache. Doesn't have to do the Data cache clean.
@ -72,13 +82,7 @@ CEntryPoint (
// Enable Full Access to CoProcessors
ArmWriteCPACR (CPACR_CP_FULL_ACCESS);
// Enable SWP instructions
ArmEnableSWPInstruction ();
// Enable program flow prediction, if supported.
ArmEnableBranchPrediction ();
if (FixedPcdGet32(PcdVFPEnabled)) {
if (FixedPcdGet32 (PcdVFPEnabled)) {
ArmEnableVFP();
}
@ -89,7 +93,7 @@ CEntryPoint (
// If we skip the PEI Core we could want to initialize the DRAM in the SEC phase.
// If we are in standalone, we need the initialization to copy the UEFI firmware into DRAM
if (FeaturePcdGet(PcdSystemMemoryInitializeInSec)) {
if (FeaturePcdGet (PcdSystemMemoryInitializeInSec)) {
// Initialize system memory (DRAM)
ArmPlatformInitializeSystemMemory ();
}
@ -104,9 +108,9 @@ CEntryPoint (
ASSERT(PcdGet32(PcdCPUCoresSecMonStackBase) != 0);
ASSERT(PcdGet32(PcdCPUCoreSecMonStackSize) != 0);
if (FixedPcdGet32(PcdMPCoreSupport)) {
if (ArmIsMpCore()) {
// Setup SMP in Non Secure world
ArmSetupSmpNonSecure (GET_CORE_ID(MpId));
ArmCpuSetupSmpNonSecure (GET_CORE_ID(MpId));
}
// Enter Monitor Mode
@ -120,35 +124,18 @@ CEntryPoint (
if (IS_PRIMARY_CORE(MpId)) {
ArmPlatformTrustzoneInit ();
// Wake up the secondary cores by sending a interrupt to everyone else
// NOTE 1: The Software Generated Interrupts are always enabled on Cortex-A9
// MPcore test chip on Versatile Express board, So the Software doesn't have to
// enable SGI's explicitly.
// 2: As no other Interrupts are enabled, doesn't have to worry about the priority.
// 3: As all the cores are in secure state, use secure SGI's
//
ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase));
ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
// Send SGI to all Secondary core to wake them up from WFI state.
ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
// Waiting for the Primary Core to have finished to initialize the Secure World
ArmCpuSynchronizeSignal (ARM_CPU_EVENT_SECURE_INIT);
} else {
// The secondary cores need to wait until the Trustzone chipsets configuration is done
// before switching to Non Secure World
// Enabled GIC CPU Interface
ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
// Waiting for the SGI from the primary core
ArmCallWFI();
// Acknowledge the interrupt and send End of Interrupt signal.
ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);
// Waiting for the Primary Core to have finished to initialize the Secure World
ArmCpuSynchronizeWait (ARM_CPU_EVENT_SECURE_INIT);
}
// Transfer the interrupt to Non-secure World
ArmGicSetupNonSecure (PcdGet32(PcdGicDistributorBase),PcdGet32(PcdGicInterruptInterfaceBase));
ArmGicSetupNonSecure (PcdGet32(PcdGicDistributorBase), PcdGet32(PcdGicInterruptInterfaceBase));
// Write to CP15 Non-secure Access Control Register :
// - Enable CP10 and CP11 accesses in NS World
@ -165,12 +152,6 @@ CEntryPoint (
SerialPrint ("Trust Zone Configuration is disabled\n\r");
}
// Trustzone is not enabled, just enable the Distributor and CPU interface
if (IS_PRIMARY_CORE(MpId)) {
ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase));
}
ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
// With Trustzone support the transition from Sec to Normal world is done by return_from_exception().
// If we want to keep this function call we need to ensure the SVC's SPSR point to the same Program
// Status Register as the the current one (CPSR).

2
ArmPlatformPkg/Sec/Sec.inf
View File

@ -36,6 +36,7 @@
ArmPlatformPkg/ArmPlatformPkg.dec
[LibraryClasses]
ArmCpuLib
ArmLib
ArmPlatformLib
BaseLib
@ -51,7 +52,6 @@
[FixedPcd]
gArmTokenSpaceGuid.PcdVFPEnabled
gArmPlatformTokenSpaceGuid.PcdMPCoreSupport
gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
gArmTokenSpaceGuid.PcdArmPrimaryCore

26
ArmPlatformPkg/Sec/SecEntryPoint.S
View File

@ -13,15 +13,11 @@
#include <AutoGen.h>
#include <AsmMacroIoLib.h>
#include <Base.h>
#include <Library/PcdLib.h>
#include <Library/ArmPlatformLib.h>
#include "SecInternal.h"
.text
.align 3
GCC_ASM_EXPORT(_ModuleEntryPoint)
GCC_ASM_IMPORT(CEntryPoint)
GCC_ASM_IMPORT(ArmPlatformSecBootAction)
GCC_ASM_IMPORT(ArmPlatformInitializeBootMemory)
@ -30,13 +26,10 @@ GCC_ASM_IMPORT(ArmDisableCachesAndMmu)
GCC_ASM_IMPORT(ArmWriteVBar)
GCC_ASM_IMPORT(ArmReadMpidr)
GCC_ASM_IMPORT(SecVectorTable)
#if (FixedPcdGet32(PcdMPCoreSupport))
GCC_ASM_IMPORT(ArmIsScuEnable)
#endif
GCC_ASM_IMPORT(ArmCpuSynchronizeWait)
GCC_ASM_EXPORT(_ModuleEntryPoint)
StartupAddr: .word ASM_PFX(CEntryPoint)
SecVectorTableAddr: .word ASM_PFX(SecVectorTable)
ASM_PFX(_ModuleEntryPoint):
// First ensure all interrupts are disabled
@ -65,14 +58,11 @@ _IdentifyCpu:
// Only the primary core initialize the memory (SMC)
beq _InitMem
#if (FixedPcdGet32(PcdMPCoreSupport))
// ... The secondary cores wait for SCU to be enabled
_WaitForEnabledScu:
bl ASM_PFX(ArmIsScuEnable)
tst r1, #1
beq _WaitForEnabledScu
_WaitInitMem:
mov r0, #ARM_CPU_EVENT_BOOT_MEM_INIT
bl ASM_PFX(ArmCpuSynchronizeWait)
// Now the Init Mem is initialized, we setup the secondary core stacks
b _SetupSecondaryCoreStack
#endif
_InitMem:
// Initialize Init Boot Memory
@ -110,7 +100,7 @@ _SetupSecondaryCoreStack:
// Get the base of the stack for the secondary cores
LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)
LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)
LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize), r2)
add r1, r1, r2
// StackOffset = CorePos * StackSize

20
ArmPlatformPkg/Sec/SecEntryPoint.asm
View File

@ -13,9 +13,7 @@
#include <AutoGen.h>
#include <AsmMacroIoLib.h>
#include <Base.h>
#include <Library/PcdLib.h>
#include <Library/ArmPlatformLib.h>
#include "SecInternal.h"
INCLUDE AsmMacroIoLib.inc
@ -27,12 +25,9 @@
IMPORT ArmWriteVBar
IMPORT ArmReadMpidr
IMPORT SecVectorTable
IMPORT ArmCpuSynchronizeWait
EXPORT _ModuleEntryPoint
#if (FixedPcdGet32(PcdMPCoreSupport))
IMPORT ArmIsScuEnable
#endif
PRESERVE8
AREA SecEntryPoint, CODE, READONLY
@ -65,14 +60,11 @@ _IdentifyCpu
// Only the primary core initialize the memory (SMC)
beq _InitMem
#if (FixedPcdGet32(PcdMPCoreSupport))
// ... The secondary cores wait for SCU to be enabled
_WaitForEnabledScu
bl ArmIsScuEnable
tst r1, #1
beq _WaitForEnabledScu
_WaitInitMem
mov r0, #ARM_CPU_EVENT_BOOT_MEM_INIT
bl ArmCpuSynchronizeWait
// Now the Init Mem is initialized, we setup the secondary core stacks
b _SetupSecondaryCoreStack
#endif
_InitMem
// Initialize Init Boot Memory

6
ArmPlatformPkg/Sec/SecInternal.h
View File

@ -17,10 +17,12 @@
#define __SEC_H__
#include <Base.h>
#include <Library/ArmLib.h>
#include <Library/ArmCpuLib.h>
#include <Library/ArmPlatformLib.h>
#include <Library/BaseLib.h>
#include <Library/DebugLib.h>
#include <Chipset/ArmV7.h>
#include <Library/PcdLib.h>
#define IS_ALIGNED(Address, Align) (((UINTN)Address & (Align-1)) == 0)