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ArmPkg: Introduce ArmCpuLib to abstract ARM Cpu specific initialization
Every CPUs have their own initialization requirements. This library allows to allows to abstract these initialization requirements into the ARM Platform common components. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12448 6f19259b-4bc3-4df7-8a09-765794883524
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@ -96,9 +96,6 @@
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ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf
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ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf
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ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf
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ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLib.inf
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ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLibPrePi.inf
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ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLibSec.inf
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ArmPkg/Library/ArmLib/Null/NullArmLib.inf
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ArmPkg/Library/ArmTrustZoneLib/ArmTrustZoneLib.inf
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ArmPkg/Library/BaseMemoryLibStm/BaseMemoryLibStm.inf
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@ -115,6 +112,9 @@
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ArmPkg/Library/SemihostLib/SemihostLib.inf
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ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
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ArmPkg/Drivers/ArmCpuLib/ArmCortexA8Lib/ArmCortexA8Lib.inf
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ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.inf
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ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Lib.inf
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ArmPkg/Drivers/CpuDxe/CpuDxe.inf
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ArmPkg/Drivers/CpuPei/CpuPei.inf
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ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf
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@ -55,7 +55,6 @@
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[PcdsFixedAtBuild.common]
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# These PCDs should be FeaturePcds. But we used these PCDs as an '#if' in an ASM file.
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# Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.
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gArmPlatformTokenSpaceGuid.PcdMPCoreSupport|0|UINT32|0x00000003
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gArmPlatformTokenSpaceGuid.PcdClusterCount|1|UINT32|0x00000038
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# Stack for CPU Cores in Secure Mode
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@ -31,6 +31,7 @@
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[LibraryClasses.common]
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ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf
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ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexA8Lib/ArmCortexA8Lib.inf
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ArmPlatformLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbLib.inf
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# ARM PL390 General Interrupt Driver in Secure and Non-secure
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@ -44,7 +45,7 @@
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[BuildOptions]
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RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu Cortex-A8 --fpu=softvfp -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform
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GCC:*_*_ARM_PLATFORM_FLAGS == -march=armv7-a -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform
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GCC:*_*_ARM_PLATFORM_FLAGS == -mcpu=cortex-a8 -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform
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XCODE:*_*_ARM_PLATFORM_FLAGS == -arch armv7 -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform
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@ -31,6 +31,7 @@
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[LibraryClasses.common]
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ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLib.inf
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ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.inf
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ArmPlatformLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbLib.inf
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# ARM PL390 General Interrupt Driver in Secure and Non-secure
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@ -44,7 +45,7 @@
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[BuildOptions]
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RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu Cortex-A9 --fpu=softvfp -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform
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GCC:*_*_ARM_PLATFORM_FLAGS == -march=armv7-a -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform
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GCC:*_*_ARM_PLATFORM_FLAGS == -mcpu=cortex-a9 -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform
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XCODE:*_*_ARM_PLATFORM_FLAGS == -arch armv7 -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform
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@ -79,8 +80,6 @@
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gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x43FE0000
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gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00020000
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gArmPlatformTokenSpaceGuid.PcdMPCoreSupport|1
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# Stacks for MPCores in Secure World
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gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0x4B000000
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# Stacks for MPCores in Monitor Mode
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@ -35,6 +35,7 @@
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[LibraryClasses.common]
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ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLib.inf
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ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.inf
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ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressLib.inf
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ArmTrustZoneLib|ArmPkg/Library/ArmTrustZoneLib/ArmTrustZoneLib.inf
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@ -174,7 +175,6 @@
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gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20
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gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0
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gArmPlatformTokenSpaceGuid.PcdMPCoreSupport|1
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gArmTokenSpaceGuid.PcdVFPEnabled|1
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# Stacks for MPCores in Secure World
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@ -31,6 +31,7 @@
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[LibraryClasses.common]
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ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLib.inf
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ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.inf
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ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf
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ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf
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@ -89,7 +90,6 @@
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gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x0FFE0000
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gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00010000
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gArmPlatformTokenSpaceGuid.PcdMPCoreSupport|1
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gArmTokenSpaceGuid.PcdVFPEnabled|1
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# Stacks for MPCores in Secure World
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@ -31,7 +31,6 @@ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize : Size of the sta
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# CPU / Architectural controllers
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gArmTokenSpaceGuid.PcdGicDistributorBase : Base address of the Distributor of your General Interrupt Controller
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gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase : Base address of the Interface of your General Interrupt Controller
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gArmPlatformTokenSpaceGuid.PcdMPCoreSupport : Set to 1 when MP Core platforms
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# Memory Regions
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gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize : Size of the region reserve for PI & UEFI
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@ -14,13 +14,12 @@
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**/
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#include <Library/DebugAgentLib.h>
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#include <Library/PcdLib.h>
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#include <Library/PrintLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/ArmLib.h>
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#include <Library/SerialPortLib.h>
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#include <Library/ArmPlatformLib.h>
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#include <Library/ArmGicLib.h>
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#include <Library/ArmCpuLib.h>
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#include "SecInternal.h"
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@ -39,8 +38,10 @@ CEntryPoint (
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// Primary CPU clears out the SCU tag RAMs, secondaries wait
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if (IS_PRIMARY_CORE(MpId)) {
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if (FixedPcdGet32(PcdMPCoreSupport)) {
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ArmInvalidScu ();
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ArmCpuSetup (MpId);
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if (ArmIsMpCore()) {
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ArmCpuSynchronizeSignal (ARM_CPU_EVENT_BOOT_MEM_INIT);
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}
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// SEC phase needs to run library constructors by hand. This assumes we are linked against the SerialLib
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@ -58,6 +59,15 @@ CEntryPoint (
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// Now we've got UART, make the check:
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// - The Vector table must be 32-byte aligned
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ASSERT(((UINT32)SecVectorTable & ((1 << 5)-1)) == 0);
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// Enable the GIC distributor and CPU Interface
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// - no other Interrupts are enabled, doesn't have to worry about the priority.
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// - all the cores are in secure state, use secure SGI's
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ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase));
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ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
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} else {
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// Enable the GIC CPU Interface
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ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
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}
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// Invalidate the data cache. Doesn't have to do the Data cache clean.
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@ -72,13 +82,7 @@ CEntryPoint (
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// Enable Full Access to CoProcessors
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ArmWriteCPACR (CPACR_CP_FULL_ACCESS);
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// Enable SWP instructions
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ArmEnableSWPInstruction ();
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// Enable program flow prediction, if supported.
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ArmEnableBranchPrediction ();
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if (FixedPcdGet32(PcdVFPEnabled)) {
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if (FixedPcdGet32 (PcdVFPEnabled)) {
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ArmEnableVFP();
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}
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@ -89,7 +93,7 @@ CEntryPoint (
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// If we skip the PEI Core we could want to initialize the DRAM in the SEC phase.
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// If we are in standalone, we need the initialization to copy the UEFI firmware into DRAM
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if (FeaturePcdGet(PcdSystemMemoryInitializeInSec)) {
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if (FeaturePcdGet (PcdSystemMemoryInitializeInSec)) {
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// Initialize system memory (DRAM)
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ArmPlatformInitializeSystemMemory ();
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}
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@ -104,9 +108,9 @@ CEntryPoint (
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ASSERT(PcdGet32(PcdCPUCoresSecMonStackBase) != 0);
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ASSERT(PcdGet32(PcdCPUCoreSecMonStackSize) != 0);
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if (FixedPcdGet32(PcdMPCoreSupport)) {
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if (ArmIsMpCore()) {
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// Setup SMP in Non Secure world
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ArmSetupSmpNonSecure (GET_CORE_ID(MpId));
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ArmCpuSetupSmpNonSecure (GET_CORE_ID(MpId));
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}
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// Enter Monitor Mode
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@ -120,35 +124,18 @@ CEntryPoint (
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if (IS_PRIMARY_CORE(MpId)) {
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ArmPlatformTrustzoneInit ();
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// Wake up the secondary cores by sending a interrupt to everyone else
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// NOTE 1: The Software Generated Interrupts are always enabled on Cortex-A9
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// MPcore test chip on Versatile Express board, So the Software doesn't have to
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// enable SGI's explicitly.
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// 2: As no other Interrupts are enabled, doesn't have to worry about the priority.
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// 3: As all the cores are in secure state, use secure SGI's
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//
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ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase));
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ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
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// Send SGI to all Secondary core to wake them up from WFI state.
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ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
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// Waiting for the Primary Core to have finished to initialize the Secure World
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ArmCpuSynchronizeSignal (ARM_CPU_EVENT_SECURE_INIT);
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} else {
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// The secondary cores need to wait until the Trustzone chipsets configuration is done
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// before switching to Non Secure World
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// Enabled GIC CPU Interface
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ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
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// Waiting for the SGI from the primary core
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ArmCallWFI();
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// Acknowledge the interrupt and send End of Interrupt signal.
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ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);
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// Waiting for the Primary Core to have finished to initialize the Secure World
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ArmCpuSynchronizeWait (ARM_CPU_EVENT_SECURE_INIT);
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}
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// Transfer the interrupt to Non-secure World
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ArmGicSetupNonSecure (PcdGet32(PcdGicDistributorBase),PcdGet32(PcdGicInterruptInterfaceBase));
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ArmGicSetupNonSecure (PcdGet32(PcdGicDistributorBase), PcdGet32(PcdGicInterruptInterfaceBase));
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// Write to CP15 Non-secure Access Control Register :
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// - Enable CP10 and CP11 accesses in NS World
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@ -165,12 +152,6 @@ CEntryPoint (
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SerialPrint ("Trust Zone Configuration is disabled\n\r");
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}
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// Trustzone is not enabled, just enable the Distributor and CPU interface
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if (IS_PRIMARY_CORE(MpId)) {
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ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase));
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}
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ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
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// With Trustzone support the transition from Sec to Normal world is done by return_from_exception().
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// If we want to keep this function call we need to ensure the SVC's SPSR point to the same Program
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// Status Register as the the current one (CPSR).
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ArmPlatformPkg/ArmPlatformPkg.dec
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[LibraryClasses]
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ArmCpuLib
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ArmLib
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ArmPlatformLib
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BaseLib
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@ -51,7 +52,6 @@
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[FixedPcd]
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gArmTokenSpaceGuid.PcdVFPEnabled
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gArmPlatformTokenSpaceGuid.PcdMPCoreSupport
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gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
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gArmTokenSpaceGuid.PcdArmPrimaryCore
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@ -13,15 +13,11 @@
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#include <AutoGen.h>
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#include <AsmMacroIoLib.h>
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#include <Base.h>
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#include <Library/PcdLib.h>
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#include <Library/ArmPlatformLib.h>
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#include "SecInternal.h"
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.text
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.align 3
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GCC_ASM_EXPORT(_ModuleEntryPoint)
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GCC_ASM_IMPORT(CEntryPoint)
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GCC_ASM_IMPORT(ArmPlatformSecBootAction)
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GCC_ASM_IMPORT(ArmPlatformInitializeBootMemory)
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@ -30,13 +26,10 @@ GCC_ASM_IMPORT(ArmDisableCachesAndMmu)
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GCC_ASM_IMPORT(ArmWriteVBar)
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GCC_ASM_IMPORT(ArmReadMpidr)
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GCC_ASM_IMPORT(SecVectorTable)
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#if (FixedPcdGet32(PcdMPCoreSupport))
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GCC_ASM_IMPORT(ArmIsScuEnable)
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#endif
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GCC_ASM_IMPORT(ArmCpuSynchronizeWait)
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GCC_ASM_EXPORT(_ModuleEntryPoint)
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StartupAddr: .word ASM_PFX(CEntryPoint)
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SecVectorTableAddr: .word ASM_PFX(SecVectorTable)
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ASM_PFX(_ModuleEntryPoint):
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// First ensure all interrupts are disabled
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@ -65,14 +58,11 @@ _IdentifyCpu:
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// Only the primary core initialize the memory (SMC)
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beq _InitMem
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#if (FixedPcdGet32(PcdMPCoreSupport))
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// ... The secondary cores wait for SCU to be enabled
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_WaitForEnabledScu:
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bl ASM_PFX(ArmIsScuEnable)
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tst r1, #1
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beq _WaitForEnabledScu
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_WaitInitMem:
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mov r0, #ARM_CPU_EVENT_BOOT_MEM_INIT
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bl ASM_PFX(ArmCpuSynchronizeWait)
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// Now the Init Mem is initialized, we setup the secondary core stacks
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b _SetupSecondaryCoreStack
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#endif
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_InitMem:
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// Initialize Init Boot Memory
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@ -110,7 +100,7 @@ _SetupSecondaryCoreStack:
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// Get the base of the stack for the secondary cores
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LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)
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LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)
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LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize), r2)
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add r1, r1, r2
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// StackOffset = CorePos * StackSize
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#include <AutoGen.h>
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#include <AsmMacroIoLib.h>
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#include <Base.h>
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#include <Library/PcdLib.h>
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#include <Library/ArmPlatformLib.h>
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#include "SecInternal.h"
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INCLUDE AsmMacroIoLib.inc
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@ -27,12 +25,9 @@
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IMPORT ArmWriteVBar
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IMPORT ArmReadMpidr
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IMPORT SecVectorTable
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IMPORT ArmCpuSynchronizeWait
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EXPORT _ModuleEntryPoint
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#if (FixedPcdGet32(PcdMPCoreSupport))
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IMPORT ArmIsScuEnable
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#endif
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PRESERVE8
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AREA SecEntryPoint, CODE, READONLY
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@ -65,14 +60,11 @@ _IdentifyCpu
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// Only the primary core initialize the memory (SMC)
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beq _InitMem
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#if (FixedPcdGet32(PcdMPCoreSupport))
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// ... The secondary cores wait for SCU to be enabled
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_WaitForEnabledScu
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bl ArmIsScuEnable
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tst r1, #1
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beq _WaitForEnabledScu
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_WaitInitMem
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mov r0, #ARM_CPU_EVENT_BOOT_MEM_INIT
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bl ArmCpuSynchronizeWait
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// Now the Init Mem is initialized, we setup the secondary core stacks
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b _SetupSecondaryCoreStack
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#endif
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_InitMem
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// Initialize Init Boot Memory
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#define __SEC_H__
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#include <Base.h>
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#include <Library/ArmLib.h>
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#include <Library/ArmCpuLib.h>
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#include <Library/ArmPlatformLib.h>
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#include <Library/BaseLib.h>
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#include <Library/DebugLib.h>
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#include <Chipset/ArmV7.h>
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#include <Library/PcdLib.h>
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#define IS_ALIGNED(Address, Align) (((UINTN)Address & (Align-1)) == 0)
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