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ArmPkg: Changed ARM CPU SetMemoryAttributes to always use strongly ordered for the EFI_MEMORY_UC attribute 

Changed ARM CPU SetMemoryAttributes to always use strongly ordered for the EFI_MEMORY_UC attribute. 

Signed-off-by: 
Reviewed-by: eugenecohen
Reviewed-by: yanivtal




git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13011 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin 2012-02-14 15:54:05 +00:00
parent cbafa15e29
commit 9207c5d758
3 changed files with 4 additions and 17 deletions
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2
ArmPkg/ArmPkg.dec
View File

@ -65,8 +65,6 @@
# it has been configured by the CPU DXE
gArmTokenSpaceGuid.PcdDebuggerExceptionSupport|FALSE|BOOLEAN|0x00000032
gArmTokenSpaceGuid.PcdEfiUncachedMemoryToStronglyOrdered|FALSE|BOOLEAN|0x00000025
[PcdsFixedAtBuild.common]
gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006

1
ArmPkg/Drivers/CpuDxe/CpuDxe.inf
View File

@ -81,7 +81,6 @@
gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport
gArmTokenSpaceGuid.PcdRelocateVectorTable
gArmTokenSpaceGuid.PcdDebuggerExceptionSupport
gArmTokenSpaceGuid.PcdEfiUncachedMemoryToStronglyOrdered
[Depex]
TRUE

18
ArmPkg/Drivers/CpuDxe/Mmu.c
View File

@ -498,13 +498,8 @@ UpdatePageEntries (
case EFI_MEMORY_UC:
// modify cacheability attributes
EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;
if (FeaturePcdGet(PcdEfiUncachedMemoryToStronglyOrdered)) {
// map to strongly ordered
EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0
} else {
// map to normal non-cachable
EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0
}
// map to strongly ordered
EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0
break;
case EFI_MEMORY_WC:
@ -646,13 +641,8 @@ UpdateSectionEntries (
case EFI_MEMORY_UC:
// modify cacheability attributes
EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;
if (FeaturePcdGet(PcdEfiUncachedMemoryToStronglyOrdered)) {
// map to strongly ordered
EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0
} else {
// map to normal non-cachable
EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0
}
// map to strongly ordered
EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0
break;
case EFI_MEMORY_WC: