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ArmPkg/ArmGicLib: Added function ArmGicSetSecureInterrupts() to define the secure interrupts 

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13122 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin 2012-03-26 10:45:27 +00:00
parent f15f91a22f
commit 9253410646
3 changed files with 49 additions and 5 deletions
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35
ArmPkg/Drivers/PL390Gic/PL390GicSec.c
View File

@ -12,7 +12,8 @@
*
**/
#include <Uefi.h>
#include <Base.h>
#include <Library/DebugLib.h>
#include <Library/IoLib.h>
#include <Library/ArmGicLib.h>
@ -29,6 +30,7 @@ ArmGicSetupNonSecure (
{
UINTN InterruptId;
UINTN CachedPriorityMask;
UINTN Index;
CachedPriorityMask = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR);
@ -46,14 +48,39 @@ ArmGicSetupNonSecure (
}
// Ensure all GIC interrupts are Non-Secure
MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff); // IRQs 0-31 are Non-Secure : Private Peripheral Interrupt[31:16] & Software Generated Interrupt[15:0]
MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + 4, 0xffffffff); // IRQs 32-63 are Non-Secure : Shared Peripheral Interrupt
MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + 8, 0xffffffff); // And another 32 in case we're on the testchip : Shared Peripheral Interrupt (2)
for (Index = 0; Index < (PcdGet32(PcdGicNumInterrupts) / 32); Index++) {
MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), 0xffffffff);
}
// Ensure all interrupts can get through the priority mask
MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, CachedPriorityMask);
}
/*
* This function configures the interrupts set by the mask to be secure.
*
*/
VOID
EFIAPI
ArmGicSetSecureInterrupts (
IN UINTN GicDistributorBase,
IN UINTN* GicSecureInterruptMask,
IN UINTN GicSecureInterruptMaskSize
)
{
UINTN Index;
UINT32 InterruptStatus;
// We must not have more interrupts defined by the mask than the number of available interrupts
ASSERT(GicSecureInterruptMaskSize <= (PcdGet32(PcdGicNumInterrupts) / 32));
// Set all the interrupts defined by the mask as Secure
for (Index = 0; Index < GicSecureInterruptMaskSize; Index++) {
InterruptStatus = MmioRead32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4));
MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), InterruptStatus & (~GicSecureInterruptMask[Index]));
}
}
VOID
EFIAPI
ArmGicEnableInterruptInterface (

9
ArmPkg/Drivers/PL390Gic/PL390GicSecLib.inf
View File

@ -26,3 +26,12 @@
[Packages]
ArmPkg/ArmPkg.dec
MdePkg/MdePkg.dec
[LibraryClasses]
DebugLib
IoLib
PcdLib
[FixedPcd.common]
gArmTokenSpaceGuid.PcdGicNumInterrupts

10
ArmPkg/Include/Library/ArmGicLib.h
View File

@ -72,7 +72,7 @@
//
// GIC SEC interfaces
// GIC Secure interfaces
//
VOID
EFIAPI
@ -81,6 +81,14 @@ ArmGicSetupNonSecure (
IN INTN GicInterruptInterfaceBase
);
VOID
EFIAPI
ArmGicSetSecureInterrupts (
IN UINTN GicDistributorBase,
IN UINTN* GicSecureInterruptMask,
IN UINTN GicSecureInterruptMaskSize
);
VOID
EFIAPI
ArmGicEnableInterruptInterface (