mirror of https://github.com/acidanthera/audk.git
CpuPageTableLib: Fix bug that wrongly requires extra size for mapping
With following paging structure to map [2M-4K, 2M] as P = 1, RW = 0, [2M, 4M] as P = 1, RW = 1: PML4[0] -> PDPTE[0] -> PDE[0](RW = 0) -> PTE[255](P = 0, RW = 0) -> PDE[1](RW = 1) When a new request to map [2M-4K, 2M+4K] as P = 1, RW = 1, CpuPageTableMap() wrongly requests 4K buffer size for the new mapping request. But in fact, for [2M-4K, 2M] request, PTE[255] can be changed in place, for [2M, 2M+4K], no change is needed because PDE[1].RW = 1 already. The change fixes the bug. Signed-off-by: Ray Ni <ray.ni@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
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@ -272,6 +272,7 @@ PageTableLibMapInLevel (
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IA32_MAP_ATTRIBUTE ChildAttribute;
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IA32_MAP_ATTRIBUTE ChildMask;
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IA32_MAP_ATTRIBUTE CurrentMask;
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IA32_MAP_ATTRIBUTE LocalParentAttribute;
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ASSERT (Level != 0);
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ASSERT ((Attribute != NULL) && (Mask != NULL));
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@ -284,6 +285,9 @@ PageTableLibMapInLevel (
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NopAttribute.Bits.ReadWrite = 1;
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NopAttribute.Bits.UserSupervisor = 1;
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LocalParentAttribute.Uint64 = ParentAttribute->Uint64;
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ParentAttribute = &LocalParentAttribute;
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//
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// ParentPagingEntry ONLY is deferenced for checking Present and MustBeOne bits
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// when Modify is FALSE.
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@ -420,7 +424,7 @@ PageTableLibMapInLevel (
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}
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if (IsPle (&PagingEntry[Index], Level)) {
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PageTableLibSetPle (Level - 1, &PagingEntry[Index], 0, &ChildAttribute, &ChildMask);
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PageTableLibSetPle (Level, &PagingEntry[Index], 0, &ChildAttribute, &ChildMask);
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} else {
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PageTableLibSetPnle (&PagingEntry[Index].Pnle, &ChildAttribute, &ChildMask);
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}
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@ -664,13 +668,6 @@ PageTableMap (
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//
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// Update the page table when the supplied buffer is sufficient.
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//
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ParentAttribute.Uint64 = 0;
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ParentAttribute.Bits.PageTableBaseAddress = 1;
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ParentAttribute.Bits.Present = 1;
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ParentAttribute.Bits.ReadWrite = 1;
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ParentAttribute.Bits.UserSupervisor = 1;
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ParentAttribute.Bits.Nx = 0;
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Status = PageTableLibMapInLevel (
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&TopPagingEntry,
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&ParentAttribute,
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