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CorebootPayloadPkg DSC: Change the section alignment option
The current CorebootPayloadPkg will print the following message "InsertImageRecord - Section Alignment(0x20) is not 4K" during boot. It is caused by the section alignment arranged by the linker. This patch change the alignment to 4K for runtime drivers. Cc: Prince Agyeman <prince.agyeman@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
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@ -61,6 +61,7 @@ INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
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[FV.DXEFV]
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[FV.DXEFV]
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BlockSize = 0x1000
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BlockSize = 0x1000
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FvForceRebase = FALSE
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FvAlignment = 16
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FvAlignment = 16
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ERASE_POLARITY = 1
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ERASE_POLARITY = 1
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MEMORY_MAPPED = TRUE
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MEMORY_MAPPED = TRUE
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@ -88,6 +88,9 @@
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INTEL:RELEASE_*_*_CC_FLAGS = /D MDEPKG_NDEBUG
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INTEL:RELEASE_*_*_CC_FLAGS = /D MDEPKG_NDEBUG
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MSFT:RELEASE_*_*_CC_FLAGS = /D MDEPKG_NDEBUG
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MSFT:RELEASE_*_*_CC_FLAGS = /D MDEPKG_NDEBUG
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[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
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MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096
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################################################################################
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################################################################################
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#
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#
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# SKU Identification section - list of all SKU IDs supported by this Platform.
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# SKU Identification section - list of all SKU IDs supported by this Platform.
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@ -90,6 +90,9 @@
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INTEL:RELEASE_*_*_CC_FLAGS = /D MDEPKG_NDEBUG
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INTEL:RELEASE_*_*_CC_FLAGS = /D MDEPKG_NDEBUG
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MSFT:RELEASE_*_*_CC_FLAGS = /D MDEPKG_NDEBUG
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MSFT:RELEASE_*_*_CC_FLAGS = /D MDEPKG_NDEBUG
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[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
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MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096
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################################################################################
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################################################################################
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#
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#
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# SKU Identification section - list of all SKU IDs supported by this Platform.
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# SKU Identification section - list of all SKU IDs supported by this Platform.
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