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CorebootPayloadPkg DSC: Change the section alignment option

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The current CorebootPayloadPkg will print the following message
"InsertImageRecord - Section Alignment(0x20) is not 4K" during
boot. It is caused by the section alignment arranged by the linker.
This patch change the alignment to 4K for runtime drivers.

Cc: Prince Agyeman <prince.agyeman@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
This commit is contained in:
Maurice Ma 2016-10-26 11:15:14 -07:00
parent 200eaa3d7d
commit 937f5cb6ac
3 changed files with 7 additions and 0 deletions
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1
CorebootPayloadPkg/CorebootPayloadPkg.fdf
View File

@ -61,6 +61,7 @@ INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
[FV.DXEFV]
BlockSize = 0x1000
FvForceRebase = FALSE
FvAlignment = 16
ERASE_POLARITY = 1
MEMORY_MAPPED = TRUE

3
CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
View File

@ -88,6 +88,9 @@
INTEL:RELEASE_*_*_CC_FLAGS = /D MDEPKG_NDEBUG
MSFT:RELEASE_*_*_CC_FLAGS = /D MDEPKG_NDEBUG
[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096
################################################################################
#
# SKU Identification section - list of all SKU IDs supported by this Platform.

3
CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
View File

@ -90,6 +90,9 @@
INTEL:RELEASE_*_*_CC_FLAGS = /D MDEPKG_NDEBUG
MSFT:RELEASE_*_*_CC_FLAGS = /D MDEPKG_NDEBUG
[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096
################################################################################
#
# SKU Identification section - list of all SKU IDs supported by this Platform.