mirror of https://github.com/acidanthera/audk.git
ArmPlatformPkg/PL180MciDxe: Fixed coding style
Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13586 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin
parent
260675b073
commit
93b429fc21
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@ -1,7 +1,7 @@
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/** @file
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This file implement the MMC Host Protocol for the ARM PrimeCell PL180.
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Copyright (c) 2011, ARM Limited. All rights reserved.
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Copyright (c) 2011-2012, ARM Limited. All rights reserved.
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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@ -27,12 +27,15 @@ EFI_MMC_HOST_PROTOCOL *gpMmcHost;
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#define MMCI0_POW2_BLOCKLEN 9
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#define MMCI0_TIMEOUT 1000
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#define SYS_MCI_CARDIN BIT0
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#define SYS_MCI_WPROT BIT1
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BOOLEAN
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MciIsPowerOn (
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VOID
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)
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{
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return ((MmioRead32(MCI_POWER_CONTROL_REG) & 0x3) == MCI_POWER_ON);
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return ((MmioRead32 (MCI_POWER_CONTROL_REG) & MCI_POWER_ON) == MCI_POWER_ON);
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}
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EFI_STATUS
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@ -40,7 +43,7 @@ MciInitialize (
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VOID
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)
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{
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MCI_TRACE("MciInitialize()");
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MCI_TRACE ("MciInitialize()");
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return EFI_SUCCESS;
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}
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@ -49,7 +52,7 @@ MciIsCardPresent (
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IN EFI_MMC_HOST_PROTOCOL *This
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)
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{
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return (MmioRead32(FixedPcdGet32(PcdPL180SysMciRegAddress)) & 1);
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return (MmioRead32 (FixedPcdGet32 (PcdPL180SysMciRegAddress)) & SYS_MCI_CARDIN);
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}
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BOOLEAN
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@ -57,7 +60,7 @@ MciIsReadOnly (
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IN EFI_MMC_HOST_PROTOCOL *This
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)
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{
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return (MmioRead32(FixedPcdGet32(PcdPL180SysMciRegAddress)) & 2);
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return (MmioRead32 (FixedPcdGet32 (PcdPL180SysMciRegAddress)) & SYS_MCI_WPROT);
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}
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#if 0
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@ -92,13 +95,13 @@ MciPrepareDataPath (
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)
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{
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// Set Data Length & Data Timer
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MmioWrite32 (MCI_DATA_TIMER_REG,0xFFFFFFF);
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MmioWrite32 (MCI_DATA_LENGTH_REG,MMCI0_BLOCKLEN);
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MmioWrite32 (MCI_DATA_TIMER_REG, 0xFFFFFFF);
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MmioWrite32 (MCI_DATA_LENGTH_REG, MMCI0_BLOCKLEN);
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#ifndef USE_STREAM
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//Note: we are using a hardcoded BlockLen (=512). If we decide to use a variable size, we could
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// compute the pow2 of BlockLen with the above function GetPow2BlockLen()
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MmioWrite32 (MCI_DATA_CTL_REG, MCI_DATACTL_ENABLE | MCI_DATACTL_DMA_ENABLE | TransferDirection | (MMCI0_POW2_BLOCKLEN << 4));
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//Note: we are using a hardcoded BlockLen (==512). If we decide to use a variable size, we could
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// compute the pow2 of BlockLen with the above function GetPow2BlockLen ()
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MmioWrite32 (MCI_DATA_CTL_REG, MCI_DATACTL_ENABLE | MCI_DATACTL_DMA_ENABLE | TransferDirection | (MMCI0_POW2_BLOCKLEN << 4));
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#else
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MmioWrite32 (MCI_DATA_CTL_REG, MCI_DATACTL_ENABLE | MCI_DATACTL_DMA_ENABLE | TransferDirection | MCI_DATACTL_STREAM_TRANS);
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#endif
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@ -111,21 +114,21 @@ MciSendCommand (
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IN UINT32 Argument
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)
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{
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UINT32 Status;
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UINT32 Cmd;
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UINTN RetVal;
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UINTN CmdCtrlReg;
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UINT32 Status;
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UINT32 Cmd;
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UINTN RetVal;
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UINTN CmdCtrlReg;
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RetVal = EFI_SUCCESS;
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if ((MmcCmd == MMC_CMD17) || (MmcCmd == MMC_CMD11)) {
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MciPrepareDataPath(MCI_DATACTL_CARD_TO_CONT);
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MciPrepareDataPath (MCI_DATACTL_CARD_TO_CONT);
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} else if ((MmcCmd == MMC_CMD24) || (MmcCmd == MMC_CMD20)) {
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MciPrepareDataPath(MCI_DATACTL_CONT_TO_CARD);
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MciPrepareDataPath (MCI_DATACTL_CONT_TO_CARD);
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}
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// Create Command for PL180
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Cmd = (MMC_GET_INDX(MmcCmd) & INDX_MASK) | MCI_CPSM_ENABLED;
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Cmd = (MMC_GET_INDX (MmcCmd) & INDX_MASK) | MCI_CPSM_ENABLE;
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if (MmcCmd & MMC_CMD_WAIT_RESPONSE) {
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Cmd |= MCI_CPSM_WAIT_RESPONSE;
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}
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@ -135,29 +138,29 @@ MciSendCommand (
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}
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// Clear Status register static flags
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MmioWrite32(MCI_CLEAR_STATUS_REG,0x7FF);
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MmioWrite32 (MCI_CLEAR_STATUS_REG, MCI_CLR_ALL_STATUS);
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//Write to command argument register
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MmioWrite32(MCI_ARGUMENT_REG,Argument);
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// Write to command argument register
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MmioWrite32 (MCI_ARGUMENT_REG, Argument);
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//Write to command register
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MmioWrite32(MCI_COMMAND_REG,Cmd);
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// Write to command register
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MmioWrite32 (MCI_COMMAND_REG, Cmd);
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if (Cmd & MCI_CPSM_WAIT_RESPONSE) {
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Status = MmioRead32(MCI_STATUS_REG);
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Status = MmioRead32 (MCI_STATUS_REG);
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while (!(Status & (MCI_STATUS_CMD_RESPEND | MCI_STATUS_CMD_CMDCRCFAIL | MCI_STATUS_CMD_CMDTIMEOUT | MCI_STATUS_CMD_START_BIT_ERROR))) {
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Status = MmioRead32(MCI_STATUS_REG);
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}
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if ((Status & MCI_STATUS_CMD_START_BIT_ERROR)) {
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DEBUG ((EFI_D_ERROR, "MciSendCommand(CmdIndex:%d) Start bit Error! Response:0x%X Status:0x%x\n",(Cmd & 0x3F),MmioRead32(MCI_RESPONSE0_REG),Status));
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DEBUG ((EFI_D_ERROR, "MciSendCommand(CmdIndex:%d) Start bit Error! Response:0x%X Status:0x%x\n", (Cmd & 0x3F), MmioRead32 (MCI_RESPONSE0_REG), Status));
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RetVal = EFI_NO_RESPONSE;
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goto Exit;
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} else if ((Status & MCI_STATUS_CMD_CMDTIMEOUT)) {
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//DEBUG ((EFI_D_ERROR, "MciSendCommand(CmdIndex:%d) TIMEOUT! Response:0x%X Status:0x%x\n",(Cmd & 0x3F),MmioRead32(MCI_RESPONSE0_REG),Status));
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//DEBUG ((EFI_D_ERROR, "MciSendCommand(CmdIndex:%d) TIMEOUT! Response:0x%X Status:0x%x\n", (Cmd & 0x3F), MmioRead32 (MCI_RESPONSE0_REG), Status));
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RetVal = EFI_TIMEOUT;
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goto Exit;
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} else if ((!(MmcCmd & MMC_CMD_NO_CRC_RESPONSE)) && (Status & MCI_STATUS_CMD_CMDCRCFAIL)) {
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} else if ((! (MmcCmd & MMC_CMD_NO_CRC_RESPONSE)) && (Status & MCI_STATUS_CMD_CMDCRCFAIL)) {
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// The CMD1 and response type R3 do not contain CRC. We should ignore the CRC failed Status.
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RetVal = EFI_CRC_ERROR;
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goto Exit;
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@ -191,10 +194,10 @@ MciSendCommand (
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}
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Exit:
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// Disable Command Path
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CmdCtrlReg = MmioRead32(MCI_COMMAND_REG);
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MmioWrite32(MCI_COMMAND_REG, (CmdCtrlReg & ~MCI_CPSM_ENABLED));
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return RetVal;
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// Disable Command Path
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CmdCtrlReg = MmioRead32 (MCI_COMMAND_REG);
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MmioWrite32 (MCI_COMMAND_REG, (CmdCtrlReg & ~MCI_CPSM_ENABLE));
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return RetVal;
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}
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EFI_STATUS
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@ -208,16 +211,18 @@ MciReceiveResponse (
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return EFI_INVALID_PARAMETER;
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}
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if ((Type == MMC_RESPONSE_TYPE_R1) || (Type == MMC_RESPONSE_TYPE_R1b) ||
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(Type == MMC_RESPONSE_TYPE_R3) || (Type == MMC_RESPONSE_TYPE_R6) ||
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(Type == MMC_RESPONSE_TYPE_R7))
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if ( (Type == MMC_RESPONSE_TYPE_R1)
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|| (Type == MMC_RESPONSE_TYPE_R1b)
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|| (Type == MMC_RESPONSE_TYPE_R3)
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|| (Type == MMC_RESPONSE_TYPE_R6)
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|| (Type == MMC_RESPONSE_TYPE_R7))
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{
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Buffer[0] = MmioRead32(MCI_RESPONSE3_REG);
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Buffer[0] = MmioRead32 (MCI_RESPONSE3_REG);
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} else if (Type == MMC_RESPONSE_TYPE_R2) {
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Buffer[0] = MmioRead32(MCI_RESPONSE0_REG);
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Buffer[1] = MmioRead32(MCI_RESPONSE1_REG);
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Buffer[2] = MmioRead32(MCI_RESPONSE2_REG);
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Buffer[3] = MmioRead32(MCI_RESPONSE3_REG);
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Buffer[0] = MmioRead32 (MCI_RESPONSE0_REG);
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Buffer[1] = MmioRead32 (MCI_RESPONSE1_REG);
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Buffer[2] = MmioRead32 (MCI_RESPONSE2_REG);
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Buffer[3] = MmioRead32 (MCI_RESPONSE3_REG);
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}
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return EFI_SUCCESS;
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@ -244,7 +249,7 @@ MciReadBlockData (
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Finish = MMCI0_BLOCKLEN / 4;
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do {
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// Read the Status flags
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Status = MmioRead32(MCI_STATUS_REG);
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Status = MmioRead32 (MCI_STATUS_REG);
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// Do eight reads if possible else a single read
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if (Status & MCI_STATUS_CMD_RXFIFOHALFFULL) {
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@ -269,16 +274,16 @@ MciReadBlockData (
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Loop++;
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} else {
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//Check for error conditions and timeouts
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if(Status & MCI_STATUS_CMD_DATATIMEOUT) {
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DEBUG ((EFI_D_ERROR, "MciReadBlockData(): TIMEOUT! Response:0x%X Status:0x%x\n",MmioRead32(MCI_RESPONSE0_REG),Status));
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if (Status & MCI_STATUS_CMD_DATATIMEOUT) {
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DEBUG ((EFI_D_ERROR, "MciReadBlockData(): TIMEOUT! Response:0x%X Status:0x%x\n", MmioRead32 (MCI_RESPONSE0_REG), Status));
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RetVal = EFI_TIMEOUT;
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break;
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} else if(Status & MCI_STATUS_CMD_DATACRCFAIL) {
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DEBUG ((EFI_D_ERROR, "MciReadBlockData(): CRC Error! Response:0x%X Status:0x%x\n",MmioRead32(MCI_RESPONSE0_REG),Status));
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} else if (Status & MCI_STATUS_CMD_DATACRCFAIL) {
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DEBUG ((EFI_D_ERROR, "MciReadBlockData(): CRC Error! Response:0x%X Status:0x%x\n", MmioRead32 (MCI_RESPONSE0_REG), Status));
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RetVal = EFI_CRC_ERROR;
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break;
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} else if(Status & MCI_STATUS_CMD_START_BIT_ERROR) {
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DEBUG ((EFI_D_ERROR, "MciReadBlockData(): Start-bit Error! Response:0x%X Status:0x%x\n",MmioRead32(MCI_RESPONSE0_REG),Status));
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} else if (Status & MCI_STATUS_CMD_START_BIT_ERROR) {
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DEBUG ((EFI_D_ERROR, "MciReadBlockData(): Start-bit Error! Response:0x%X Status:0x%x\n", MmioRead32 (MCI_RESPONSE0_REG), Status));
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RetVal = EFI_NO_RESPONSE;
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break;
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}
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@ -289,14 +294,14 @@ MciReadBlockData (
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}
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} while ((Loop < Finish));
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//Clear Status flags
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MmioWrite32(MCI_CLEAR_STATUS_REG, 0x7FF);
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// Clear Status flags
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MmioWrite32 (MCI_CLEAR_STATUS_REG, MCI_CLR_ALL_STATUS);
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//Disable Data path
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DataCtrlReg = MmioRead32(MCI_DATA_CTL_REG);
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MmioWrite32(MCI_DATA_CTL_REG, (DataCtrlReg & 0xFE));
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//Disable Data path
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DataCtrlReg = MmioRead32 (MCI_DATA_CTL_REG);
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MmioWrite32 (MCI_DATA_CTL_REG, (DataCtrlReg & MCI_DATACTL_DISABLE_MASK));
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return RetVal;
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return RetVal;
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}
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EFI_STATUS
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@ -322,7 +327,7 @@ MciWriteBlockData (
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Timer = MMCI0_TIMEOUT * 100;
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do {
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// Read the Status flags
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Status = MmioRead32(MCI_STATUS_REG);
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Status = MmioRead32 (MCI_STATUS_REG);
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// Do eight writes if possible else a single write
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if (Status & MCI_STATUS_CMD_TXFIFOHALFEMPTY) {
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@ -346,16 +351,16 @@ MciWriteBlockData (
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MmioWrite32(MCI_FIFO_REG, Buffer[Loop]);
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Loop++;
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} else {
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//Check for error conditions and timeouts
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if(Status & MCI_STATUS_CMD_DATATIMEOUT) {
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DEBUG ((EFI_D_ERROR, "MciWriteBlockData(): TIMEOUT! Response:0x%X Status:0x%x\n",MmioRead32(MCI_RESPONSE0_REG),Status));
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// Check for error conditions and timeouts
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if (Status & MCI_STATUS_CMD_DATATIMEOUT) {
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DEBUG ((EFI_D_ERROR, "MciWriteBlockData(): TIMEOUT! Response:0x%X Status:0x%x\n", MmioRead32 (MCI_RESPONSE0_REG), Status));
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RetVal = EFI_TIMEOUT;
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goto Exit;
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} else if(Status & MCI_STATUS_CMD_DATACRCFAIL) {
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DEBUG ((EFI_D_ERROR, "MciWriteBlockData(): CRC Error! Response:0x%X Status:0x%x\n",MmioRead32(MCI_RESPONSE0_REG),Status));
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} else if (Status & MCI_STATUS_CMD_DATACRCFAIL) {
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DEBUG ((EFI_D_ERROR, "MciWriteBlockData(): CRC Error! Response:0x%X Status:0x%x\n", MmioRead32 (MCI_RESPONSE0_REG), Status));
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RetVal = EFI_CRC_ERROR;
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goto Exit;
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} else if(Status & MCI_STATUS_CMD_TX_UNDERRUN) {
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} else if (Status & MCI_STATUS_CMD_TX_UNDERRUN) {
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DEBUG ((EFI_D_ERROR, "MciWriteBlockData(): TX buffer Underrun! Response:0x%X Status:0x%x, Number of bytes written 0x%x\n",MmioRead32(MCI_RESPONSE0_REG),Status, Loop));
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RetVal = EFI_BUFFER_TOO_SMALL;
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ASSERT(0);
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@ -365,37 +370,37 @@ MciWriteBlockData (
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} while (Loop < Finish);
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// Wait for FIFO to drain
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Timer = MMCI0_TIMEOUT * 60;
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Status = MmioRead32(MCI_STATUS_REG);
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Timer = MMCI0_TIMEOUT * 60;
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Status = MmioRead32 (MCI_STATUS_REG);
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#ifndef USE_STREAM
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// Single block
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while (((Status & MCI_STATUS_CMD_TXDONE) != MCI_STATUS_CMD_TXDONE) && Timer) {
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while (((Status & MCI_STATUS_TXDONE) != MCI_STATUS_TXDONE) && Timer) {
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#else
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// Stream
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while (((Status & MCI_STATUS_CMD_DATAEND) != MCI_STATUS_CMD_DATAEND) && Timer) {
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#endif
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NanoSecondDelay(10);
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Status = MmioRead32(MCI_STATUS_REG);
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Status = MmioRead32 (MCI_STATUS_REG);
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Timer--;
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}
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if(Timer == 0) {
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if (Timer == 0) {
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DEBUG ((EFI_D_ERROR, "MciWriteBlockData(): Data End timeout Number of bytes written 0x%x\n",Loop));
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ASSERT(Timer > 0);
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ASSERT (Timer > 0);
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return EFI_TIMEOUT;
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}
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//Clear Status flags
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MmioWrite32(MCI_CLEAR_STATUS_REG, 0x7FF);
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// Clear Status flags
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MmioWrite32 (MCI_CLEAR_STATUS_REG, MCI_CLR_ALL_STATUS);
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if (Timer == 0) {
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RetVal = EFI_TIMEOUT;
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}
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Exit:
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//Disable Data path
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DataCtrlReg = MmioRead32(MCI_DATA_CTL_REG);
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MmioWrite32(MCI_DATA_CTL_REG, (DataCtrlReg & 0xFE));
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return RetVal;
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// Disable Data path
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DataCtrlReg = MmioRead32 (MCI_DATA_CTL_REG);
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MmioWrite32 (MCI_DATA_CTL_REG, (DataCtrlReg & MCI_DATACTL_DISABLE_MASK));
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return RetVal;
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}
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EFI_STATUS
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@ -406,59 +411,59 @@ MciNotifyState (
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{
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UINT32 Data32;
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switch(State) {
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switch (State) {
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case MmcInvalidState:
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ASSERT(0);
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ASSERT (0);
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break;
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case MmcHwInitializationState:
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// If device already turn on then restart it
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Data32 = MmioRead32(MCI_POWER_CONTROL_REG);
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Data32 = MmioRead32 (MCI_POWER_CONTROL_REG);
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if ((Data32 & 0x2) == MCI_POWER_UP) {
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MCI_TRACE("MciNotifyState(MmcHwInitializationState): TurnOff MCI");
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MCI_TRACE ("MciNotifyState(MmcHwInitializationState): TurnOff MCI");
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// Turn off
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MmioWrite32(MCI_CLOCK_CONTROL_REG, 0);
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MmioWrite32(MCI_POWER_CONTROL_REG, 0);
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MicroSecondDelay(100);
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MmioWrite32 (MCI_CLOCK_CONTROL_REG, 0);
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MmioWrite32 (MCI_POWER_CONTROL_REG, 0);
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MicroSecondDelay (100);
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}
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MCI_TRACE("MciNotifyState(MmcHwInitializationState): TurnOn MCI");
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MCI_TRACE ("MciNotifyState(MmcHwInitializationState): TurnOn MCI");
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// Setup clock
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// - 0x1D = 29 => should be the clock divider to be less than 400kHz at MCLK = 24Mhz
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MmioWrite32(MCI_CLOCK_CONTROL_REG,0x1D | MCI_CLOCK_ENABLE | MCI_CLOCK_POWERSAVE);
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MmioWrite32 (MCI_CLOCK_CONTROL_REG, 0x1D | MCI_CLOCK_ENABLE | MCI_CLOCK_POWERSAVE);
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//MmioWrite32(MCI_CLOCK_CONTROL_REG,0x1D | MCI_CLOCK_ENABLE);
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// Set the voltage
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MmioWrite32(MCI_POWER_CONTROL_REG,MCI_POWER_OPENDRAIN | (15<<2));
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MmioWrite32(MCI_POWER_CONTROL_REG,MCI_POWER_ROD | MCI_POWER_OPENDRAIN | (15<<2) | MCI_POWER_UP);
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MicroSecondDelay(10);
|
||||
MmioWrite32(MCI_POWER_CONTROL_REG,MCI_POWER_ROD | MCI_POWER_OPENDRAIN | (15<<2) | MCI_POWER_ON);
|
||||
MicroSecondDelay(100);
|
||||
MmioWrite32 (MCI_POWER_CONTROL_REG, MCI_POWER_OPENDRAIN | (15<<2));
|
||||
MmioWrite32 (MCI_POWER_CONTROL_REG, MCI_POWER_ROD | MCI_POWER_OPENDRAIN | (15<<2) | MCI_POWER_UP);
|
||||
MicroSecondDelay (10);
|
||||
MmioWrite32 (MCI_POWER_CONTROL_REG, MCI_POWER_ROD | MCI_POWER_OPENDRAIN | (15<<2) | MCI_POWER_ON);
|
||||
MicroSecondDelay (100);
|
||||
|
||||
// Set Data Length & Data Timer
|
||||
MmioWrite32(MCI_DATA_TIMER_REG,0xFFFFF);
|
||||
MmioWrite32(MCI_DATA_LENGTH_REG,8);
|
||||
MmioWrite32 (MCI_DATA_TIMER_REG, 0xFFFFF);
|
||||
MmioWrite32 (MCI_DATA_LENGTH_REG, 8);
|
||||
|
||||
ASSERT((MmioRead32(MCI_POWER_CONTROL_REG) & 0x3) == MCI_POWER_ON);
|
||||
ASSERT ((MmioRead32 (MCI_POWER_CONTROL_REG) & 0x3) == MCI_POWER_ON);
|
||||
break;
|
||||
case MmcIdleState:
|
||||
MCI_TRACE("MciNotifyState(MmcIdleState)");
|
||||
MCI_TRACE ("MciNotifyState(MmcIdleState)");
|
||||
break;
|
||||
case MmcReadyState:
|
||||
MCI_TRACE("MciNotifyState(MmcReadyState)");
|
||||
MCI_TRACE ("MciNotifyState(MmcReadyState)");
|
||||
break;
|
||||
case MmcIdentificationState:
|
||||
MCI_TRACE("MciNotifyState(MmcIdentificationState)");
|
||||
MCI_TRACE ("MciNotifyState (MmcIdentificationState)");
|
||||
break;
|
||||
case MmcStandByState:{
|
||||
volatile UINT32 PwrCtrlReg;
|
||||
MCI_TRACE("MciNotifyState(MmcStandByState)");
|
||||
MCI_TRACE ("MciNotifyState (MmcStandByState)");
|
||||
|
||||
// Enable MCICMD push-pull drive
|
||||
PwrCtrlReg = MmioRead32(MCI_POWER_CONTROL_REG);
|
||||
PwrCtrlReg = MmioRead32 (MCI_POWER_CONTROL_REG);
|
||||
//Disable Open Drain output
|
||||
PwrCtrlReg &=~(MCI_POWER_OPENDRAIN);
|
||||
MmioWrite32(MCI_POWER_CONTROL_REG,PwrCtrlReg);
|
||||
PwrCtrlReg &= ~ (MCI_POWER_OPENDRAIN);
|
||||
MmioWrite32 (MCI_POWER_CONTROL_REG, PwrCtrlReg);
|
||||
|
||||
// Set MMCI0 clock to 4MHz (24MHz may be possible with cache enabled)
|
||||
//
|
||||
|
|
@ -471,22 +476,22 @@ MciNotifyState (
|
|||
break;
|
||||
}
|
||||
case MmcTransferState:
|
||||
//MCI_TRACE("MciNotifyState(MmcTransferState)");
|
||||
//MCI_TRACE ("MciNotifyState(MmcTransferState)");
|
||||
break;
|
||||
case MmcSendingDataState:
|
||||
MCI_TRACE("MciNotifyState(MmcSendingDataState)");
|
||||
MCI_TRACE ("MciNotifyState(MmcSendingDataState)");
|
||||
break;
|
||||
case MmcReceiveDataState:
|
||||
MCI_TRACE("MciNotifyState(MmcReceiveDataState)");
|
||||
MCI_TRACE ("MciNotifyState(MmcReceiveDataState)");
|
||||
break;
|
||||
case MmcProgrammingState:
|
||||
MCI_TRACE("MciNotifyState(MmcProgrammingState)");
|
||||
MCI_TRACE ("MciNotifyState(MmcProgrammingState)");
|
||||
break;
|
||||
case MmcDisconnectState:
|
||||
MCI_TRACE("MciNotifyState(MmcDisconnectState)");
|
||||
MCI_TRACE ("MciNotifyState(MmcDisconnectState)");
|
||||
break;
|
||||
default:
|
||||
ASSERT(0);
|
||||
ASSERT (0);
|
||||
}
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
|
@ -501,8 +506,8 @@ MciBuildDevicePath (
|
|||
{
|
||||
EFI_DEVICE_PATH_PROTOCOL *NewDevicePathNode;
|
||||
|
||||
NewDevicePathNode = CreateDeviceNode(HARDWARE_DEVICE_PATH,HW_VENDOR_DP,sizeof(VENDOR_DEVICE_PATH));
|
||||
CopyGuid(&((VENDOR_DEVICE_PATH*)NewDevicePathNode)->Guid,&mPL180MciDevicePathGuid);
|
||||
NewDevicePathNode = CreateDeviceNode (HARDWARE_DEVICE_PATH, HW_VENDOR_DP, sizeof (VENDOR_DEVICE_PATH));
|
||||
CopyGuid (& ((VENDOR_DEVICE_PATH*)NewDevicePathNode)->Guid, &mPL180MciDevicePathGuid);
|
||||
|
||||
*DevicePath = NewDevicePathNode;
|
||||
return EFI_SUCCESS;
|
||||
|
|
@ -527,9 +532,11 @@ PL180MciDxeInitialize (
|
|||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
EFI_HANDLE Handle = NULL;
|
||||
EFI_HANDLE Handle;
|
||||
|
||||
MCI_TRACE("PL180MciDxeInitialize()");
|
||||
Handle = NULL;
|
||||
|
||||
MCI_TRACE ("PL180MciDxeInitialize()");
|
||||
|
||||
//Publish Component Name, BlockIO protocol interfaces
|
||||
Status = gBS->InstallMultipleProtocolInterfaces (
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/** @file
|
||||
Header for the MMC Host Protocol implementation for the ARM PrimeCell PL180.
|
||||
|
||||
Copyright (c) 2011, ARM Limited. All rights reserved.
|
||||
Copyright (c) 2011-2012, ARM Limited. All rights reserved.
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
|
|
@ -27,76 +27,108 @@
|
|||
#include <Library/TimerLib.h>
|
||||
#include <Library/PcdLib.h>
|
||||
|
||||
#define PL180_MCI_DXE_VERSION 0x10
|
||||
#define PL180_MCI_DXE_VERSION 0x10
|
||||
|
||||
#define MCI_SYSCTL FixedPcdGet32(PcdPL180MciBaseAddress)
|
||||
#define MCI_SYSCTL FixedPcdGet32 (PcdPL180MciBaseAddress)
|
||||
|
||||
#define MCI_POWER_CONTROL_REG (MCI_SYSCTL+0x000)
|
||||
#define MCI_CLOCK_CONTROL_REG (MCI_SYSCTL+0x004)
|
||||
#define MCI_ARGUMENT_REG (MCI_SYSCTL+0x008)
|
||||
#define MCI_COMMAND_REG (MCI_SYSCTL+0x00C)
|
||||
#define MCI_RESPCMD_REG (MCI_SYSCTL+0x010)
|
||||
#define MCI_RESPONSE3_REG (MCI_SYSCTL+0x014)
|
||||
#define MCI_RESPONSE2_REG (MCI_SYSCTL+0x018)
|
||||
#define MCI_RESPONSE1_REG (MCI_SYSCTL+0x01C)
|
||||
#define MCI_RESPONSE0_REG (MCI_SYSCTL+0x020)
|
||||
#define MCI_DATA_TIMER_REG (MCI_SYSCTL+0x024)
|
||||
#define MCI_DATA_LENGTH_REG (MCI_SYSCTL+0x028)
|
||||
#define MCI_DATA_CTL_REG (MCI_SYSCTL+0x02C)
|
||||
#define MCI_DATA_COUNTER (MCI_SYSCTL+0x030)
|
||||
#define MCI_STATUS_REG (MCI_SYSCTL+0x034)
|
||||
#define MCI_CLEAR_STATUS_REG (MCI_SYSCTL+0x038)
|
||||
#define MCI_INT0_MASK_REG (MCI_SYSCTL+0x03C)
|
||||
#define MCI_INT1_MASK_REG (MCI_SYSCTL+0x040)
|
||||
#define MCI_FIFOCOUNT_REG (MCI_SYSCTL+0x048)
|
||||
#define MCI_FIFO_REG (MCI_SYSCTL+0x080)
|
||||
#define MCI_POWER_CONTROL_REG (MCI_SYSCTL + 0x000)
|
||||
#define MCI_CLOCK_CONTROL_REG (MCI_SYSCTL + 0x004)
|
||||
#define MCI_ARGUMENT_REG (MCI_SYSCTL + 0x008)
|
||||
#define MCI_COMMAND_REG (MCI_SYSCTL + 0x00C)
|
||||
#define MCI_RESPCMD_REG (MCI_SYSCTL + 0x010)
|
||||
#define MCI_RESPONSE3_REG (MCI_SYSCTL + 0x014)
|
||||
#define MCI_RESPONSE2_REG (MCI_SYSCTL + 0x018)
|
||||
#define MCI_RESPONSE1_REG (MCI_SYSCTL + 0x01C)
|
||||
#define MCI_RESPONSE0_REG (MCI_SYSCTL + 0x020)
|
||||
#define MCI_DATA_TIMER_REG (MCI_SYSCTL + 0x024)
|
||||
#define MCI_DATA_LENGTH_REG (MCI_SYSCTL + 0x028)
|
||||
#define MCI_DATA_CTL_REG (MCI_SYSCTL + 0x02C)
|
||||
#define MCI_DATA_COUNTER (MCI_SYSCTL + 0x030)
|
||||
#define MCI_STATUS_REG (MCI_SYSCTL + 0x034)
|
||||
#define MCI_CLEAR_STATUS_REG (MCI_SYSCTL + 0x038)
|
||||
#define MCI_INT0_MASK_REG (MCI_SYSCTL + 0x03C)
|
||||
#define MCI_INT1_MASK_REG (MCI_SYSCTL + 0x040)
|
||||
#define MCI_SELECT_REG (MCI_SYSCTL + 0x044)
|
||||
#define MCI_FIFOCOUNT_REG (MCI_SYSCTL + 0x048)
|
||||
#define MCI_FIFO_REG (MCI_SYSCTL + 0x080)
|
||||
|
||||
#define MCI_POWER_UP 0x2
|
||||
#define MCI_POWER_ON 0x3
|
||||
#define MCI_POWER_OPENDRAIN (1 << 6)
|
||||
#define MCI_POWER_ROD (1 << 7)
|
||||
#define MCI_POWER_OFF 0
|
||||
#define MCI_POWER_UP BIT1
|
||||
#define MCI_POWER_ON (BIT1 | BIT0)
|
||||
#define MCI_POWER_OPENDRAIN BIT6
|
||||
#define MCI_POWER_ROD BIT7
|
||||
|
||||
#define MCI_CLOCK_ENABLE 0x100
|
||||
#define MCI_CLOCK_POWERSAVE 0x200
|
||||
#define MCI_CLOCK_BYPASS 0x400
|
||||
#define MCI_CLOCK_ENABLE BIT8
|
||||
#define MCI_CLOCK_POWERSAVE BIT9
|
||||
#define MCI_CLOCK_BYPASS BIT10
|
||||
#define MCI_CLOCK_WIDEBUS BIT11
|
||||
|
||||
#define MCI_STATUS_CMD_CMDCRCFAIL 0x1
|
||||
#define MCI_STATUS_CMD_DATACRCFAIL 0x2
|
||||
#define MCI_STATUS_CMD_CMDTIMEOUT 0x4
|
||||
#define MCI_STATUS_CMD_DATATIMEOUT 0x8
|
||||
#define MCI_STATUS_CMD_TX_UNDERRUN 0x10
|
||||
#define MCI_STATUS_CMD_RXOVERRUN 0x20
|
||||
#define MCI_STATUS_CMD_RESPEND 0x40
|
||||
#define MCI_STATUS_CMD_SENT 0x80
|
||||
#define MCI_STATUS_CMD_TXDONE (MCI_STATUS_CMD_DATAEND | MCI_STATUS_CMD_DATABLOCKEND)
|
||||
#define MCI_STATUS_CMD_DATAEND 0x000100 // Command Status - Data end
|
||||
#define MCI_STATUS_CMD_START_BIT_ERROR 0x000200
|
||||
#define MCI_STATUS_CMD_DATABLOCKEND 0x000400 // Command Status - Data end
|
||||
#define MCI_STATUS_CMD_ACTIVE 0x800
|
||||
#define MCI_STATUS_CMD_RXACTIVE (1 << 13)
|
||||
#define MCI_STATUS_CMD_RXFIFOHALFFULL 0x008000
|
||||
#define MCI_STATUS_CMD_RXFIFOEMPTY 0x080000
|
||||
#define MCI_STATUS_CMD_RXDATAAVAILBL (1 << 21)
|
||||
#define MCI_STATUS_CMD_TXACTIVE (1 << 12)
|
||||
#define MCI_STATUS_CMD_TXFIFOFULL (1 << 16)
|
||||
#define MCI_STATUS_CMD_TXFIFOHALFEMPTY (1 << 14)
|
||||
#define MCI_STATUS_CMD_TXFIFOEMPTY (1 << 18)
|
||||
#define MCI_STATUS_CMD_TXDATAAVAILBL (1 << 20)
|
||||
#define MCI_STATUS_CMD_CMDCRCFAIL BIT0
|
||||
#define MCI_STATUS_CMD_DATACRCFAIL BIT1
|
||||
#define MCI_STATUS_CMD_CMDTIMEOUT BIT2
|
||||
#define MCI_STATUS_CMD_DATATIMEOUT BIT3
|
||||
#define MCI_STATUS_CMD_TX_UNDERRUN BIT4
|
||||
#define MCI_STATUS_CMD_RXOVERRUN BIT5
|
||||
#define MCI_STATUS_CMD_RESPEND BIT6
|
||||
#define MCI_STATUS_CMD_SENT BIT7
|
||||
#define MCI_STATUS_CMD_DATAEND BIT8
|
||||
#define MCI_STATUS_CMD_START_BIT_ERROR BIT9
|
||||
#define MCI_STATUS_CMD_DATABLOCKEND BIT10
|
||||
#define MCI_STATUS_CMD_ACTIVE BIT11
|
||||
#define MCI_STATUS_CMD_TXACTIVE BIT12
|
||||
#define MCI_STATUS_CMD_RXACTIVE BIT13
|
||||
#define MCI_STATUS_CMD_TXFIFOHALFEMPTY BIT14
|
||||
#define MCI_STATUS_CMD_RXFIFOHALFFULL BIT15
|
||||
#define MCI_STATUS_CMD_TXFIFOFULL BIT16
|
||||
#define MCI_STATUS_CMD_RXFIFOFULL BIT17
|
||||
#define MCI_STATUS_CMD_TXFIFOEMPTY BIT18
|
||||
#define MCI_STATUS_CMD_RXFIFOEMPTY BIT19
|
||||
#define MCI_STATUS_CMD_TXDATAAVAILBL BIT20
|
||||
#define MCI_STATUS_CMD_RXDATAAVAILBL BIT21
|
||||
|
||||
#define MCI_DATACTL_ENABLE 1
|
||||
#define MCI_STATUS_TXDONE (MCI_STATUS_CMD_DATAEND | MCI_STATUS_CMD_DATABLOCKEND)
|
||||
#define MCI_STATUS_RXDONE (MCI_STATUS_CMD_DATAEND | MCI_STATUS_CMD_DATABLOCKEND)
|
||||
#define MCI_STATUS_READ_ERROR ( MCI_STATUS_CMD_DATACRCFAIL \
|
||||
| MCI_STATUS_CMD_DATATIMEOUT \
|
||||
| MCI_STATUS_CMD_RXOVERRUN \
|
||||
| MCI_STATUS_CMD_START_BIT_ERROR )
|
||||
#define MCI_STATUS_WRITE_ERROR ( MCI_STATUS_CMD_DATACRCFAIL \
|
||||
| MCI_STATUS_CMD_DATATIMEOUT \
|
||||
| MCI_STATUS_CMD_TX_UNDERRUN )
|
||||
#define MCI_STATUS_CMD_ERROR ( MCI_STATUS_CMD_CMDCRCFAIL \
|
||||
| MCI_STATUS_CMD_CMDTIMEOUT \
|
||||
| MCI_STATUS_CMD_START_BIT_ERROR )
|
||||
|
||||
#define MCI_CLR_CMD_STATUS ( MCI_STATUS_CMD_RESPEND \
|
||||
| MCI_STATUS_CMD_SENT \
|
||||
| MCI_STATUS_CMD_ERROR )
|
||||
|
||||
#define MCI_CLR_READ_STATUS ( MCI_STATUS_RXDONE \
|
||||
| MCI_STATUS_READ_ERROR )
|
||||
|
||||
#define MCI_CLR_WRITE_STATUS ( MCI_STATUS_TXDONE \
|
||||
| MCI_STATUS_WRITE_ERROR )
|
||||
|
||||
#define MCI_CLR_ALL_STATUS (BIT11 - 1)
|
||||
|
||||
#define MCI_DATACTL_DISABLE_MASK 0xFE
|
||||
#define MCI_DATACTL_ENABLE BIT0
|
||||
#define MCI_DATACTL_CONT_TO_CARD 0
|
||||
#define MCI_DATACTL_CARD_TO_CONT 2
|
||||
#define MCI_DATACTL_CARD_TO_CONT BIT1
|
||||
#define MCI_DATACTL_BLOCK_TRANS 0
|
||||
#define MCI_DATACTL_STREAM_TRANS 4
|
||||
#define MCI_DATACTL_DMA_ENABLE (1 << 3)
|
||||
#define MCI_DATACTL_STREAM_TRANS BIT2
|
||||
#define MCI_DATACTL_DMA_DISABLED 0
|
||||
#define MCI_DATACTL_DMA_ENABLE BIT3
|
||||
|
||||
#define INDX_MASK 0x3F
|
||||
|
||||
#define MCI_CPSM_ENABLED (1 << 10)
|
||||
#define MCI_CPSM_WAIT_RESPONSE (1 << 6)
|
||||
#define MCI_CPSM_LONG_RESPONSE (1 << 7)
|
||||
#define MCI_CPSM_WAIT_RESPONSE BIT6
|
||||
#define MCI_CPSM_LONG_RESPONSE BIT7
|
||||
#define MCI_CPSM_LONG_INTERRUPT BIT8
|
||||
#define MCI_CPSM_LONG_PENDING BIT9
|
||||
#define MCI_CPSM_ENABLE BIT10
|
||||
|
||||
#define MCI_TRACE(txt) DEBUG((EFI_D_BLKIO, "ARM_MCI: " txt "\n"))
|
||||
#define MCI_TRACE(txt) DEBUG ((EFI_D_BLKIO, "ARM_MCI: " txt "\n"))
|
||||
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
|
|
|
|||
Loading…
Reference in New Issue