tyler.durden/audk
1
0
Fork 0
mirror of https://github.com/acidanthera/audk.git synced 2025-07-03 20:04:23 +02:00
Code Issues Packages Projects Releases Wiki Activity

ArmPlatformPkg/PL180MciDxe: Fixed coding style

Browse Source 
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13586 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin 2012-08-02 11:20:37 +00:00
parent 260675b073
commit 93b429fc21
2 changed files with 202 additions and 163 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

41
ArmPlatformPkg/Drivers/PL180MciDxe/PL180Mci.c
View File

@ -1,7 +1,7 @@
/** @file /** @file
This file implement the MMC Host Protocol for the ARM PrimeCell PL180. This file implement the MMC Host Protocol for the ARM PrimeCell PL180.
Copyright (c) 2011, ARM Limited. All rights reserved. Copyright (c) 2011-2012, ARM Limited. All rights reserved.
This program and the accompanying materials This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
@ -27,12 +27,15 @@ EFI_MMC_HOST_PROTOCOL *gpMmcHost;
#define MMCI0_POW2_BLOCKLEN 9 #define MMCI0_POW2_BLOCKLEN 9
#define MMCI0_TIMEOUT 1000 #define MMCI0_TIMEOUT 1000
#define SYS_MCI_CARDIN BIT0
#define SYS_MCI_WPROT BIT1
BOOLEAN BOOLEAN
MciIsPowerOn ( MciIsPowerOn (
VOID VOID
) )
{ {
return ((MmioRead32(MCI_POWER_CONTROL_REG) & 0x3) == MCI_POWER_ON); return ((MmioRead32 (MCI_POWER_CONTROL_REG) & MCI_POWER_ON) == MCI_POWER_ON);
} }
EFI_STATUS EFI_STATUS
@ -49,7 +52,7 @@ MciIsCardPresent (
IN EFI_MMC_HOST_PROTOCOL *This IN EFI_MMC_HOST_PROTOCOL *This
) )
{ {
return (MmioRead32(FixedPcdGet32(PcdPL180SysMciRegAddress)) & 1); return (MmioRead32 (FixedPcdGet32 (PcdPL180SysMciRegAddress)) & SYS_MCI_CARDIN);
} }
BOOLEAN BOOLEAN
@ -57,7 +60,7 @@ MciIsReadOnly (
IN EFI_MMC_HOST_PROTOCOL *This IN EFI_MMC_HOST_PROTOCOL *This
) )
{ {
return (MmioRead32(FixedPcdGet32(PcdPL180SysMciRegAddress)) & 2); return (MmioRead32 (FixedPcdGet32 (PcdPL180SysMciRegAddress)) & SYS_MCI_WPROT);
} }
#if 0 #if 0
@ -96,7 +99,7 @@ MciPrepareDataPath (
MmioWrite32 (MCI_DATA_LENGTH_REG, MMCI0_BLOCKLEN); MmioWrite32 (MCI_DATA_LENGTH_REG, MMCI0_BLOCKLEN);
#ifndef USE_STREAM #ifndef USE_STREAM
//Note: we are using a hardcoded BlockLen (=512). If we decide to use a variable size, we could //Note: we are using a hardcoded BlockLen (==512). If we decide to use a variable size, we could
// compute the pow2 of BlockLen with the above function GetPow2BlockLen () // compute the pow2 of BlockLen with the above function GetPow2BlockLen ()
MmioWrite32 (MCI_DATA_CTL_REG, MCI_DATACTL_ENABLE | MCI_DATACTL_DMA_ENABLE | TransferDirection | (MMCI0_POW2_BLOCKLEN << 4)); MmioWrite32 (MCI_DATA_CTL_REG, MCI_DATACTL_ENABLE | MCI_DATACTL_DMA_ENABLE | TransferDirection | (MMCI0_POW2_BLOCKLEN << 4));
#else #else
@ -125,7 +128,7 @@ MciSendCommand (
} }
// Create Command for PL180 // Create Command for PL180
Cmd = (MMC_GET_INDX(MmcCmd) & INDX_MASK) | MCI_CPSM_ENABLED; Cmd = (MMC_GET_INDX (MmcCmd) & INDX_MASK) | MCI_CPSM_ENABLE;
if (MmcCmd & MMC_CMD_WAIT_RESPONSE) { if (MmcCmd & MMC_CMD_WAIT_RESPONSE) {
Cmd |= MCI_CPSM_WAIT_RESPONSE; Cmd |= MCI_CPSM_WAIT_RESPONSE;
} }
@ -135,7 +138,7 @@ MciSendCommand (
} }
// Clear Status register static flags // Clear Status register static flags
MmioWrite32(MCI_CLEAR_STATUS_REG,0x7FF); MmioWrite32 (MCI_CLEAR_STATUS_REG, MCI_CLR_ALL_STATUS);
// Write to command argument register // Write to command argument register
MmioWrite32 (MCI_ARGUMENT_REG, Argument); MmioWrite32 (MCI_ARGUMENT_REG, Argument);
@ -193,7 +196,7 @@ MciSendCommand (
Exit: Exit:
// Disable Command Path // Disable Command Path
CmdCtrlReg = MmioRead32 (MCI_COMMAND_REG); CmdCtrlReg = MmioRead32 (MCI_COMMAND_REG);
MmioWrite32(MCI_COMMAND_REG, (CmdCtrlReg & ~MCI_CPSM_ENABLED)); MmioWrite32 (MCI_COMMAND_REG, (CmdCtrlReg & ~MCI_CPSM_ENABLE));
return RetVal; return RetVal;
} }
@ -208,9 +211,11 @@ MciReceiveResponse (
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
if ((Type == MMC_RESPONSE_TYPE_R1) || (Type == MMC_RESPONSE_TYPE_R1b) || if ( (Type == MMC_RESPONSE_TYPE_R1)
(Type == MMC_RESPONSE_TYPE_R3) || (Type == MMC_RESPONSE_TYPE_R6) || || (Type == MMC_RESPONSE_TYPE_R1b)
(Type == MMC_RESPONSE_TYPE_R7)) || (Type == MMC_RESPONSE_TYPE_R3)
|| (Type == MMC_RESPONSE_TYPE_R6)
|| (Type == MMC_RESPONSE_TYPE_R7))
{ {
Buffer[0] = MmioRead32 (MCI_RESPONSE3_REG); Buffer[0] = MmioRead32 (MCI_RESPONSE3_REG);
} else if (Type == MMC_RESPONSE_TYPE_R2) { } else if (Type == MMC_RESPONSE_TYPE_R2) {
@ -290,11 +295,11 @@ MciReadBlockData (
} while ((Loop < Finish)); } while ((Loop < Finish));
// Clear Status flags // Clear Status flags
MmioWrite32(MCI_CLEAR_STATUS_REG, 0x7FF); MmioWrite32 (MCI_CLEAR_STATUS_REG, MCI_CLR_ALL_STATUS);
//Disable Data path //Disable Data path
DataCtrlReg = MmioRead32 (MCI_DATA_CTL_REG); DataCtrlReg = MmioRead32 (MCI_DATA_CTL_REG);
MmioWrite32(MCI_DATA_CTL_REG, (DataCtrlReg & 0xFE)); MmioWrite32 (MCI_DATA_CTL_REG, (DataCtrlReg & MCI_DATACTL_DISABLE_MASK));
return RetVal; return RetVal;
} }
@ -369,7 +374,7 @@ MciWriteBlockData (
Status = MmioRead32 (MCI_STATUS_REG); Status = MmioRead32 (MCI_STATUS_REG);
#ifndef USE_STREAM #ifndef USE_STREAM
// Single block // Single block
while (((Status & MCI_STATUS_CMD_TXDONE) != MCI_STATUS_CMD_TXDONE) && Timer) { while (((Status & MCI_STATUS_TXDONE) != MCI_STATUS_TXDONE) && Timer) {
#else #else
// Stream // Stream
while (((Status & MCI_STATUS_CMD_DATAEND) != MCI_STATUS_CMD_DATAEND) && Timer) { while (((Status & MCI_STATUS_CMD_DATAEND) != MCI_STATUS_CMD_DATAEND) && Timer) {
@ -386,7 +391,7 @@ MciWriteBlockData (
} }
// Clear Status flags // Clear Status flags
MmioWrite32(MCI_CLEAR_STATUS_REG, 0x7FF); MmioWrite32 (MCI_CLEAR_STATUS_REG, MCI_CLR_ALL_STATUS);
if (Timer == 0) { if (Timer == 0) {
RetVal = EFI_TIMEOUT; RetVal = EFI_TIMEOUT;
} }
@ -394,7 +399,7 @@ MciWriteBlockData (
Exit: Exit:
// Disable Data path // Disable Data path
DataCtrlReg = MmioRead32 (MCI_DATA_CTL_REG); DataCtrlReg = MmioRead32 (MCI_DATA_CTL_REG);
MmioWrite32(MCI_DATA_CTL_REG, (DataCtrlReg & 0xFE)); MmioWrite32 (MCI_DATA_CTL_REG, (DataCtrlReg & MCI_DATACTL_DISABLE_MASK));
return RetVal; return RetVal;
} }
@ -527,7 +532,9 @@ PL180MciDxeInitialize (
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
EFI_HANDLE Handle = NULL; EFI_HANDLE Handle;
Handle = NULL;
MCI_TRACE ("PL180MciDxeInitialize()"); MCI_TRACE ("PL180MciDxeInitialize()");

106
ArmPlatformPkg/Drivers/PL180MciDxe/PL180Mci.h
View File

@ -1,7 +1,7 @@
/** @file /** @file
Header for the MMC Host Protocol implementation for the ARM PrimeCell PL180. Header for the MMC Host Protocol implementation for the ARM PrimeCell PL180.
Copyright (c) 2011, ARM Limited. All rights reserved. Copyright (c) 2011-2012, ARM Limited. All rights reserved.
This program and the accompanying materials This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
@ -48,53 +48,85 @@
#define MCI_CLEAR_STATUS_REG (MCI_SYSCTL + 0x038) #define MCI_CLEAR_STATUS_REG (MCI_SYSCTL + 0x038)
#define MCI_INT0_MASK_REG (MCI_SYSCTL + 0x03C) #define MCI_INT0_MASK_REG (MCI_SYSCTL + 0x03C)
#define MCI_INT1_MASK_REG (MCI_SYSCTL + 0x040) #define MCI_INT1_MASK_REG (MCI_SYSCTL + 0x040)
#define MCI_SELECT_REG (MCI_SYSCTL + 0x044)
#define MCI_FIFOCOUNT_REG (MCI_SYSCTL + 0x048) #define MCI_FIFOCOUNT_REG (MCI_SYSCTL + 0x048)
#define MCI_FIFO_REG (MCI_SYSCTL + 0x080) #define MCI_FIFO_REG (MCI_SYSCTL + 0x080)
#define MCI_POWER_UP 0x2 #define MCI_POWER_OFF 0
#define MCI_POWER_ON 0x3 #define MCI_POWER_UP BIT1
#define MCI_POWER_OPENDRAIN (1 << 6) #define MCI_POWER_ON (BIT1 | BIT0)
#define MCI_POWER_ROD (1 << 7) #define MCI_POWER_OPENDRAIN BIT6
#define MCI_POWER_ROD BIT7
#define MCI_CLOCK_ENABLE 0x100 #define MCI_CLOCK_ENABLE BIT8
#define MCI_CLOCK_POWERSAVE 0x200 #define MCI_CLOCK_POWERSAVE BIT9
#define MCI_CLOCK_BYPASS 0x400 #define MCI_CLOCK_BYPASS BIT10
#define MCI_CLOCK_WIDEBUS BIT11
#define MCI_STATUS_CMD_CMDCRCFAIL 0x1 #define MCI_STATUS_CMD_CMDCRCFAIL BIT0
#define MCI_STATUS_CMD_DATACRCFAIL 0x2 #define MCI_STATUS_CMD_DATACRCFAIL BIT1
#define MCI_STATUS_CMD_CMDTIMEOUT 0x4 #define MCI_STATUS_CMD_CMDTIMEOUT BIT2
#define MCI_STATUS_CMD_DATATIMEOUT 0x8 #define MCI_STATUS_CMD_DATATIMEOUT BIT3
#define MCI_STATUS_CMD_TX_UNDERRUN 0x10 #define MCI_STATUS_CMD_TX_UNDERRUN BIT4
#define MCI_STATUS_CMD_RXOVERRUN 0x20 #define MCI_STATUS_CMD_RXOVERRUN BIT5
#define MCI_STATUS_CMD_RESPEND 0x40 #define MCI_STATUS_CMD_RESPEND BIT6
#define MCI_STATUS_CMD_SENT 0x80 #define MCI_STATUS_CMD_SENT BIT7
#define MCI_STATUS_CMD_TXDONE (MCI_STATUS_CMD_DATAEND | MCI_STATUS_CMD_DATABLOCKEND) #define MCI_STATUS_CMD_DATAEND BIT8
#define MCI_STATUS_CMD_DATAEND 0x000100 // Command Status - Data end #define MCI_STATUS_CMD_START_BIT_ERROR BIT9
#define MCI_STATUS_CMD_START_BIT_ERROR 0x000200 #define MCI_STATUS_CMD_DATABLOCKEND BIT10
#define MCI_STATUS_CMD_DATABLOCKEND 0x000400 // Command Status - Data end #define MCI_STATUS_CMD_ACTIVE BIT11
#define MCI_STATUS_CMD_ACTIVE 0x800 #define MCI_STATUS_CMD_TXACTIVE BIT12
#define MCI_STATUS_CMD_RXACTIVE (1 << 13) #define MCI_STATUS_CMD_RXACTIVE BIT13
#define MCI_STATUS_CMD_RXFIFOHALFFULL 0x008000 #define MCI_STATUS_CMD_TXFIFOHALFEMPTY BIT14
#define MCI_STATUS_CMD_RXFIFOEMPTY 0x080000 #define MCI_STATUS_CMD_RXFIFOHALFFULL BIT15
#define MCI_STATUS_CMD_RXDATAAVAILBL (1 << 21) #define MCI_STATUS_CMD_TXFIFOFULL BIT16
#define MCI_STATUS_CMD_TXACTIVE (1 << 12) #define MCI_STATUS_CMD_RXFIFOFULL BIT17
#define MCI_STATUS_CMD_TXFIFOFULL (1 << 16) #define MCI_STATUS_CMD_TXFIFOEMPTY BIT18
#define MCI_STATUS_CMD_TXFIFOHALFEMPTY (1 << 14) #define MCI_STATUS_CMD_RXFIFOEMPTY BIT19
#define MCI_STATUS_CMD_TXFIFOEMPTY (1 << 18) #define MCI_STATUS_CMD_TXDATAAVAILBL BIT20
#define MCI_STATUS_CMD_TXDATAAVAILBL (1 << 20) #define MCI_STATUS_CMD_RXDATAAVAILBL BIT21
#define MCI_DATACTL_ENABLE 1 #define MCI_STATUS_TXDONE (MCI_STATUS_CMD_DATAEND | MCI_STATUS_CMD_DATABLOCKEND)
#define MCI_STATUS_RXDONE (MCI_STATUS_CMD_DATAEND | MCI_STATUS_CMD_DATABLOCKEND)
#define MCI_STATUS_READ_ERROR ( MCI_STATUS_CMD_DATACRCFAIL \
| MCI_STATUS_CMD_DATATIMEOUT \
| MCI_STATUS_CMD_RXOVERRUN \
| MCI_STATUS_CMD_START_BIT_ERROR )
#define MCI_STATUS_WRITE_ERROR ( MCI_STATUS_CMD_DATACRCFAIL \
| MCI_STATUS_CMD_DATATIMEOUT \
| MCI_STATUS_CMD_TX_UNDERRUN )
#define MCI_STATUS_CMD_ERROR ( MCI_STATUS_CMD_CMDCRCFAIL \
| MCI_STATUS_CMD_CMDTIMEOUT \
| MCI_STATUS_CMD_START_BIT_ERROR )
#define MCI_CLR_CMD_STATUS ( MCI_STATUS_CMD_RESPEND \
| MCI_STATUS_CMD_SENT \
| MCI_STATUS_CMD_ERROR )
#define MCI_CLR_READ_STATUS ( MCI_STATUS_RXDONE \
| MCI_STATUS_READ_ERROR )
#define MCI_CLR_WRITE_STATUS ( MCI_STATUS_TXDONE \
| MCI_STATUS_WRITE_ERROR )
#define MCI_CLR_ALL_STATUS (BIT11 - 1)
#define MCI_DATACTL_DISABLE_MASK 0xFE
#define MCI_DATACTL_ENABLE BIT0
#define MCI_DATACTL_CONT_TO_CARD 0 #define MCI_DATACTL_CONT_TO_CARD 0
#define MCI_DATACTL_CARD_TO_CONT 2 #define MCI_DATACTL_CARD_TO_CONT BIT1
#define MCI_DATACTL_BLOCK_TRANS 0 #define MCI_DATACTL_BLOCK_TRANS 0
#define MCI_DATACTL_STREAM_TRANS 4 #define MCI_DATACTL_STREAM_TRANS BIT2
#define MCI_DATACTL_DMA_ENABLE (1 << 3) #define MCI_DATACTL_DMA_DISABLED 0
#define MCI_DATACTL_DMA_ENABLE BIT3
#define INDX_MASK 0x3F #define INDX_MASK 0x3F
#define MCI_CPSM_ENABLED (1 << 10) #define MCI_CPSM_WAIT_RESPONSE BIT6
#define MCI_CPSM_WAIT_RESPONSE (1 << 6) #define MCI_CPSM_LONG_RESPONSE BIT7
#define MCI_CPSM_LONG_RESPONSE (1 << 7) #define MCI_CPSM_LONG_INTERRUPT BIT8
#define MCI_CPSM_LONG_PENDING BIT9
#define MCI_CPSM_ENABLE BIT10
#define MCI_TRACE(txt) DEBUG ((EFI_D_BLKIO, "ARM_MCI: " txt "\n")) #define MCI_TRACE(txt) DEBUG ((EFI_D_BLKIO, "ARM_MCI: " txt "\n"))