mirror of https://github.com/acidanthera/audk.git
This revision can only work with Intel(c) UDK Debugger Tool version 1.2 or greater. Detailed change log is as below:
1. Define the transfer protocol revision mechanism. Increase the revision number to 0.2 and inform user to use the latest one when the HOST software is too old. New HOST software will implement logic to handle all other revision mismatch cases. 2. Define new debug message packet to print the debug agent trace information by debug port channel. 3. Add check sum mechanism in the communication protocol between TARGET/HOST. 4. Introduced one "try" mechanism to avoid Debug Agent crashed by some invalid HOST command. 5. Enable the late-attach feature: Change the break in from "!" to "\xFC". Add a new short symbol "\xFA" for attach and a new debug command for detach. 6. Support Terminal work on debug port by install EFI Serial IO protocol upon Debug Communication Library. 7. Enable CPUID feature. 8. Enable the hardware data breakpoint. 9. add handshake to improve usb debug cable identify stability issue. 10.Refine all the communication protocol packet to improve extensibility and debugging performance. a. Use 64bit for IO port address. b. Add additional Width field to READ_MEMORY/WRITE_MEMORY. c. Add SEARCH_SIGNATURE support to speed the symbol finding for late attach. d. Remove READ_GROUP register. e. Add READ_ALL_REGISTERS support (WinDbg always requests to read all registers). 11.Move AcquireDebugPortControl () in advance to fix resource collision on IpiSentByApFlag. 12.Fix IO break point does not work issue in PEI phase. 13.Avoid BSP/APs collision when they met break point at the same time. 14.Solve a bug of calculating debug handle in sec phase. 15.Use mailbox content at Dxe phase but not clear it and reinitialize again. 16.Fix FP/MMX/XMM/IO/MSR access issue in both Gdb and WinDbg. Signed-off-by: Jeff Fan <jeff.fan@intel.com> Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Signed-off-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13437 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
vanjeff
parent
44538ba5aa
commit
93c0bdec28
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@ -2,7 +2,7 @@
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IA32/x64 architecture specific defintions needed by debug transfer protocol.It is only
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intended to be used by Debug related module implementation.
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Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2010 - 2012, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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@ -19,161 +19,292 @@
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//
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// IA-32/x64 processor register index table
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//
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#define SOFT_DEBUGGER_REGISTER_DR0 0
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#define SOFT_DEBUGGER_REGISTER_DR1 1
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#define SOFT_DEBUGGER_REGISTER_DR2 2
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#define SOFT_DEBUGGER_REGISTER_DR3 3
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#define SOFT_DEBUGGER_REGISTER_DR6 4
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#define SOFT_DEBUGGER_REGISTER_DR7 5
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#define SOFT_DEBUGGER_REGISTER_EFLAGS 6
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#define SOFT_DEBUGGER_REGISTER_LDTR 7
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#define SOFT_DEBUGGER_REGISTER_TR 8
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#define SOFT_DEBUGGER_REGISTER_GDTR0 9 // the low 32bit of GDTR
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#define SOFT_DEBUGGER_REGISTER_GDTR1 10 // the high 32bit of GDTR
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#define SOFT_DEBUGGER_REGISTER_IDTR0 11 // the low 32bit of IDTR
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#define SOFT_DEBUGGER_REGISTER_IDTR1 12 // the high 32bot of IDTR
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#define SOFT_DEBUGGER_REGISTER_EIP 13
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#define SOFT_DEBUGGER_REGISTER_GS 14
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#define SOFT_DEBUGGER_REGISTER_FS 15
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#define SOFT_DEBUGGER_REGISTER_ES 16
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#define SOFT_DEBUGGER_REGISTER_DS 17
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#define SOFT_DEBUGGER_REGISTER_CS 18
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#define SOFT_DEBUGGER_REGISTER_SS 19
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#define SOFT_DEBUGGER_REGISTER_CR0 20
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#define SOFT_DEBUGGER_REGISTER_CR1 21
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#define SOFT_DEBUGGER_REGISTER_CR2 22
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#define SOFT_DEBUGGER_REGISTER_CR3 23
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#define SOFT_DEBUGGER_REGISTER_CR4 24
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#define SOFT_DEBUGGER_REGISTER_DR0 0x00
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#define SOFT_DEBUGGER_REGISTER_DR1 0x01
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#define SOFT_DEBUGGER_REGISTER_DR2 0x02
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#define SOFT_DEBUGGER_REGISTER_DR3 0x03
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#define SOFT_DEBUGGER_REGISTER_DR6 0x04
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#define SOFT_DEBUGGER_REGISTER_DR7 0x05
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#define SOFT_DEBUGGER_REGISTER_EFLAGS 0x06
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#define SOFT_DEBUGGER_REGISTER_LDTR 0x07
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#define SOFT_DEBUGGER_REGISTER_TR 0x08
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#define SOFT_DEBUGGER_REGISTER_GDTR0 0x09 // the low 32bit of GDTR
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#define SOFT_DEBUGGER_REGISTER_GDTR1 0x0A // the high 32bit of GDTR
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#define SOFT_DEBUGGER_REGISTER_IDTR0 0x0B // the low 32bit of IDTR
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#define SOFT_DEBUGGER_REGISTER_IDTR1 0x0C // the high 32bot of IDTR
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#define SOFT_DEBUGGER_REGISTER_EIP 0x0D
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#define SOFT_DEBUGGER_REGISTER_GS 0x0E
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#define SOFT_DEBUGGER_REGISTER_FS 0x0F
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#define SOFT_DEBUGGER_REGISTER_ES 0x10
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#define SOFT_DEBUGGER_REGISTER_DS 0x11
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#define SOFT_DEBUGGER_REGISTER_CS 0x12
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#define SOFT_DEBUGGER_REGISTER_SS 0x13
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#define SOFT_DEBUGGER_REGISTER_CR0 0x14
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#define SOFT_DEBUGGER_REGISTER_CR1 0x15
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#define SOFT_DEBUGGER_REGISTER_CR2 0x16
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#define SOFT_DEBUGGER_REGISTER_CR3 0x17
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#define SOFT_DEBUGGER_REGISTER_CR4 0x18
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#define SOFT_DEBUGGER_REGISTER_DI 25
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#define SOFT_DEBUGGER_REGISTER_SI 26
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#define SOFT_DEBUGGER_REGISTER_BP 27
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#define SOFT_DEBUGGER_REGISTER_SP 28
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#define SOFT_DEBUGGER_REGISTER_DX 29
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#define SOFT_DEBUGGER_REGISTER_CX 30
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#define SOFT_DEBUGGER_REGISTER_BX 31
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#define SOFT_DEBUGGER_REGISTER_AX 32
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#define SOFT_DEBUGGER_REGISTER_DI 0x19
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#define SOFT_DEBUGGER_REGISTER_SI 0x1A
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#define SOFT_DEBUGGER_REGISTER_BP 0x1B
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#define SOFT_DEBUGGER_REGISTER_SP 0x1C
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#define SOFT_DEBUGGER_REGISTER_DX 0x1D
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#define SOFT_DEBUGGER_REGISTER_CX 0x1E
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#define SOFT_DEBUGGER_REGISTER_BX 0x1F
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#define SOFT_DEBUGGER_REGISTER_AX 0x20
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//
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// This below registers are only available for x64 (not valid for Ia32 mode)
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//
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#define SOFT_DEBUGGER_REGISTER_CR8 33
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#define SOFT_DEBUGGER_REGISTER_R8 34
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#define SOFT_DEBUGGER_REGISTER_R9 35
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#define SOFT_DEBUGGER_REGISTER_R10 36
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#define SOFT_DEBUGGER_REGISTER_R11 37
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#define SOFT_DEBUGGER_REGISTER_R12 38
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#define SOFT_DEBUGGER_REGISTER_R13 39
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#define SOFT_DEBUGGER_REGISTER_R14 40
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#define SOFT_DEBUGGER_REGISTER_R15 41
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#define SOFT_DEBUGGER_REGISTER_MAX_COUNT_IA32 33
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#define SOFT_DEBUGGER_REGISTER_MAX_COUNT_X64 42
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#define SOFT_DEBUGGER_REGISTER_CR8 0x21
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#define SOFT_DEBUGGER_REGISTER_R8 0x22
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#define SOFT_DEBUGGER_REGISTER_R9 0x23
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#define SOFT_DEBUGGER_REGISTER_R10 0x24
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#define SOFT_DEBUGGER_REGISTER_R11 0x25
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#define SOFT_DEBUGGER_REGISTER_R12 0x26
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#define SOFT_DEBUGGER_REGISTER_R13 0x27
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#define SOFT_DEBUGGER_REGISTER_R14 0x28
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#define SOFT_DEBUGGER_REGISTER_R15 0x29
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//
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// This below registers are FP / MMX / XMM registers
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//
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#define SOFT_DEBUGGER_REGISTER_FP_BASE 50
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#define SOFT_DEBUGGER_REGISTER_FP_BASE 0x30
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#define SOFT_DEBUGGER_REGISTER_FP_FCW (SOFT_DEBUGGER_REGISTER_FP_BASE + 0)
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#define SOFT_DEBUGGER_REGISTER_FP_FSW (SOFT_DEBUGGER_REGISTER_FP_BASE + 1)
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#define SOFT_DEBUGGER_REGISTER_FP_FTW (SOFT_DEBUGGER_REGISTER_FP_BASE + 2)
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#define SOFT_DEBUGGER_REGISTER_FP_OPCODE (SOFT_DEBUGGER_REGISTER_FP_BASE + 3)
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#define SOFT_DEBUGGER_REGISTER_FP_EIP (SOFT_DEBUGGER_REGISTER_FP_BASE + 4)
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#define SOFT_DEBUGGER_REGISTER_FP_CS (SOFT_DEBUGGER_REGISTER_FP_BASE + 5)
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#define SOFT_DEBUGGER_REGISTER_FP_DATAOFFSET (SOFT_DEBUGGER_REGISTER_FP_BASE + 6)
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#define SOFT_DEBUGGER_REGISTER_FP_DS (SOFT_DEBUGGER_REGISTER_FP_BASE + 7)
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#define SOFT_DEBUGGER_REGISTER_FP_MXCSR (SOFT_DEBUGGER_REGISTER_FP_BASE + 8)
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#define SOFT_DEBUGGER_REGISTER_FP_MXCSR_MASK (SOFT_DEBUGGER_REGISTER_FP_BASE + 9)
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#define SOFT_DEBUGGER_REGISTER_ST0 (SOFT_DEBUGGER_REGISTER_FP_BASE + 10)
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#define SOFT_DEBUGGER_REGISTER_ST1 (SOFT_DEBUGGER_REGISTER_FP_BASE + 11)
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#define SOFT_DEBUGGER_REGISTER_ST2 (SOFT_DEBUGGER_REGISTER_FP_BASE + 12)
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#define SOFT_DEBUGGER_REGISTER_ST3 (SOFT_DEBUGGER_REGISTER_FP_BASE + 13)
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#define SOFT_DEBUGGER_REGISTER_ST4 (SOFT_DEBUGGER_REGISTER_FP_BASE + 14)
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#define SOFT_DEBUGGER_REGISTER_ST5 (SOFT_DEBUGGER_REGISTER_FP_BASE + 15)
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#define SOFT_DEBUGGER_REGISTER_ST6 (SOFT_DEBUGGER_REGISTER_FP_BASE + 16)
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#define SOFT_DEBUGGER_REGISTER_ST7 (SOFT_DEBUGGER_REGISTER_FP_BASE + 17)
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#define SOFT_DEBUGGER_REGISTER_XMM0 (SOFT_DEBUGGER_REGISTER_FP_BASE + 18)
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#define SOFT_DEBUGGER_REGISTER_XMM1 (SOFT_DEBUGGER_REGISTER_FP_BASE + 19)
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#define SOFT_DEBUGGER_REGISTER_XMM2 (SOFT_DEBUGGER_REGISTER_FP_BASE + 20)
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#define SOFT_DEBUGGER_REGISTER_XMM3 (SOFT_DEBUGGER_REGISTER_FP_BASE + 21)
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#define SOFT_DEBUGGER_REGISTER_XMM4 (SOFT_DEBUGGER_REGISTER_FP_BASE + 22)
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#define SOFT_DEBUGGER_REGISTER_XMM5 (SOFT_DEBUGGER_REGISTER_FP_BASE + 23)
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#define SOFT_DEBUGGER_REGISTER_XMM6 (SOFT_DEBUGGER_REGISTER_FP_BASE + 24)
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#define SOFT_DEBUGGER_REGISTER_XMM7 (SOFT_DEBUGGER_REGISTER_FP_BASE + 25)
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#define SOFT_DEBUGGER_REGISTER_XMM8 (SOFT_DEBUGGER_REGISTER_FP_BASE + 26)
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#define SOFT_DEBUGGER_REGISTER_XMM9 (SOFT_DEBUGGER_REGISTER_FP_BASE + 27)
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#define SOFT_DEBUGGER_REGISTER_XMM10 (SOFT_DEBUGGER_REGISTER_FP_BASE + 28)
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#define SOFT_DEBUGGER_REGISTER_XMM11 (SOFT_DEBUGGER_REGISTER_FP_BASE + 29)
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#define SOFT_DEBUGGER_REGISTER_XMM12 (SOFT_DEBUGGER_REGISTER_FP_BASE + 30)
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#define SOFT_DEBUGGER_REGISTER_XMM13 (SOFT_DEBUGGER_REGISTER_FP_BASE + 31)
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#define SOFT_DEBUGGER_REGISTER_XMM14 (SOFT_DEBUGGER_REGISTER_FP_BASE + 32)
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#define SOFT_DEBUGGER_REGISTER_XMM15 (SOFT_DEBUGGER_REGISTER_FP_BASE + 33)
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#define SOFT_DEBUGGER_REGISTER_MM0 (SOFT_DEBUGGER_REGISTER_FP_BASE + 34)
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#define SOFT_DEBUGGER_REGISTER_MM1 (SOFT_DEBUGGER_REGISTER_FP_BASE + 35)
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#define SOFT_DEBUGGER_REGISTER_MM2 (SOFT_DEBUGGER_REGISTER_FP_BASE + 36)
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#define SOFT_DEBUGGER_REGISTER_MM3 (SOFT_DEBUGGER_REGISTER_FP_BASE + 37)
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#define SOFT_DEBUGGER_REGISTER_MM4 (SOFT_DEBUGGER_REGISTER_FP_BASE + 38)
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#define SOFT_DEBUGGER_REGISTER_MM5 (SOFT_DEBUGGER_REGISTER_FP_BASE + 39)
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#define SOFT_DEBUGGER_REGISTER_MM6 (SOFT_DEBUGGER_REGISTER_FP_BASE + 40)
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#define SOFT_DEBUGGER_REGISTER_MM7 (SOFT_DEBUGGER_REGISTER_FP_BASE + 41)
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#define SOFT_DEBUGGER_REGISTER_FP_FCW (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x00)
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#define SOFT_DEBUGGER_REGISTER_FP_FSW (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x01)
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#define SOFT_DEBUGGER_REGISTER_FP_FTW (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x02)
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#define SOFT_DEBUGGER_REGISTER_FP_OPCODE (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x03)
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#define SOFT_DEBUGGER_REGISTER_FP_EIP (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x04)
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#define SOFT_DEBUGGER_REGISTER_FP_CS (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x05)
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#define SOFT_DEBUGGER_REGISTER_FP_DATAOFFSET (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x06)
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#define SOFT_DEBUGGER_REGISTER_FP_DS (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x07)
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#define SOFT_DEBUGGER_REGISTER_FP_MXCSR (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x08)
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#define SOFT_DEBUGGER_REGISTER_FP_MXCSR_MASK (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x09)
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#define SOFT_DEBUGGER_REGISTER_ST0 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x0A)
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#define SOFT_DEBUGGER_REGISTER_ST1 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x0B)
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#define SOFT_DEBUGGER_REGISTER_ST2 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x0C)
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#define SOFT_DEBUGGER_REGISTER_ST3 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x0D)
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#define SOFT_DEBUGGER_REGISTER_ST4 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x0E)
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#define SOFT_DEBUGGER_REGISTER_ST5 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x0F)
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#define SOFT_DEBUGGER_REGISTER_ST6 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x10)
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#define SOFT_DEBUGGER_REGISTER_ST7 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x11)
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#define SOFT_DEBUGGER_REGISTER_XMM0 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x12)
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#define SOFT_DEBUGGER_REGISTER_XMM1 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x13)
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#define SOFT_DEBUGGER_REGISTER_XMM2 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x14)
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#define SOFT_DEBUGGER_REGISTER_XMM3 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x15)
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#define SOFT_DEBUGGER_REGISTER_XMM4 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x16)
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#define SOFT_DEBUGGER_REGISTER_XMM5 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x17)
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#define SOFT_DEBUGGER_REGISTER_XMM6 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x18)
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#define SOFT_DEBUGGER_REGISTER_XMM7 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x19)
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#define SOFT_DEBUGGER_REGISTER_XMM8 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x1A)
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#define SOFT_DEBUGGER_REGISTER_XMM9 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x1B)
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#define SOFT_DEBUGGER_REGISTER_XMM10 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x1C)
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#define SOFT_DEBUGGER_REGISTER_XMM11 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x1D)
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#define SOFT_DEBUGGER_REGISTER_XMM12 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x1E)
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#define SOFT_DEBUGGER_REGISTER_XMM13 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x1F)
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#define SOFT_DEBUGGER_REGISTER_XMM14 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x20)
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#define SOFT_DEBUGGER_REGISTER_XMM15 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x21)
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#define SOFT_DEBUGGER_REGISTER_MM0 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x22)
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#define SOFT_DEBUGGER_REGISTER_MM1 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x23)
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#define SOFT_DEBUGGER_REGISTER_MM2 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x24)
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#define SOFT_DEBUGGER_REGISTER_MM3 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x25)
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#define SOFT_DEBUGGER_REGISTER_MM4 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x26)
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#define SOFT_DEBUGGER_REGISTER_MM5 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x27)
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#define SOFT_DEBUGGER_REGISTER_MM6 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x28)
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#define SOFT_DEBUGGER_REGISTER_MM7 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x29)
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//
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// This below registers are for GDT, LDT, TSS
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//
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#define SOFT_DEBUGGER_REGISTER_OTHERS_BASE 100
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#define SOFT_DEBUGGER_REGISTER_MAX SOFT_DEBUGGER_REGISTER_MM7
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#define SOFT_DEBUGGER_REGISTER_CS_LIM (SOFT_DEBUGGER_REGISTER_OTHERS_BASE + 0)
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#define SOFT_DEBUGGER_REGISTER_SS_LIM (SOFT_DEBUGGER_REGISTER_OTHERS_BASE + 1)
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#define SOFT_DEBUGGER_REGISTER_GS_LIM (SOFT_DEBUGGER_REGISTER_OTHERS_BASE + 2)
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#define SOFT_DEBUGGER_REGISTER_FS_LIM (SOFT_DEBUGGER_REGISTER_OTHERS_BASE + 3)
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#define SOFT_DEBUGGER_REGISTER_ES_LIM (SOFT_DEBUGGER_REGISTER_OTHERS_BASE + 4)
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#define SOFT_DEBUGGER_REGISTER_DS_LIM (SOFT_DEBUGGER_REGISTER_OTHERS_BASE + 5)
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#define SOFT_DEBUGGER_REGISTER_LDT_LIM (SOFT_DEBUGGER_REGISTER_OTHERS_BASE + 6)
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#define SOFT_DEBUGGER_REGISTER_TSS_LIM (SOFT_DEBUGGER_REGISTER_OTHERS_BASE + 7)
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#define SOFT_DEBUGGER_MSR_EFER (0xC0000080)
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#define SOFT_DEBUGGER_REGISTER_CS_BAS (SOFT_DEBUGGER_REGISTER_OTHERS_BASE + 8)
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#define SOFT_DEBUGGER_REGISTER_SS_BAS (SOFT_DEBUGGER_REGISTER_OTHERS_BASE + 9)
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#define SOFT_DEBUGGER_REGISTER_GS_BAS (SOFT_DEBUGGER_REGISTER_OTHERS_BASE + 10)
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#define SOFT_DEBUGGER_REGISTER_FS_BAS (SOFT_DEBUGGER_REGISTER_OTHERS_BASE + 11)
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#define SOFT_DEBUGGER_REGISTER_ES_BAS (SOFT_DEBUGGER_REGISTER_OTHERS_BASE + 12)
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#define SOFT_DEBUGGER_REGISTER_DS_BAS (SOFT_DEBUGGER_REGISTER_OTHERS_BASE + 13)
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#define SOFT_DEBUGGER_REGISTER_LDT_BAS (SOFT_DEBUGGER_REGISTER_OTHERS_BASE + 14)
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#define SOFT_DEBUGGER_REGISTER_TSS_BAS (SOFT_DEBUGGER_REGISTER_OTHERS_BASE + 15)
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#pragma pack(1)
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#define SOFT_DEBUGGER_REGISTER_CSAS (SOFT_DEBUGGER_REGISTER_OTHERS_BASE + 16)
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#define SOFT_DEBUGGER_REGISTER_SSAS (SOFT_DEBUGGER_REGISTER_OTHERS_BASE + 17)
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#define SOFT_DEBUGGER_REGISTER_GSAS (SOFT_DEBUGGER_REGISTER_OTHERS_BASE + 18)
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#define SOFT_DEBUGGER_REGISTER_FSAS (SOFT_DEBUGGER_REGISTER_OTHERS_BASE + 19)
|
||||
#define SOFT_DEBUGGER_REGISTER_ESAS (SOFT_DEBUGGER_REGISTER_OTHERS_BASE + 20)
|
||||
#define SOFT_DEBUGGER_REGISTER_DSAS (SOFT_DEBUGGER_REGISTER_OTHERS_BASE + 21)
|
||||
#define SOFT_DEBUGGER_REGISTER_LDTAS (SOFT_DEBUGGER_REGISTER_OTHERS_BASE + 22)
|
||||
#define SOFT_DEBUGGER_REGISTER_TSSAS (SOFT_DEBUGGER_REGISTER_OTHERS_BASE + 23)
|
||||
///
|
||||
/// FXSAVE_STATE
|
||||
/// FP / MMX / XMM registers (see fxrstor instruction definition)
|
||||
///
|
||||
typedef struct {
|
||||
UINT16 Fcw;
|
||||
UINT16 Fsw;
|
||||
UINT16 Ftw;
|
||||
UINT16 Opcode;
|
||||
UINT32 Eip;
|
||||
UINT16 Cs;
|
||||
UINT16 Reserved1;
|
||||
UINT32 DataOffset;
|
||||
UINT16 Ds;
|
||||
UINT8 Reserved2[2];
|
||||
UINT32 Mxcsr;
|
||||
UINT32 Mxcsr_Mask;
|
||||
UINT8 St0Mm0[10];
|
||||
UINT8 Reserved3[6];
|
||||
UINT8 St1Mm1[10];
|
||||
UINT8 Reserved4[6];
|
||||
UINT8 St2Mm2[10];
|
||||
UINT8 Reserved5[6];
|
||||
UINT8 St3Mm3[10];
|
||||
UINT8 Reserved6[6];
|
||||
UINT8 St4Mm4[10];
|
||||
UINT8 Reserved7[6];
|
||||
UINT8 St5Mm5[10];
|
||||
UINT8 Reserved8[6];
|
||||
UINT8 St6Mm6[10];
|
||||
UINT8 Reserved9[6];
|
||||
UINT8 St7Mm7[10];
|
||||
UINT8 Reserved10[6];
|
||||
UINT8 Xmm0[16];
|
||||
UINT8 Xmm1[16];
|
||||
UINT8 Xmm2[16];
|
||||
UINT8 Xmm3[16];
|
||||
UINT8 Xmm4[16];
|
||||
UINT8 Xmm5[16];
|
||||
UINT8 Xmm6[16];
|
||||
UINT8 Xmm7[16];
|
||||
UINT8 Reserved11[14 * 16];
|
||||
} DEBUG_DATA_IA32_FX_SAVE_STATE;
|
||||
|
||||
#define SOFT_DEBUGGER_REGISTER_IDT_LIM (SOFT_DEBUGGER_REGISTER_OTHERS_BASE + 24)
|
||||
#define SOFT_DEBUGGER_REGISTER_GDT_LIM (SOFT_DEBUGGER_REGISTER_OTHERS_BASE + 25)
|
||||
#define SOFT_DEBUGGER_REGISTER_IDT_BAS (SOFT_DEBUGGER_REGISTER_OTHERS_BASE + 26)
|
||||
#define SOFT_DEBUGGER_REGISTER_GDT_BAS (SOFT_DEBUGGER_REGISTER_OTHERS_BASE + 27)
|
||||
///
|
||||
/// IA-32 processor context definition
|
||||
///
|
||||
typedef struct {
|
||||
UINT32 ExceptionData;
|
||||
DEBUG_DATA_IA32_FX_SAVE_STATE FxSaveState;
|
||||
UINT32 Dr0;
|
||||
UINT32 Dr1;
|
||||
UINT32 Dr2;
|
||||
UINT32 Dr3;
|
||||
UINT32 Dr6;
|
||||
UINT32 Dr7;
|
||||
UINT32 Eflags;
|
||||
UINT32 Ldtr;
|
||||
UINT32 Tr;
|
||||
UINT32 Gdtr[2];
|
||||
UINT32 Idtr[2];
|
||||
UINT32 Eip;
|
||||
UINT32 Gs;
|
||||
UINT32 Fs;
|
||||
UINT32 Es;
|
||||
UINT32 Ds;
|
||||
UINT32 Cs;
|
||||
UINT32 Ss;
|
||||
UINT32 Cr0;
|
||||
UINT32 Cr1; ///< Reserved
|
||||
UINT32 Cr2;
|
||||
UINT32 Cr3;
|
||||
UINT32 Cr4;
|
||||
UINT32 Edi;
|
||||
UINT32 Esi;
|
||||
UINT32 Ebp;
|
||||
UINT32 Esp;
|
||||
UINT32 Edx;
|
||||
UINT32 Ecx;
|
||||
UINT32 Ebx;
|
||||
UINT32 Eax;
|
||||
} DEBUG_DATA_IA32_SYSTEM_CONTEXT;
|
||||
|
||||
///
|
||||
/// FXSAVE_STATE
|
||||
/// FP / MMX / XMM registers (see fxrstor instruction definition)
|
||||
///
|
||||
typedef struct {
|
||||
UINT16 Fcw;
|
||||
UINT16 Fsw;
|
||||
UINT16 Ftw;
|
||||
UINT16 Opcode;
|
||||
UINT32 Eip;
|
||||
UINT16 Cs;
|
||||
UINT16 Reserved1;
|
||||
UINT32 DataOffset;
|
||||
UINT16 Ds;
|
||||
UINT8 Reserved2[2];
|
||||
UINT32 Mxcsr;
|
||||
UINT32 Mxcsr_Mask;
|
||||
UINT8 St0Mm0[10];
|
||||
UINT8 Reserved3[6];
|
||||
UINT8 St1Mm1[10];
|
||||
UINT8 Reserved4[6];
|
||||
UINT8 St2Mm2[10];
|
||||
UINT8 Reserved5[6];
|
||||
UINT8 St3Mm3[10];
|
||||
UINT8 Reserved6[6];
|
||||
UINT8 St4Mm4[10];
|
||||
UINT8 Reserved7[6];
|
||||
UINT8 St5Mm5[10];
|
||||
UINT8 Reserved8[6];
|
||||
UINT8 St6Mm6[10];
|
||||
UINT8 Reserved9[6];
|
||||
UINT8 St7Mm7[10];
|
||||
UINT8 Reserved10[6];
|
||||
UINT8 Xmm0[16];
|
||||
UINT8 Xmm1[16];
|
||||
UINT8 Xmm2[16];
|
||||
UINT8 Xmm3[16];
|
||||
UINT8 Xmm4[16];
|
||||
UINT8 Xmm5[16];
|
||||
UINT8 Xmm6[16];
|
||||
UINT8 Xmm7[16];
|
||||
UINT8 Xmm8[16];
|
||||
UINT8 Xmm9[16];
|
||||
UINT8 Xmm10[16];
|
||||
UINT8 Xmm11[16];
|
||||
UINT8 Xmm12[16];
|
||||
UINT8 Xmm13[16];
|
||||
UINT8 Xmm14[16];
|
||||
UINT8 Xmm15[16];
|
||||
UINT8 Reserved11[6 * 16];
|
||||
} DEBUG_DATA_X64_FX_SAVE_STATE;
|
||||
|
||||
#define SOFT_DEBUGGER_MSR_EFER (0xC0000080)
|
||||
|
||||
//
|
||||
// Definition for the Index field for DEBUG_DATA_READ_REGISTER_GROUP
|
||||
//
|
||||
#define SOFT_DEBUGGER_REGISTER_GROUP_GPDRS32 1 //for cs,ds,es,fs,gs,ss,eflags,ebp,eip,esp,eax,ebx,ecx,edx,esi,edi,dr0,dr1,dr2,dr3,dr6,dr7
|
||||
#define SOFT_DEBUGGER_REGISTER_GROUP_SEGMENT_LIMITS32 2 //for cslim,sslim,gslim,fslim,eslim,dslim,ldtlim,tsslim
|
||||
#define SOFT_DEBUGGER_REGISTER_GROUP_SEGMENT_BASES32 3 //for csbas,ssbas,gsbas,fsbas,esbas,dsbas,ldtbas,tssbas
|
||||
|
||||
#define SOFT_DEBUGGER_REGISTER_GROUP_SEGMENT64 4 //for cs,ds,es,fs,gs,ss
|
||||
#define SOFT_DEBUGGER_REGISTER_GROUP_GP2_64 5 //for eflags,rbp,rip,rsp
|
||||
#define SOFT_DEBUGGER_REGISTER_GROUP_GP64 6 //for rax,rbx,rcx,rdx,rsi,rdi,r8,r9,r10,r11,r12,r13,r14,r15
|
||||
#define SOFT_DEBUGGER_REGISTER_GROUP_DR64 7 //for dr0,dr1,dr2,dr3,dr6,dr7
|
||||
#define SOFT_DEBUGGER_REGISTER_GROUP_SEGMENT_BAS_LIM64 8 //for ldtbas,ldtlim,gdtbas,gdtlim,cslim,sslim,gslim,fslim,eslim,dslim,ldtlim,tsslim,csbas,ssbas,gsbas,fsbas,esbas,dsbas,ldtbas,tssbas
|
||||
#define SOFT_DEBUGGER_REGISTER_GROUP_SEGMENT_BASES64 9 //for idtr,tr,csas,ssas,gsas,fsas,esas,dsas,idtas,tssas
|
||||
#define SOFT_DEBUGGER_REGISTER_GROUP_CR64 10 //for cr0,cr2,cr3,cr4,cr8
|
||||
#define SOFT_DEBUGGER_REGISTER_GROUP_XMM64 11 //for xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7,xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15
|
||||
///
|
||||
/// x64 processor context definition
|
||||
///
|
||||
typedef struct {
|
||||
UINT64 ExceptionData;
|
||||
DEBUG_DATA_X64_FX_SAVE_STATE FxSaveState;
|
||||
UINT64 Dr0;
|
||||
UINT64 Dr1;
|
||||
UINT64 Dr2;
|
||||
UINT64 Dr3;
|
||||
UINT64 Dr6;
|
||||
UINT64 Dr7;
|
||||
UINT64 Eflags;
|
||||
UINT64 Ldtr;
|
||||
UINT64 Tr;
|
||||
UINT64 Gdtr[2];
|
||||
UINT64 Idtr[2];
|
||||
UINT64 Eip;
|
||||
UINT64 Gs;
|
||||
UINT64 Fs;
|
||||
UINT64 Es;
|
||||
UINT64 Ds;
|
||||
UINT64 Cs;
|
||||
UINT64 Ss;
|
||||
UINT64 Cr0;
|
||||
UINT64 Cr1; ///< Reserved
|
||||
UINT64 Cr2;
|
||||
UINT64 Cr3;
|
||||
UINT64 Cr4;
|
||||
UINT64 Rdi;
|
||||
UINT64 Rsi;
|
||||
UINT64 Rbp;
|
||||
UINT64 Rsp;
|
||||
UINT64 Rdx;
|
||||
UINT64 Rcx;
|
||||
UINT64 Rbx;
|
||||
UINT64 Rax;
|
||||
UINT64 Cr8;
|
||||
UINT64 R8;
|
||||
UINT64 R9;
|
||||
UINT64 R10;
|
||||
UINT64 R11;
|
||||
UINT64 R12;
|
||||
UINT64 R13;
|
||||
UINT64 R14;
|
||||
UINT64 R15;
|
||||
} DEBUG_DATA_X64_SYSTEM_CONTEXT;
|
||||
|
||||
#pragma pack()
|
||||
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -1,42 +0,0 @@
|
|||
/** @file
|
||||
Soft Debugger defintions. The definitions will also be used as part
|
||||
of debug transfer protocol. It is only intended to be used by Debug
|
||||
related module implementation.
|
||||
|
||||
Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __SOFT_DEBUGGER_DEFINITIONS_H__
|
||||
#define __SOFT_DEBUGGER_DEFINITIONS_H__
|
||||
|
||||
//
|
||||
// Definition for processor mode (IA16, IA32, X64, ...)
|
||||
//
|
||||
#define SOFT_DEBUGGER_PROCESSOR_IA16 0
|
||||
#define SOFT_DEBUGGER_PROCESSOR_IA32 1
|
||||
#define SOFT_DEBUGGER_PROCESSOR_X64 2
|
||||
|
||||
//
|
||||
// Break cause defintions
|
||||
//
|
||||
#define SOFT_DEBUGGER_BREAK_CAUSE_UNKNOWN 0
|
||||
#define SOFT_DEBUGGER_BREAK_CAUSE_HW_BREAKPOINT 1
|
||||
#define SOFT_DEBUGGER_BREAK_CAUSE_STEPPING 2
|
||||
#define SOFT_DEBUGGER_BREAK_CAUSE_SW_BREAKPOINT 3
|
||||
#define SOFT_DEBUGGER_BREAK_CAUSE_USER_HALT 4
|
||||
#define SOFT_DEBUGGER_BREAK_CAUSE_IMAGE_LOAD 5
|
||||
#define SOFT_DEBUGGER_BREAK_CAUSE_IMAGE_UNLOAD 6
|
||||
#define SOFT_DEBUGGER_BREAK_CAUSE_SYSTEM_RESET 7
|
||||
#define SOFT_DEBUGGER_BREAK_CAUSE_EXCEPTION 8
|
||||
|
||||
#define SOFT_DEBUGGER_SETTING_SMM_ENTRY_BREAK 1
|
||||
|
||||
#endif
|
||||
|
|
@ -17,16 +17,25 @@
|
|||
#define __TRANSFER_PROTOCOL_H__
|
||||
|
||||
#include "ProcessorContext.h"
|
||||
#include "SoftDebuggerDefinitions.h"
|
||||
|
||||
//
|
||||
// Current revision of transfer protocol
|
||||
//
|
||||
#define DEBUG_AGENT_REVISION ((0 << 16) | 02)
|
||||
#define DEBUG_AGENT_CAPABILITIES 0
|
||||
|
||||
//
|
||||
// Definitions for break command.
|
||||
//
|
||||
#define DEBUG_STARTING_SYMBOL_BREAK (0x21) // '!'
|
||||
#define DEBUG_STARTING_SYMBOL_BREAK_STRING ("!")
|
||||
#define DEBUG_STARTING_SYMBOL_BREAK (0xFC)
|
||||
|
||||
//
|
||||
// Definition for starting symbol of a normal debug packet. Choose a non-ASCII to avoid conflict with other serial output.
|
||||
// Definitions for attach command
|
||||
//
|
||||
#define DEBUG_STARTING_SYMBOL_ATTACH (0xFA)
|
||||
|
||||
//
|
||||
// Definition for starting symbol of a normal debug packet. Choose a non-ASCII to avoid conflict with other serial output.
|
||||
//
|
||||
#define DEBUG_STARTING_SYMBOL_NORMAL (0xFE)
|
||||
|
||||
|
|
@ -34,22 +43,14 @@
|
|||
#pragma pack(1)
|
||||
|
||||
//
|
||||
// Definition for common header for normal debug packets (not including break command)
|
||||
// Definition for debug packet header for normal debug packets (not including break/attach command)
|
||||
//
|
||||
typedef struct {
|
||||
UINT8 StartSymbol;
|
||||
UINT8 Command;
|
||||
UINT8 DataLength;
|
||||
} DEBUG_COMMAND_HEADER;
|
||||
|
||||
//
|
||||
// Structure to facilitate debug packet header parsing or construction
|
||||
//
|
||||
typedef struct {
|
||||
UINT8 Command;
|
||||
UINT8 DataLength;
|
||||
} DEBUG_COMMAND_HEADER_NO_START_SYMBOL;
|
||||
|
||||
UINT8 Length; // Length of Debug Packet including header and payload in byte
|
||||
UINT8 CheckSum;
|
||||
} DEBUG_PACKET_HEADER;
|
||||
|
||||
//
|
||||
// Definition for Command field for debug packets
|
||||
|
|
@ -57,103 +58,79 @@ typedef struct {
|
|||
#define DEBUG_COMMAND_REQUEST (0 << 7)
|
||||
#define DEBUG_COMMAND_RESPONSE (1 << 7)
|
||||
|
||||
|
||||
|
||||
#define DEBUG_COMMAND_RESET (DEBUG_COMMAND_REQUEST | 0) // 0
|
||||
|
||||
#define DEBUG_COMMAND_GO (DEBUG_COMMAND_REQUEST | 1) // 1
|
||||
|
||||
#define DEBUG_COMMAND_BREAK_CAUSE (DEBUG_COMMAND_REQUEST | 2) // 2
|
||||
|
||||
#define DEBUG_COMMAND_SET_HW_BREAKPOINT (DEBUG_COMMAND_REQUEST | 3) // 3
|
||||
#define DEBUG_COMMAND_CLEAR_HW_BREAKPOINT (DEBUG_COMMAND_REQUEST | 4) // 4
|
||||
|
||||
#define DEBUG_COMMAND_SINGLE_STEPPING (DEBUG_COMMAND_REQUEST | 5) // 5
|
||||
|
||||
#define DEBUG_COMMAND_SET_SW_BREAKPOINT (DEBUG_COMMAND_REQUEST | 6) // 6
|
||||
#define DEBUG_COMMAND_CLEAR_SW_BREAKPOINT (DEBUG_COMMAND_REQUEST | 7) // 7
|
||||
|
||||
#define DEBUG_COMMAND_READ_MEMORY_8 (DEBUG_COMMAND_REQUEST | 8) // 8
|
||||
#define DEBUG_COMMAND_READ_MEMORY_16 (DEBUG_COMMAND_REQUEST | 9) // 9
|
||||
#define DEBUG_COMMAND_READ_MEMORY_32 (DEBUG_COMMAND_REQUEST | 10) // 10
|
||||
#define DEBUG_COMMAND_READ_MEMORY_64 (DEBUG_COMMAND_REQUEST | 11) // 11
|
||||
|
||||
#define DEBUG_COMMAND_WRITE_MEMORY_8 (DEBUG_COMMAND_REQUEST | 12) // 12
|
||||
#define DEBUG_COMMAND_WRITE_MEMORY_16 (DEBUG_COMMAND_REQUEST | 13) // 13
|
||||
#define DEBUG_COMMAND_WRITE_MEMORY_32 (DEBUG_COMMAND_REQUEST | 14) // 14
|
||||
#define DEBUG_COMMAND_WRITE_MEMORY_64 (DEBUG_COMMAND_REQUEST | 15) // 15
|
||||
|
||||
#define DEBUG_COMMAND_READ_IO (DEBUG_COMMAND_REQUEST | 16) // 16
|
||||
#define DEBUG_COMMAND_WRITE_IO (DEBUG_COMMAND_REQUEST | 20) // 20
|
||||
|
||||
#define DEBUG_COMMAND_READ_REGISTER (DEBUG_COMMAND_REQUEST | 24) // 24
|
||||
#define DEBUG_COMMAND_WRITE_REGISTER (DEBUG_COMMAND_REQUEST | 26) // 26
|
||||
|
||||
#define DEBUG_COMMAND_STEP_OVER (DEBUG_COMMAND_REQUEST | 28) // 28
|
||||
#define DEBUG_COMMAND_STEP_OUT (DEBUG_COMMAND_REQUEST | 29) // 29
|
||||
#define DEBUG_COMMAND_STEP_BRANCH (DEBUG_COMMAND_REQUEST | 30) // 30
|
||||
|
||||
#define DEBUG_COMMAND_ARCH_MODE (DEBUG_COMMAND_REQUEST | 34) // 34
|
||||
|
||||
#define DEBUG_COMMAND_READ_MSR (DEBUG_COMMAND_REQUEST | 35) // 35
|
||||
#define DEBUG_COMMAND_WRITE_MSR (DEBUG_COMMAND_REQUEST | 36) // 36
|
||||
|
||||
#define DEBUG_COMMAND_READ_REGISTER_GROUP (DEBUG_COMMAND_REQUEST | 37) // 37
|
||||
|
||||
#define DEBUG_COMMAND_SET_DEBUG_FLAG (DEBUG_COMMAND_REQUEST | 38) // 38
|
||||
|
||||
#define DEBUG_COMMAND_GET_REVISION (DEBUG_COMMAND_REQUEST | 39) // 39
|
||||
|
||||
#define DEBUG_COMMAND_GET_EXCEPTION (DEBUG_COMMAND_REQUEST | 40) // 40
|
||||
|
||||
#define DEBUG_COMMAND_SET_VIEWPOINT (DEBUG_COMMAND_REQUEST | 41) // 41
|
||||
|
||||
#define DEBUG_COMMAND_GET_VIEWPOINT (DEBUG_COMMAND_REQUEST | 42) // 42
|
||||
//
|
||||
// HOST initiated commands
|
||||
//
|
||||
#define DEBUG_COMMAND_RESET (DEBUG_COMMAND_REQUEST | 0x00)
|
||||
#define DEBUG_COMMAND_GO (DEBUG_COMMAND_REQUEST | 0x01)
|
||||
#define DEBUG_COMMAND_BREAK_CAUSE (DEBUG_COMMAND_REQUEST | 0x02)
|
||||
#define DEBUG_COMMAND_SET_HW_BREAKPOINT (DEBUG_COMMAND_REQUEST | 0x03)
|
||||
#define DEBUG_COMMAND_CLEAR_HW_BREAKPOINT (DEBUG_COMMAND_REQUEST | 0x04)
|
||||
#define DEBUG_COMMAND_SINGLE_STEPPING (DEBUG_COMMAND_REQUEST | 0x05)
|
||||
#define DEBUG_COMMAND_SET_SW_BREAKPOINT (DEBUG_COMMAND_REQUEST | 0x06)
|
||||
#define DEBUG_COMMAND_READ_MEMORY (DEBUG_COMMAND_REQUEST | 0x07)
|
||||
#define DEBUG_COMMAND_WRITE_MEMORY (DEBUG_COMMAND_REQUEST | 0x08)
|
||||
#define DEBUG_COMMAND_READ_IO (DEBUG_COMMAND_REQUEST | 0x09)
|
||||
#define DEBUG_COMMAND_WRITE_IO (DEBUG_COMMAND_REQUEST | 0x0A)
|
||||
#define DEBUG_COMMAND_READ_REGISTER (DEBUG_COMMAND_REQUEST | 0x0B)
|
||||
#define DEBUG_COMMAND_WRITE_REGISTER (DEBUG_COMMAND_REQUEST | 0x0C)
|
||||
#define DEBUG_COMMAND_READ_ALL_REGISTERS (DEBUG_COMMAND_REQUEST | 0x0D)
|
||||
#define DEBUG_COMMAND_ARCH_MODE (DEBUG_COMMAND_REQUEST | 0x0E)
|
||||
#define DEBUG_COMMAND_READ_MSR (DEBUG_COMMAND_REQUEST | 0x0F)
|
||||
#define DEBUG_COMMAND_WRITE_MSR (DEBUG_COMMAND_REQUEST | 0x10)
|
||||
#define DEBUG_COMMAND_SET_DEBUG_SETTING (DEBUG_COMMAND_REQUEST | 0x11)
|
||||
#define DEBUG_COMMAND_GET_REVISION (DEBUG_COMMAND_REQUEST | 0x12)
|
||||
#define DEBUG_COMMAND_GET_EXCEPTION (DEBUG_COMMAND_REQUEST | 0x13)
|
||||
#define DEBUG_COMMAND_SET_VIEWPOINT (DEBUG_COMMAND_REQUEST | 0x14)
|
||||
#define DEBUG_COMMAND_GET_VIEWPOINT (DEBUG_COMMAND_REQUEST | 0x15)
|
||||
#define DEBUG_COMMAND_DETACH (DEBUG_COMMAND_REQUEST | 0x16)
|
||||
#define DEBUG_COMMAND_CPUID (DEBUG_COMMAND_REQUEST | 0x17)
|
||||
#define DEBUG_COMMAND_SEARCH_SIGNATURE (DEBUG_COMMAND_REQUEST | 0x18)
|
||||
|
||||
//
|
||||
// The below are target side initiated commands.
|
||||
// TARGET initiated commands
|
||||
//
|
||||
#define DEBUG_COMMAND_INIT_BREAK (DEBUG_COMMAND_REQUEST | 63) // 63
|
||||
#define DEBUG_COMMAND_BREAK_POINT (DEBUG_COMMAND_REQUEST | 62) // 62
|
||||
#define DEBUG_COMMAND_MEMORY_READY (DEBUG_COMMAND_REQUEST | 61) // 61
|
||||
|
||||
#define DEBUG_COMMAND_OK (DEBUG_COMMAND_RESPONSE | 0)
|
||||
#define DEBUG_COMMAND_RESEND (DEBUG_COMMAND_RESPONSE | 1)
|
||||
#define DEBUG_COMMAND_ABORT (DEBUG_COMMAND_RESPONSE | 2)
|
||||
#define DEBUG_COMMAND_INIT_BREAK (DEBUG_COMMAND_REQUEST | 0x3F)
|
||||
#define DEBUG_COMMAND_BREAK_POINT (DEBUG_COMMAND_REQUEST | 0x3E)
|
||||
#define DEBUG_COMMAND_MEMORY_READY (DEBUG_COMMAND_REQUEST | 0x3D)
|
||||
#define DEBUG_COMMAND_PRINT_MESSAGE (DEBUG_COMMAND_REQUEST | 0x3C)
|
||||
|
||||
//
|
||||
// The below 2 commands are used when transferring big data (like > ~250 bytes). The sequence is:
|
||||
// Host Macine Target Macine
|
||||
// Request =>
|
||||
// <= IN_PROGRESS with part of the data
|
||||
// CONTINUE =>
|
||||
// (could have multiple IN_PROGRESS and CONTINUE interactions)
|
||||
// <= OK with the last part of data
|
||||
// OK (no data as ACK) =>
|
||||
// Response commands
|
||||
//
|
||||
#define DEBUG_COMMAND_IN_PROGRESS (DEBUG_COMMAND_RESPONSE | 3) // Used when trying to
|
||||
#define DEBUG_COMMAND_CONTINUE (DEBUG_COMMAND_RESPONSE | 4) // Used when trying to transfer big data (like > ~250 bytes)
|
||||
#define DEBUG_COMMAND_OK (DEBUG_COMMAND_RESPONSE | 0x00)
|
||||
#define DEBUG_COMMAND_RESEND (DEBUG_COMMAND_RESPONSE | 0x01)
|
||||
#define DEBUG_COMMAND_ABORT (DEBUG_COMMAND_RESPONSE | 0x02)
|
||||
//
|
||||
// The below 2 commands are used when transferring big data (like > ~250 bytes).
|
||||
// The sequence is:
|
||||
// HOST TARGET
|
||||
// Request =>
|
||||
// <= IN_PROGRESS with partial data
|
||||
// CONTINUE =>
|
||||
// (could have multiple IN_PROGRESS and CONTINUE interactions)
|
||||
// <= OK with the last part of data
|
||||
// OK (no data as ACK) =>
|
||||
//
|
||||
#define DEBUG_COMMAND_IN_PROGRESS (DEBUG_COMMAND_RESPONSE | 0x03)
|
||||
#define DEBUG_COMMAND_CONTINUE (DEBUG_COMMAND_RESPONSE | 0x04)
|
||||
//
|
||||
// The below 2 commands are used to support deferred halt:
|
||||
// TARGET returns HALT_DEFERRED when it receives a HALT request in inter-active mode.
|
||||
// TARGET returns HALT_PROCESSED when it receives a GO request and has a pending HALT request.
|
||||
//
|
||||
#define DEBUG_COMMAND_HALT_DEFERRED (DEBUG_COMMAND_RESPONSE | 0x05)
|
||||
#define DEBUG_COMMAND_HALT_PROCESSED (DEBUG_COMMAND_RESPONSE | 0x06)
|
||||
|
||||
//
|
||||
// The below 2 commands are used to support deferred halt. HALT_DEFERRED will be returned when a halt request received while target is already in inter-active mode.
|
||||
// HALT_PROCESSED will be return as a possible return value for GO command, if target has a pending halt request.
|
||||
//
|
||||
#define DEBUG_COMMAND_HALT_DEFERRED (DEBUG_COMMAND_RESPONSE | 5)
|
||||
#define DEBUG_COMMAND_HALT_PROCESSED (DEBUG_COMMAND_RESPONSE | 6)
|
||||
|
||||
#define DEBUG_COMMAND_TIMEOUT (DEBUG_COMMAND_RESPONSE | 7)
|
||||
#define DEBUG_COMMAND_NOT_SUPPORTED (DEBUG_COMMAND_RESPONSE | 15)
|
||||
#define DEBUG_COMMAND_TIMEOUT (DEBUG_COMMAND_RESPONSE | 0x07)
|
||||
#define DEBUG_COMMAND_NOT_SUPPORTED (DEBUG_COMMAND_RESPONSE | 0x0F)
|
||||
|
||||
//
|
||||
// Definition for data field for debug packets
|
||||
//
|
||||
#define DEBUG_DATA_MAXIMUM_LENGTH_FOR_SMALL_COMMANDS 20
|
||||
#define DEBUG_DATA_UPPER_LIMIT 0xff // Upper limit for the data size, by the limit of the packet header definition.
|
||||
|
||||
#define DEBUG_DATA_UPPER_LIMIT 0xff // This is the upper limit for the data size, by the limit of the packet header definition.
|
||||
|
||||
#define DEBUG_DATA_MAXIMUM_REAL_DATA 0xf8
|
||||
|
||||
#define DEBUG_DEFINITION_MAX_IO_LENGTH 4
|
||||
#define DEBUG_DATA_MAXIMUM_REAL_DATA (DEBUG_DATA_UPPER_LIMIT - sizeof (DEBUG_PACKET_HEADER))
|
||||
|
||||
//
|
||||
// Response data for DEBUG_COMMAND_BREAK_CAUSE
|
||||
|
|
@ -162,7 +139,6 @@ typedef struct {
|
|||
UINT8 Cause;
|
||||
UINT64 StopAddress;
|
||||
} DEBUG_DATA_RESPONSE_BREAK_CAUSE;
|
||||
|
||||
//
|
||||
// Break type defintions for DEBUG_DATA_BREAK_CAUSE
|
||||
//
|
||||
|
|
@ -183,7 +159,6 @@ typedef struct {
|
|||
typedef struct {
|
||||
UINT8 CpuMode;
|
||||
} DEBUG_DATA_RESPONSE_ARCH_MODE;
|
||||
|
||||
//
|
||||
// Cpu architecture defintions for DEBUG_DATA_RESPONSE_ARCH_MODE
|
||||
//
|
||||
|
|
@ -191,28 +166,23 @@ typedef struct {
|
|||
#define DEBUG_DATA_BREAK_CPU_ARCH_IA32 1
|
||||
#define DEBUG_DATA_BREAK_CPU_ARCH_X64 2
|
||||
|
||||
//
|
||||
// Command and response data for DEBUG_COMMAND_XX_YY_BREAKPOINT
|
||||
//
|
||||
typedef struct {
|
||||
UINT8 Length:2; // Refer to below DEBUG_DATA_BREAKPOINT_LENGTH_XX macros
|
||||
UINT8 Access:2; // Refer to below DEBUG_DATA_BREAKPOINT_ACCESS_XX macros
|
||||
UINT8 Index:2; // Index of debug register
|
||||
UINT8 Reserved:2;
|
||||
} DEBUG_DATA_BREAKPOINT_TYPE;
|
||||
|
||||
#define DEBUG_DATA_BREAKPOINT_MEMORY_ACCESS (0x11)
|
||||
#define DEBUG_DATA_BREAKPOINT_IO_ACCESS (0x10)
|
||||
#define DEBUG_DATA_BREAKPOINT_MEMORY_WRITE (0x01)
|
||||
#define DEBUG_DATA_BREAKPOINT_MEMORY_EXECUTE (0x00)
|
||||
|
||||
#define DEBUG_DATA_BREAKPOINT_LENGTH_64 (0x11)
|
||||
#define DEBUG_DATA_BREAKPOINT_LENGTH_32 (0x10)
|
||||
#define DEBUG_DATA_BREAKPOINT_LENGTH_16 (0x01)
|
||||
#define DEBUG_DATA_BREAKPOINT_LENGTH_8 (0x00)
|
||||
#define DEBUG_DATA_BREAKPOINT_MEMORY_ACCESS (0x3)
|
||||
#define DEBUG_DATA_BREAKPOINT_IO_ACCESS (0x2)
|
||||
#define DEBUG_DATA_BREAKPOINT_MEMORY_WRITE (0x1)
|
||||
#define DEBUG_DATA_BREAKPOINT_MEMORY_EXECUTE (0x0)
|
||||
#define DEBUG_DATA_BREAKPOINT_LENGTH_32 (0x3)
|
||||
#define DEBUG_DATA_BREAKPOINT_LENGTH_64 (0x2)
|
||||
#define DEBUG_DATA_BREAKPOINT_LENGTH_16 (0x1)
|
||||
#define DEBUG_DATA_BREAKPOINT_LENGTH_8 (0x0)
|
||||
|
||||
//
|
||||
// Command data for DEBUG_COMMAND_SET_HW_BREAKPOINT
|
||||
// Request data for DEBUG_COMMAND_SET_HW_BREAKPOINT
|
||||
//
|
||||
typedef struct {
|
||||
DEBUG_DATA_BREAKPOINT_TYPE Type;
|
||||
|
|
@ -220,133 +190,98 @@ typedef struct {
|
|||
} DEBUG_DATA_SET_HW_BREAKPOINT;
|
||||
|
||||
//
|
||||
// Command data for DEBUG_COMMAND_CLEAR_HW_BREAKPOINT
|
||||
// Request data for DEBUG_COMMAND_CLEAR_HW_BREAKPOINT
|
||||
//
|
||||
typedef struct {
|
||||
UINT8 IndexMask; // 0x0f will clear all hw breakpoints
|
||||
} DEBUG_DATA_CLEAR_HW_BREAKPOINT;
|
||||
|
||||
//
|
||||
// Command data for DEBUG_COMMAND_SET_SW_BREAKPOINT
|
||||
// Request and response data for DEBUG_COMMAND_SET_SW_BREAKPOINT
|
||||
//
|
||||
typedef struct {
|
||||
UINT64 Address;
|
||||
} DEBUG_DATA_SET_SW_BREAKPOINT;
|
||||
|
||||
//
|
||||
// Response data for DEBUG_COMMAND_SET_SW_BREAKPOINT
|
||||
//
|
||||
typedef struct {
|
||||
UINT8 OriginalData;
|
||||
} DEBUG_DATA_RESPONSE_SET_SW_BREAKPOINT;
|
||||
|
||||
//
|
||||
// Command data for DEBUG_COMMAND_CLEAR_SW_BREAKPOINT
|
||||
//
|
||||
typedef DEBUG_DATA_SET_SW_BREAKPOINT DEBUG_DATA_CLEAR_SW_BREAKPOINT;
|
||||
|
||||
//
|
||||
// Command data for DEBUG_COMMAND_READ_MEMORY_XX
|
||||
// Request data for DEBUG_COMMAND_READ_MEMORY
|
||||
//
|
||||
typedef struct {
|
||||
UINT64 Address;
|
||||
UINT8 Width;
|
||||
UINT16 Count;
|
||||
} DEBUG_DATA_READ_MEMORY_8;
|
||||
|
||||
typedef DEBUG_DATA_READ_MEMORY_8 DEBUG_DATA_READ_MEMORY_16;
|
||||
|
||||
typedef DEBUG_DATA_READ_MEMORY_8 DEBUG_DATA_READ_MEMORY_32;
|
||||
|
||||
typedef DEBUG_DATA_READ_MEMORY_8 DEBUG_DATA_READ_MEMORY_64;
|
||||
} DEBUG_DATA_READ_MEMORY;
|
||||
|
||||
//
|
||||
// Command data for DEBUG_COMMAND_WRITE_MEMORY_XX
|
||||
// Request data for DEBUG_COMMAND_WRITE_MEMORY
|
||||
//
|
||||
typedef struct {
|
||||
UINT64 Address;
|
||||
UINT8 Width;
|
||||
UINT16 Count;
|
||||
UINT8 Data; // The actual length for this field is decided by Width x Count
|
||||
} DEBUG_DATA_WRITE_MEMORY_8;
|
||||
|
||||
typedef DEBUG_DATA_WRITE_MEMORY_8 DEBUG_DATA_WRITE_MEMORY_16;
|
||||
|
||||
typedef DEBUG_DATA_WRITE_MEMORY_8 DEBUG_DATA_WRITE_MEMORY_32;
|
||||
|
||||
typedef DEBUG_DATA_WRITE_MEMORY_8 DEBUG_DATA_WRITE_MEMORY_64;
|
||||
UINT8 Data[1]; // The actual length is (Width * Count)
|
||||
} DEBUG_DATA_WRITE_MEMORY;
|
||||
|
||||
//
|
||||
// Command data for DEBUG_COMMAND_READ_IO
|
||||
// Request and response data for DEBUG_COMMAND_READ_IO
|
||||
//
|
||||
typedef struct {
|
||||
UINT16 Port;
|
||||
UINT64 Port;
|
||||
UINT8 Width;
|
||||
} DEBUG_DATA_READ_IO;
|
||||
|
||||
//
|
||||
// Response data for DEBUG_COMMAND_READ_IO
|
||||
//
|
||||
typedef struct {
|
||||
UINT8 Data; // The actual length of this structure will be adjusted according to the Width field
|
||||
UINT8 Data[1]; // The actual length depends on the packet header
|
||||
} DEBUG_DATA_RESPONSE_READ_IO;
|
||||
|
||||
//
|
||||
// Command data for DEBUG_COMMAND_WRITE_IO
|
||||
// Request data for DEBUG_COMMAND_WRITE_IO
|
||||
//
|
||||
typedef struct {
|
||||
UINT16 Port;
|
||||
UINT64 Port;
|
||||
UINT8 Width;
|
||||
UINT8 Data; // The actual length of this structure will be adjusted according to the Width field
|
||||
UINT8 Data[1]; // The actual length is Width
|
||||
} DEBUG_DATA_WRITE_IO;
|
||||
|
||||
//
|
||||
// Command data for DEBUG_COMMAND_READ_REGISTER
|
||||
// Request data for DEBUG_COMMAND_READ_REGISTER
|
||||
//
|
||||
typedef struct {
|
||||
UINT8 Index; // defined as DEBUG_DEFINITION_REGISTER_XX
|
||||
UINT8 Offset:4;
|
||||
UINT8 Length:4;
|
||||
UINT8 Index; // defined as SOFT_DEBUGGER_REGISTER_XX
|
||||
} DEBUG_DATA_READ_REGISTER;
|
||||
|
||||
//
|
||||
// Command data for DEBUG_COMMAND_WRITE_REGISTER
|
||||
// Request data for DEBUG_COMMAND_WRITE_REGISTER
|
||||
//
|
||||
typedef struct {
|
||||
UINT8 Index; // defined as DEBUG_DEFINITION_REGISTER_XX
|
||||
UINT8 Offset:4;
|
||||
UINT8 Length:4;
|
||||
UINT64 Value;
|
||||
UINT8 Index; // defined as SOFT_DEBUGGER_REGISTER_XX
|
||||
UINT8 Length;
|
||||
UINT8 Data[1]; // The actual length is Length
|
||||
} DEBUG_DATA_WRITE_REGISTER;
|
||||
|
||||
//
|
||||
// Command data for DEBUG_COMMAND_READ_MSR
|
||||
// Request and response data for DEBUG_COMMAND_READ_MSR
|
||||
//
|
||||
typedef struct {
|
||||
UINT32 Index;
|
||||
} DEBUG_DATA_READ_MSR;
|
||||
|
||||
//
|
||||
// Response data for DEBUG_COMMAND_READ_MSR
|
||||
//
|
||||
typedef struct {
|
||||
UINT64 Value;
|
||||
} DEBUG_DATA_RESPONSE_READ_MSR;
|
||||
|
||||
//
|
||||
// Command data for DEBUG_COMMAND_WRITE_MSR
|
||||
// Request data for DEBUG_COMMAND_WRITE_MSR
|
||||
//
|
||||
typedef struct {
|
||||
UINT32 Index;
|
||||
UINT64 Value;
|
||||
} DEBUG_DATA_WRITE_MSR;
|
||||
|
||||
//
|
||||
// Command data for DEBUG_COMMAND_READ_REGISTER_GROUP
|
||||
//
|
||||
typedef struct {
|
||||
// For possible values, refer to the definition for DEBUG_DEFINITION_REGISTER_GROUP_XXX (in another .h file as it is architecture specific)
|
||||
UINT8 Index;
|
||||
} DEBUG_DATA_READ_REGISTER_GROUP;
|
||||
|
||||
//
|
||||
// Response data for DEBUG_COMMAND_GET_REVISION
|
||||
//
|
||||
|
|
@ -360,24 +295,31 @@ typedef struct {
|
|||
//
|
||||
typedef struct {
|
||||
UINT8 ExceptionNum;
|
||||
UINT64 ExceptionData;
|
||||
UINT32 ExceptionData;
|
||||
} DEBUG_DATA_RESPONSE_GET_EXCEPTION;
|
||||
|
||||
typedef struct {
|
||||
UINT8 DRn; // The index of DR register which to be used as temporary breakpoint
|
||||
} DEBUG_DATA_STEP_OVER;
|
||||
|
||||
//
|
||||
// Command data for DEBUG_COMMAND_SET_DEBUG_FLAG
|
||||
// Request data for DEBUG_DATA_SET_DEBUG_SETTING
|
||||
//
|
||||
typedef struct {
|
||||
UINT32 DebugFlag; // The index of DR register which to be used as temporary breakpoint
|
||||
} DEBUG_DATA_SET_DEBUG_FLAG;
|
||||
UINT8 Key;
|
||||
UINT8 Value;
|
||||
} DEBUG_DATA_SET_DEBUG_SETTING;
|
||||
//
|
||||
// Supported keys
|
||||
//
|
||||
#define DEBUG_AGENT_SETTING_SMM_ENTRY_BREAK 1
|
||||
#define DEBUG_AGENT_SETTING_PRINT_ERROR_LEVEL 2
|
||||
//
|
||||
// Bitmask of print error level for debug message
|
||||
//
|
||||
#define DEBUG_AGENT_ERROR BIT0
|
||||
#define DEBUG_AGENT_WARNING BIT1
|
||||
#define DEBUG_AGENT_INFO BIT2
|
||||
#define DEBUG_AGENT_VERBOSE BIT3
|
||||
|
||||
//
|
||||
// Command data for DEBUG_COMMAND_SET_VIEWPOINT
|
||||
// If viewpoint is changed successfully, DEBUG_COMMAND_OK will be returned.
|
||||
// If viewpoint is not availabe, DEBUG_COMMAND_NOT_SUPPORTED will be returned.
|
||||
// Request data for DEBUG_COMMAND_SET_VIEWPOINT
|
||||
//
|
||||
typedef struct {
|
||||
UINT32 ViewPoint; // The index of viewpoint will be set
|
||||
|
|
@ -390,19 +332,38 @@ typedef struct {
|
|||
UINT32 ViewPoint; // The index of viewpoint will be returned
|
||||
} DEBUG_DATA_RESPONSE_GET_VIEWPOINT;
|
||||
|
||||
//
|
||||
// Request and response data for DEBUG_COMMAND_CPUID
|
||||
//
|
||||
typedef struct {
|
||||
UINT32 Eax; // The value of EAX prior to invoking the CPUID instruction
|
||||
UINT32 Ecx; // The value of ECX prior to invoking the CPUID instruction
|
||||
} DEBUG_DATA_CPUID;
|
||||
|
||||
typedef struct {
|
||||
UINT32 Eax; // The value of EAX returned by the CPUID instruction
|
||||
UINT32 Ebx; // The value of EBX returned by the CPUID instruction
|
||||
UINT32 Ecx; // The value of ECX returned by the CPUID instruction
|
||||
UINT32 Edx; // The value of EDX returned by the CPUID instruction
|
||||
} DEBUG_DATA_RESPONSE_CPUID;
|
||||
|
||||
//
|
||||
// Request and response data for DEBUG_COMMAND_SEARCH_SIGNATURE
|
||||
//
|
||||
typedef struct {
|
||||
UINT64 Start;
|
||||
UINT32 Count;
|
||||
UINT32 Alignment;
|
||||
BOOLEAN Positive; // TRUE to search in higher address memory
|
||||
UINT8 DataLength;
|
||||
UINT8 Data[1];
|
||||
} DEBUG_DATA_SEARCH_SIGNATURE;
|
||||
|
||||
typedef struct {
|
||||
UINT64 Address; // -1 indicates not found
|
||||
} DEBUG_DATA_RESPONSE_SEARCH_SIGNATURE;
|
||||
|
||||
#pragma pack()
|
||||
|
||||
#define DEBUG_PACKET_CONSTRUCTOR_WITH_NO_DATA(DebugPacket,ShortCommandType) \
|
||||
((DEBUG_COMMAND_HEADER *)DebugPacket)->StartSymbol = DEBUG_STARTING_SYMBOL_NORMAL; \
|
||||
((DEBUG_COMMAND_HEADER *)DebugPacket)->Command = DEBUG_COMMAND_##ShortCommandType; \
|
||||
((DEBUG_COMMAND_HEADER *)DebugPacket)->DataLength = 0;
|
||||
|
||||
#define DEBUG_PACKET_CONSTRUCTOR_WITH_DATA(DebugPacket,ShortCommandType, DebugPacketDataPointer, PacketLength) \
|
||||
((DEBUG_COMMAND_HEADER *)DebugPacket)->StartSymbol = DEBUG_STARTING_SYMBOL_NORMAL; \
|
||||
((DEBUG_COMMAND_HEADER *)DebugPacket)->Command = DEBUG_COMMAND_##ShortCommandType; \
|
||||
((DEBUG_COMMAND_HEADER *)DebugPacket)->DataLength = sizeof (DEBUG_DATA_##ShortCommandType); \
|
||||
*DebugPacketDataPointer = (DEBUG_DATA_##ShortCommandType *)((DEBUG_COMMAND_HEADER *)DebugPacket+1); \
|
||||
*PacketLength = sizeof (DEBUG_COMMAND_HEADER) + sizeof (DEBUG_DATA_##ShortCommandType);
|
||||
|
||||
#endif
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -31,6 +31,7 @@
|
|||
#include <Library/LocalApicLib.h>
|
||||
#include <Library/DebugLib.h>
|
||||
#include <Library/TimerLib.h>
|
||||
#include <Library/PrintLib.h>
|
||||
|
||||
#include <TransferProtocol.h>
|
||||
#include <ImageDebugSupport.h>
|
||||
|
|
@ -39,9 +40,6 @@
|
|||
#include "DebugTimer.h"
|
||||
#include "ArchDebugSupport.h"
|
||||
|
||||
#define DEBUG_AGENT_REVISION ((0 << 16) | 01)
|
||||
#define DEBUG_AGENT_CAPABILITIES 0
|
||||
|
||||
#define DEBUG_INT1_VECTOR 1
|
||||
#define DEBUG_INT3_VECTOR 3
|
||||
#define DEBUG_TIMER_VECTOR 32
|
||||
|
|
@ -55,19 +53,46 @@ extern UINTN Exception0Handle;
|
|||
extern UINTN TimerInterruptHandle;
|
||||
extern UINT16 ExceptionStubHeaderSize;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
UINT32 HostPresent : 1;
|
||||
UINT32 BreakOnNextSmi : 1;
|
||||
UINT32 Reserved : 30;
|
||||
} Bits;
|
||||
UINT32 Uint32;
|
||||
} DEBUG_AGENT_FLAG;
|
||||
//
|
||||
// CPU exception information issued by debug agent
|
||||
//
|
||||
typedef struct {
|
||||
//
|
||||
// This field is used to save CPU content before executing HOST command
|
||||
//
|
||||
BASE_LIBRARY_JUMP_BUFFER JumpBuffer;
|
||||
//
|
||||
// This filed returens the exception information issued by HOST command
|
||||
//
|
||||
DEBUG_DATA_RESPONSE_GET_EXCEPTION ExceptionContent;
|
||||
} DEBUG_AGENT_EXCEPTION_BUFFER;
|
||||
|
||||
#pragma pack(1)
|
||||
typedef struct {
|
||||
//
|
||||
// Lower 32 bits to store the status of DebugAgent
|
||||
//
|
||||
UINT32 HostAttached : 1; // 1: HOST is attached
|
||||
UINT32 AgentInProgress : 1; // 1: Debug Agent is communicating with HOST
|
||||
UINT32 MemoryReady : 1; // 1: Memory is ready
|
||||
UINT32 SteppingFlag : 1; // 1: Agent is running stepping command
|
||||
UINT32 Reserved1 : 28;
|
||||
|
||||
//
|
||||
// Higher 32bits to control the behavior of DebugAgent
|
||||
//
|
||||
UINT32 BreakOnNextSmi : 1; // 1: Break on next SMI
|
||||
UINT32 PrintErrorLevel : 8; // Bitmask of print error level for debug message
|
||||
UINT32 Reserved2 : 23;
|
||||
} DEBUG_AGENT_FLAG;
|
||||
|
||||
typedef struct {
|
||||
DEBUG_AGENT_FLAG DebugFlag;
|
||||
UINT64 DebugPortHandle;
|
||||
//
|
||||
// Pointer to DEBUG_AGENT_EXCEPTION_BUFFER
|
||||
//
|
||||
UINT64 ExceptionBufferPointer;
|
||||
} DEBUG_AGENT_MAILBOX;
|
||||
#pragma pack()
|
||||
|
||||
|
|
@ -115,31 +140,11 @@ InitializeDebugIdt (
|
|||
VOID
|
||||
);
|
||||
|
||||
/**
|
||||
Write specified register into save CPU context.
|
||||
|
||||
@param[in] CpuContext Pointer to saved CPU context.
|
||||
@param[in] Index Register index value.
|
||||
@param[in] Offset Offset in register address range
|
||||
@param[in] Width Data width to read.
|
||||
@param[in] RegisterBuffer Pointer to input buffer with data.
|
||||
|
||||
**/
|
||||
VOID
|
||||
ArchWriteRegisterBuffer (
|
||||
IN DEBUG_CPU_CONTEXT *CpuContext,
|
||||
IN UINT8 Index,
|
||||
IN UINT8 Offset,
|
||||
IN UINT8 Width,
|
||||
IN UINT8 *RegisterBuffer
|
||||
);
|
||||
|
||||
/**
|
||||
Read register value from saved CPU context.
|
||||
|
||||
@param[in] CpuContext Pointer to saved CPU context.
|
||||
@param[in] Index Register index value.
|
||||
@param[in] Offset Offset in register address range
|
||||
@param[in] Width Data width to read.
|
||||
|
||||
@return The address of register value.
|
||||
|
|
@ -149,14 +154,12 @@ UINT8 *
|
|||
ArchReadRegisterBuffer (
|
||||
IN DEBUG_CPU_CONTEXT *CpuContext,
|
||||
IN UINT8 Index,
|
||||
IN UINT8 Offset,
|
||||
IN UINT8 *Width
|
||||
);
|
||||
|
||||
/**
|
||||
Send packet with response data to HOST.
|
||||
|
||||
@param[in] CpuContext Pointer to saved CPU context.
|
||||
@param[in] Data Pointer to response data buffer.
|
||||
@param[in] DataSize Size of response data in byte.
|
||||
|
||||
|
|
@ -166,121 +169,19 @@ ArchReadRegisterBuffer (
|
|||
**/
|
||||
RETURN_STATUS
|
||||
SendDataResponsePacket (
|
||||
IN DEBUG_CPU_CONTEXT *CpuContext,
|
||||
IN UINT8 *Data,
|
||||
IN UINT16 DataSize
|
||||
);
|
||||
|
||||
/**
|
||||
Read segment selector by register index.
|
||||
Check if HOST is attached based on Mailbox.
|
||||
|
||||
@param[in] CpuContext Pointer to saved CPU context.
|
||||
@param[in] RegisterIndex Register Index.
|
||||
|
||||
@return Value of segment selector.
|
||||
|
||||
**/
|
||||
UINT64
|
||||
ReadRegisterSelectorByIndex (
|
||||
IN DEBUG_CPU_CONTEXT *CpuContext,
|
||||
IN UINT8 RegisterIndex
|
||||
);
|
||||
|
||||
/**
|
||||
Read group register of common registers.
|
||||
|
||||
@param[in] CpuContext Pointer to saved CPU context.
|
||||
@param[in] RegisterGroup Pointer to Group registers.
|
||||
|
||||
**/
|
||||
VOID
|
||||
ReadRegisterGroup (
|
||||
IN DEBUG_CPU_CONTEXT *CpuContext,
|
||||
IN DEBUG_DATA_REPONSE_READ_REGISTER_GROUP *RegisterGroup
|
||||
);
|
||||
|
||||
/**
|
||||
Read group register of Segment Base.
|
||||
|
||||
@param[in] CpuContext Pointer to saved CPU context.
|
||||
@param[in] RegisterGroupSegBase Pointer to Group registers.
|
||||
|
||||
**/
|
||||
VOID
|
||||
ReadRegisterGroupSegBase (
|
||||
IN DEBUG_CPU_CONTEXT *CpuContext,
|
||||
IN DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGBASE *RegisterGroupSegBase
|
||||
);
|
||||
|
||||
/**
|
||||
Read gourp register of Segment Limit.
|
||||
|
||||
@param[in] CpuContext Pointer to saved CPU context.
|
||||
@param[in] RegisterGroupSegLim Pointer to Group registers.
|
||||
|
||||
**/
|
||||
VOID
|
||||
ReadRegisterGroupSegLim (
|
||||
IN DEBUG_CPU_CONTEXT *CpuContext,
|
||||
IN DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGLIM *RegisterGroupSegLim
|
||||
);
|
||||
|
||||
/**
|
||||
Read group register by group index.
|
||||
|
||||
@param[in] CpuContext Pointer to saved CPU context.
|
||||
@param[in] GroupIndex Group Index.
|
||||
|
||||
@retval RETURN_SUCCESS Read successfully.
|
||||
@retval RETURN_NOT_SUPPORTED Group index cannot be supported.
|
||||
|
||||
**/
|
||||
RETURN_STATUS
|
||||
ArchReadRegisterGroup (
|
||||
IN DEBUG_CPU_CONTEXT *CpuContext,
|
||||
IN UINT8 GroupIndex
|
||||
);
|
||||
|
||||
/**
|
||||
Send acknowledge packet to HOST.
|
||||
|
||||
@param AckCommand Type of Acknowledge packet.
|
||||
|
||||
**/
|
||||
VOID
|
||||
SendAckPacket (
|
||||
IN UINT8 AckCommand
|
||||
);
|
||||
|
||||
/**
|
||||
Receive acknowledge packet OK from HOST in specified time.
|
||||
|
||||
@param[in] Timeout Time out value to wait for acknowlege from HOST.
|
||||
The unit is microsecond.
|
||||
@param[out] BreakReceived If BreakReceived is not NULL,
|
||||
TRUE is retured if break-in symbol received.
|
||||
FALSE is retured if break-in symbol not received.
|
||||
|
||||
@retval RETRUEN_SUCCESS Succeed to receive acknowlege packet from HOST,
|
||||
the type of acknowlege packet saved in Ack.
|
||||
@retval RETURN_TIMEOUT Specified timeout value was up.
|
||||
|
||||
**/
|
||||
RETURN_STATUS
|
||||
WaitForAckPacketOK (
|
||||
IN UINTN Timeout,
|
||||
OUT BOOLEAN *BreakReceived OPTIONAL
|
||||
);
|
||||
|
||||
/**
|
||||
Check if HOST is connected based on Mailbox.
|
||||
|
||||
@retval TRUE HOST is connected.
|
||||
@retval FALSE HOST is not connected.
|
||||
@retval TRUE HOST is attached.
|
||||
@retval FALSE HOST is not attached.
|
||||
|
||||
**/
|
||||
BOOLEAN
|
||||
IsHostConnected (
|
||||
IsHostAttached (
|
||||
VOID
|
||||
);
|
||||
|
||||
|
|
@ -306,5 +207,40 @@ GetDebugPortHandle (
|
|||
VOID
|
||||
);
|
||||
|
||||
/**
|
||||
Read the Attach/Break-in symbols from the debug port.
|
||||
|
||||
@param[in] Handle Pointer to Debug Port handle.
|
||||
@param[out] BreakSymbol Returned break symbol.
|
||||
|
||||
@retval EFI_SUCCESS Read the symbol in BreakSymbol.
|
||||
@retval EFI_NOT_FOUND No read the break symbol.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
DebugReadBreakSymbol (
|
||||
IN DEBUG_PORT_HANDLE Handle,
|
||||
OUT UINT8 *BreakSymbol
|
||||
);
|
||||
|
||||
/**
|
||||
Prints a debug message to the debug port if the specified error level is enabled.
|
||||
|
||||
If any bit in ErrorLevel is also set in Mainbox, then print the message specified
|
||||
by Format and the associated variable argument list to the debug port.
|
||||
|
||||
@param[in] ErrorLevel The error level of the debug message.
|
||||
@param[in] Format Format string for the debug message to print.
|
||||
@param[in] ... Variable argument list whose contents are accessed
|
||||
based on the format string specified by Format.
|
||||
|
||||
**/
|
||||
VOID
|
||||
EFIAPI
|
||||
DebugAgentMsgPrint (
|
||||
IN UINT8 ErrorLevel,
|
||||
IN CHAR8 *Format,
|
||||
...
|
||||
);
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/** @file
|
||||
Multi-Processor support functions implementation.
|
||||
|
||||
Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>
|
||||
Copyright (c) 2010 - 2012, Intel Corporation. All rights reserved.<BR>
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
|
|
@ -101,7 +101,7 @@ HaltOtherProcessors (
|
|||
IN UINT32 CurrentProcessorIndex
|
||||
)
|
||||
{
|
||||
|
||||
DebugAgentMsgPrint (DEBUG_AGENT_INFO, "processor[%x]:Try to halt other processors.\n", CurrentProcessorIndex);
|
||||
if (!IsBsp (CurrentProcessorIndex)) {
|
||||
SetIpiSentByApFlag (TRUE);;
|
||||
}
|
||||
|
|
@ -305,7 +305,7 @@ SetDebugViewPoint (
|
|||
}
|
||||
|
||||
/**
|
||||
Initialize debug timer.
|
||||
Set the IPI send by BPS/AP flag.
|
||||
|
||||
@param[in] IpiSentByApFlag TRUE means this IPI is sent by AP.
|
||||
FALSE means this IPI is sent by BSP.
|
||||
|
|
@ -324,7 +324,7 @@ SetIpiSentByApFlag (
|
|||
}
|
||||
|
||||
/**
|
||||
Check if any processor breaks.
|
||||
Check the next pending breaking CPU.
|
||||
|
||||
@retval others There is at least one processor broken, the minimum
|
||||
index number of Processor returned.
|
||||
|
|
@ -332,7 +332,7 @@ SetIpiSentByApFlag (
|
|||
|
||||
**/
|
||||
UINT32
|
||||
FindCpuNotRunning (
|
||||
FindNextPendingBreakCpu (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
|
|
@ -368,3 +368,37 @@ IsAllCpuRunning (
|
|||
return TRUE;
|
||||
}
|
||||
|
||||
/**
|
||||
Check if the current processor is the first breaking processor.
|
||||
|
||||
If yes, halt other processors.
|
||||
|
||||
@param[in] ProcessorIndex Processor index value.
|
||||
|
||||
@return TRUE This processor is the first breaking processor.
|
||||
@return FALSE This processor is not the first breaking processor.
|
||||
|
||||
**/
|
||||
BOOLEAN
|
||||
IsFirstBreakProcessor (
|
||||
IN UINT32 ProcessorIndex
|
||||
)
|
||||
{
|
||||
if (MultiProcessorDebugSupport) {
|
||||
if (mDebugMpContext.BreakAtCpuIndex != (UINT32) -1) {
|
||||
//
|
||||
// The current processor is not the first breaking one.
|
||||
//
|
||||
SetCpuBreakFlagByIndex (ProcessorIndex, TRUE);
|
||||
return FALSE;
|
||||
} else {
|
||||
//
|
||||
// If no any processor breaks, try to halt other processors
|
||||
//
|
||||
HaltOtherProcessors (ProcessorIndex);
|
||||
return TRUE;
|
||||
}
|
||||
}
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/** @file
|
||||
Header file for Multi-Processor support.
|
||||
|
||||
Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
|
||||
Copyright (c) 2010 - 2012, Intel Corporation. All rights reserved.<BR>
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
|
|
@ -32,7 +32,7 @@ typedef struct {
|
|||
UINT32 BreakAtCpuIndex; ///< Processor index value of the current breaking CPU
|
||||
UINT32 DebugTimerInitCount; ///< Record BSP's init timer count
|
||||
BOOLEAN IpiSentByAp; ///< TRUR: IPI is sent by AP. TALSE: IPI is sent by BSP
|
||||
BOOLEAN RunCommandSet; ///< TRUE: RUN commmand is not executed. FALSE : RUN command is executed.
|
||||
BOOLEAN RunCommandSet; ///< TRUE: RUN commmand is executing. FALSE : RUN command has been executed.
|
||||
} DEBUG_MP_CONTEXT;
|
||||
|
||||
extern CONST BOOLEAN MultiProcessorDebugSupport;
|
||||
|
|
@ -181,7 +181,7 @@ SetDebugViewPoint (
|
|||
);
|
||||
|
||||
/**
|
||||
Initialize debug timer.
|
||||
Set the IPI send by BPS/AP flag.
|
||||
|
||||
@param[in] IpiSentByApFlag TRUE means this IPI is sent by AP.
|
||||
FALSE means this IPI is sent by BSP.
|
||||
|
|
@ -193,7 +193,7 @@ SetIpiSentByApFlag (
|
|||
);
|
||||
|
||||
/**
|
||||
Check if any processor breaks.
|
||||
Check the next pending breaking CPU.
|
||||
|
||||
@retval others There is at least one processor broken, the minimum
|
||||
index number of Processor returned.
|
||||
|
|
@ -201,7 +201,7 @@ SetIpiSentByApFlag (
|
|||
|
||||
**/
|
||||
UINT32
|
||||
FindCpuNotRunning (
|
||||
FindNextPendingBreakCpu (
|
||||
VOID
|
||||
);
|
||||
|
||||
|
|
@ -217,5 +217,21 @@ IsAllCpuRunning (
|
|||
VOID
|
||||
);
|
||||
|
||||
/**
|
||||
Check if the current processor is the first breaking processor.
|
||||
|
||||
If yes, halt other processors.
|
||||
|
||||
@param[in] ProcessorIndex Processor index value.
|
||||
|
||||
@return TRUE This processor is the first breaking processor.
|
||||
@return FALSE This processor is not the first breaking processor.
|
||||
|
||||
**/
|
||||
BOOLEAN
|
||||
IsFirstBreakProcessor (
|
||||
IN UINT32 ProcessorIndex
|
||||
);
|
||||
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/** @file
|
||||
Public include file for Debug Port Library.
|
||||
Supporting functions for IA32 architecture.
|
||||
|
||||
Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
|
||||
Copyright (c) 2010 - 2012, Intel Corporation. All rights reserved.<BR>
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
|
|
@ -14,188 +14,6 @@
|
|||
|
||||
#include "DebugAgent.h"
|
||||
|
||||
/**
|
||||
Read the offset of FP / MMX / XMM registers by register index.
|
||||
|
||||
@param[in] Index Register index.
|
||||
@param[out] Width Register width returned.
|
||||
|
||||
@return Offset in register address range.
|
||||
|
||||
**/
|
||||
UINT16
|
||||
ArchReadFxStatOffset (
|
||||
IN UINT8 Index,
|
||||
OUT UINT8 *Width
|
||||
)
|
||||
{
|
||||
if (Index < SOFT_DEBUGGER_REGISTER_ST0) {
|
||||
switch (Index) {
|
||||
case SOFT_DEBUGGER_REGISTER_FP_FCW:
|
||||
*Width = (UINT8) sizeof (UINT16);
|
||||
return (UINT16)OFFSET_OF(DEBUG_DATA_IA32_FX_SAVE_STATE, Fcw);
|
||||
|
||||
case SOFT_DEBUGGER_REGISTER_FP_FSW:
|
||||
*Width = (UINT8) sizeof (UINT16);
|
||||
return (UINT16)OFFSET_OF(DEBUG_DATA_IA32_FX_SAVE_STATE, Fsw);
|
||||
|
||||
case SOFT_DEBUGGER_REGISTER_FP_FTW:
|
||||
*Width = (UINT8) sizeof (UINT16);
|
||||
return (UINT16)OFFSET_OF(DEBUG_DATA_IA32_FX_SAVE_STATE, Ftw);
|
||||
|
||||
case SOFT_DEBUGGER_REGISTER_FP_OPCODE:
|
||||
*Width = (UINT8) sizeof (UINT16);
|
||||
return (UINT16)OFFSET_OF(DEBUG_DATA_IA32_FX_SAVE_STATE, Opcode);
|
||||
|
||||
case SOFT_DEBUGGER_REGISTER_FP_EIP:
|
||||
*Width = (UINT8) sizeof (UINTN);
|
||||
return (UINT16)OFFSET_OF(DEBUG_DATA_IA32_FX_SAVE_STATE, Eip);
|
||||
|
||||
case SOFT_DEBUGGER_REGISTER_FP_CS:
|
||||
*Width = (UINT8) sizeof (UINT16);
|
||||
return (UINT16)OFFSET_OF(DEBUG_DATA_IA32_FX_SAVE_STATE, Cs);
|
||||
|
||||
case SOFT_DEBUGGER_REGISTER_FP_DATAOFFSET:
|
||||
*Width = (UINT8) sizeof (UINTN);
|
||||
return (UINT16)OFFSET_OF(DEBUG_DATA_IA32_FX_SAVE_STATE, DataOffset);
|
||||
|
||||
case SOFT_DEBUGGER_REGISTER_FP_DS:
|
||||
*Width = (UINT8) sizeof (UINT16);
|
||||
return (UINT16)OFFSET_OF(DEBUG_DATA_IA32_FX_SAVE_STATE, Ds);
|
||||
|
||||
case SOFT_DEBUGGER_REGISTER_FP_MXCSR:
|
||||
*Width = (UINT8) sizeof (UINTN);
|
||||
return (UINT16)OFFSET_OF(DEBUG_DATA_IA32_FX_SAVE_STATE, Mxcsr);
|
||||
|
||||
case SOFT_DEBUGGER_REGISTER_FP_MXCSR_MASK:
|
||||
*Width = (UINT8) sizeof (UINTN);
|
||||
return (UINT16)OFFSET_OF(DEBUG_DATA_IA32_FX_SAVE_STATE, Mxcsr_Mask);
|
||||
}
|
||||
}
|
||||
|
||||
if (Index < SOFT_DEBUGGER_REGISTER_XMM0) {
|
||||
*Width = 10;
|
||||
} else if (Index < SOFT_DEBUGGER_REGISTER_MM0 ) {
|
||||
*Width = 16;
|
||||
} else {
|
||||
*Width = 8;
|
||||
Index -= SOFT_DEBUGGER_REGISTER_MM0 - SOFT_DEBUGGER_REGISTER_ST0;
|
||||
}
|
||||
|
||||
return (UINT16)(OFFSET_OF(DEBUG_DATA_IA32_FX_SAVE_STATE, St0Mm0) + (Index - SOFT_DEBUGGER_REGISTER_ST0) * 16);
|
||||
}
|
||||
|
||||
/**
|
||||
Write specified register into save CPU context.
|
||||
|
||||
@param[in] CpuContext Pointer to saved CPU context.
|
||||
@param[in] Index Register index value.
|
||||
@param[in] Offset Offset in register address range.
|
||||
@param[in] Width Data width to read.
|
||||
@param[in] RegisterBuffer Pointer to input buffer with data.
|
||||
|
||||
**/
|
||||
VOID
|
||||
ArchWriteRegisterBuffer (
|
||||
IN DEBUG_CPU_CONTEXT *CpuContext,
|
||||
IN UINT8 Index,
|
||||
IN UINT8 Offset,
|
||||
IN UINT8 Width,
|
||||
IN UINT8 *RegisterBuffer
|
||||
)
|
||||
{
|
||||
UINT8 *Buffer;
|
||||
if (Index < SOFT_DEBUGGER_REGISTER_FP_BASE) {
|
||||
Buffer = (UINT8 *) CpuContext + sizeof (DEBUG_DATA_IA32_FX_SAVE_STATE) + Index * 4;
|
||||
} else {
|
||||
//
|
||||
// If it is MMX register, adjust its index position
|
||||
//
|
||||
if (Index >= SOFT_DEBUGGER_REGISTER_MM0) {
|
||||
Index -= SOFT_DEBUGGER_REGISTER_MM0 - SOFT_DEBUGGER_REGISTER_ST0;
|
||||
}
|
||||
//
|
||||
// FPU/MMX/XMM registers
|
||||
//
|
||||
Buffer = (UINT8 *) CpuContext + ArchReadFxStatOffset (Index, &Width);
|
||||
}
|
||||
|
||||
CopyMem (Buffer + Offset, RegisterBuffer, Width);
|
||||
}
|
||||
|
||||
/**
|
||||
Read register value from saved CPU context.
|
||||
|
||||
@param[in] CpuContext Pointer to saved CPU context.
|
||||
@param[in] Index Register index value.
|
||||
@param[in] Offset Offset in register address range
|
||||
@param[in] Width Data width to read.
|
||||
|
||||
@return The address of register value.
|
||||
|
||||
**/
|
||||
UINT8 *
|
||||
ArchReadRegisterBuffer (
|
||||
IN DEBUG_CPU_CONTEXT *CpuContext,
|
||||
IN UINT8 Index,
|
||||
IN UINT8 Offset,
|
||||
IN UINT8 *Width
|
||||
)
|
||||
{
|
||||
UINT8 *Buffer;
|
||||
|
||||
if (Index < SOFT_DEBUGGER_REGISTER_FP_BASE) {
|
||||
Buffer = (UINT8 *) CpuContext + sizeof (DEBUG_DATA_IA32_FX_SAVE_STATE) + Index * 4;
|
||||
if (*Width == 0) {
|
||||
*Width = (UINT8) sizeof (UINTN);
|
||||
}
|
||||
} else {
|
||||
//
|
||||
// FPU/MMX/XMM registers
|
||||
//
|
||||
Buffer = (UINT8 *) CpuContext + ArchReadFxStatOffset (Index, Width);
|
||||
}
|
||||
|
||||
return Buffer;
|
||||
}
|
||||
|
||||
/**
|
||||
Read group register of common registers.
|
||||
|
||||
@param[in] CpuContext Pointer to saved CPU context.
|
||||
@param[in] RegisterGroup Pointer to Group registers.
|
||||
|
||||
**/
|
||||
VOID
|
||||
ReadRegisterGroup (
|
||||
IN DEBUG_CPU_CONTEXT *CpuContext,
|
||||
IN DEBUG_DATA_REPONSE_READ_REGISTER_GROUP *RegisterGroup
|
||||
)
|
||||
{
|
||||
RegisterGroup->Cs = (UINT16) CpuContext->Cs;
|
||||
RegisterGroup->Ds = (UINT16) CpuContext->Ds;
|
||||
RegisterGroup->Es = (UINT16) CpuContext->Es;
|
||||
RegisterGroup->Fs = (UINT16) CpuContext->Fs;
|
||||
RegisterGroup->Gs = (UINT16) CpuContext->Gs;
|
||||
RegisterGroup->Ss = (UINT16) CpuContext->Ss;
|
||||
RegisterGroup->Eflags = CpuContext->Eflags;
|
||||
RegisterGroup->Ebp = CpuContext->Ebp;
|
||||
RegisterGroup->Eip = CpuContext->Eip;
|
||||
RegisterGroup->Esp = CpuContext->Esp;
|
||||
RegisterGroup->Eax = CpuContext->Eax;
|
||||
RegisterGroup->Ebx = CpuContext->Ebx;
|
||||
RegisterGroup->Ecx = CpuContext->Ecx;
|
||||
RegisterGroup->Edx = CpuContext->Edx;
|
||||
RegisterGroup->Esi = CpuContext->Esi;
|
||||
RegisterGroup->Edi = CpuContext->Edi;
|
||||
RegisterGroup->Dr0 = CpuContext->Dr0;
|
||||
RegisterGroup->Dr1 = CpuContext->Dr1;
|
||||
RegisterGroup->Dr2 = CpuContext->Dr2;
|
||||
RegisterGroup->Dr3 = CpuContext->Dr3;
|
||||
RegisterGroup->Dr6 = CpuContext->Dr6;
|
||||
RegisterGroup->Dr7 = CpuContext->Dr7;
|
||||
}
|
||||
|
||||
/**
|
||||
Initialize IDT entries to support source level debug.
|
||||
|
||||
|
|
@ -237,6 +55,11 @@ InitializeDebugIdt (
|
|||
InterruptHandler = (UINTN) &TimerInterruptHandle;
|
||||
IdtEntry[DEBUG_TIMER_VECTOR].Bits.OffsetLow = (UINT16)(UINTN)InterruptHandler;
|
||||
IdtEntry[DEBUG_TIMER_VECTOR].Bits.OffsetHigh = (UINT16)((UINTN)InterruptHandler >> 16);
|
||||
IdtEntry[Index].Bits.Selector = CodeSegment;
|
||||
IdtEntry[Index].Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32;
|
||||
IdtEntry[DEBUG_TIMER_VECTOR].Bits.Selector = CodeSegment;
|
||||
IdtEntry[DEBUG_TIMER_VECTOR].Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32;
|
||||
|
||||
//
|
||||
// Set DE flag in CR4 to enable IO breakpoint
|
||||
//
|
||||
AsmWriteCr4 (AsmReadCr4 () | BIT3);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/** @file
|
||||
IA32 specific defintions for debug agent library instance.
|
||||
|
||||
Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
|
||||
Copyright (c) 2010 - 2012, Intel Corporation. All rights reserved.<BR>
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
|
|
@ -15,17 +15,13 @@
|
|||
#ifndef _ARCH_DEBUG_SUPPORT_H_
|
||||
#define _ARCH_DEBUG_SUPPORT_H_
|
||||
|
||||
#include "ArchRegisters.h"
|
||||
#include "ProcessorContext.h"
|
||||
#include "TransferProtocol.h"
|
||||
|
||||
typedef DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_IA32 DEBUG_DATA_REPONSE_READ_REGISTER_GROUP;
|
||||
typedef DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGLIM_IA32 DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGLIM;
|
||||
typedef DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGBASE_IA32 DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGBASE;
|
||||
|
||||
#define DEBUG_SW_BREAKPOINT_SYMBOL 0xcc
|
||||
|
||||
#define DEBUG_ARCH_SYMBOL DEBUG_DATA_BREAK_CPU_ARCH_IA32
|
||||
|
||||
typedef DEBUG_DATA_IA32_FX_SAVE_STATE DEBUG_DATA_FX_SAVE_STATE;
|
||||
typedef DEBUG_DATA_IA32_SYSTEM_CONTEXT DEBUG_CPU_CONTEXT;
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,210 +0,0 @@
|
|||
/** @file
|
||||
IA32 Group registers read support functions.
|
||||
|
||||
Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#include "DebugAgent.h"
|
||||
|
||||
/**
|
||||
Read group register of Segment Base.
|
||||
|
||||
@param[in] CpuContext Pointer to saved CPU context.
|
||||
@param[in] RegisterGroupSegBase Pointer to Group registers.
|
||||
|
||||
**/
|
||||
VOID
|
||||
ReadRegisterGroupSegBase (
|
||||
IN DEBUG_CPU_CONTEXT *CpuContext,
|
||||
IN DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGBASE *RegisterGroupSegBase
|
||||
)
|
||||
{
|
||||
IA32_DESCRIPTOR *Ia32Descriptor;
|
||||
IA32_GDT *Ia32Gdt;
|
||||
UINTN Index;
|
||||
|
||||
Ia32Descriptor = (IA32_DESCRIPTOR *) CpuContext->Gdtr;
|
||||
Ia32Gdt = (IA32_GDT *) (Ia32Descriptor->Base);
|
||||
|
||||
Index = CpuContext->Cs / 8;
|
||||
RegisterGroupSegBase->CsBas = (Ia32Gdt[Index].Bits.BaseLow) + (Ia32Gdt[Index].Bits.BaseMid << 16) + (Ia32Gdt[Index].Bits.BaseMid << 24);
|
||||
Index = CpuContext->Ss / 8;
|
||||
RegisterGroupSegBase->SsBas = (Ia32Gdt[Index].Bits.BaseLow) + (Ia32Gdt[Index].Bits.BaseMid << 16) + (Ia32Gdt[Index].Bits.BaseMid << 24);
|
||||
Index = CpuContext->Gs / 8;
|
||||
RegisterGroupSegBase->GsBas = (Ia32Gdt[Index].Bits.BaseLow) + (Ia32Gdt[Index].Bits.BaseMid << 16) + (Ia32Gdt[Index].Bits.BaseMid << 24);
|
||||
Index = CpuContext->Fs / 8;
|
||||
RegisterGroupSegBase->FsBas = (Ia32Gdt[Index].Bits.BaseLow) + (Ia32Gdt[Index].Bits.BaseMid << 16) + (Ia32Gdt[Index].Bits.BaseMid << 24);
|
||||
Index = CpuContext->Es / 8;
|
||||
RegisterGroupSegBase->EsBas = (Ia32Gdt[Index].Bits.BaseLow) + (Ia32Gdt[Index].Bits.BaseMid << 16) + (Ia32Gdt[Index].Bits.BaseMid << 24);
|
||||
Index = CpuContext->Ds / 8;
|
||||
RegisterGroupSegBase->DsBas = (Ia32Gdt[Index].Bits.BaseLow) + (Ia32Gdt[Index].Bits.BaseMid << 16) + (Ia32Gdt[Index].Bits.BaseMid << 24);
|
||||
|
||||
RegisterGroupSegBase->LdtBas = 0;
|
||||
RegisterGroupSegBase->TssBas = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
Read gourp register of Segment Limit.
|
||||
|
||||
@param[in] CpuContext Pointer to saved CPU context.
|
||||
@param[in] RegisterGroupSegLim Pointer to Group registers.
|
||||
|
||||
**/
|
||||
VOID
|
||||
ReadRegisterGroupSegLim (
|
||||
IN DEBUG_CPU_CONTEXT *CpuContext,
|
||||
IN DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGLIM *RegisterGroupSegLim
|
||||
)
|
||||
{
|
||||
IA32_DESCRIPTOR *Ia32Descriptor;
|
||||
IA32_GDT *Ia32Gdt;
|
||||
UINTN Index;
|
||||
|
||||
Ia32Descriptor = (IA32_DESCRIPTOR *) CpuContext->Gdtr;
|
||||
Ia32Gdt = (IA32_GDT *) (Ia32Descriptor->Base);
|
||||
|
||||
Index = CpuContext->Cs / 8;
|
||||
RegisterGroupSegLim->CsLim = Ia32Gdt[Index].Bits.LimitLow + (Ia32Gdt[Index].Bits.LimitHigh << 16);
|
||||
if (Ia32Gdt[Index].Bits.Granularity == 1) {
|
||||
RegisterGroupSegLim->CsLim = (RegisterGroupSegLim->CsLim << 12) | 0xfff;
|
||||
}
|
||||
|
||||
Index = CpuContext->Ss / 8;
|
||||
RegisterGroupSegLim->SsLim = Ia32Gdt[Index].Bits.LimitLow + (Ia32Gdt[Index].Bits.LimitHigh << 16);
|
||||
if (Ia32Gdt[Index].Bits.Granularity == 1) {
|
||||
RegisterGroupSegLim->SsLim = (RegisterGroupSegLim->SsLim << 12) | 0xfff;
|
||||
}
|
||||
|
||||
Index = CpuContext->Gs / 8;
|
||||
RegisterGroupSegLim->GsLim = Ia32Gdt[Index].Bits.LimitLow + (Ia32Gdt[Index].Bits.LimitHigh << 16);
|
||||
if (Ia32Gdt[Index].Bits.Granularity == 1) {
|
||||
RegisterGroupSegLim->GsLim = (RegisterGroupSegLim->GsLim << 12) | 0xfff;
|
||||
}
|
||||
|
||||
Index = CpuContext->Fs / 8;
|
||||
RegisterGroupSegLim->FsLim = Ia32Gdt[Index].Bits.LimitLow + (Ia32Gdt[Index].Bits.LimitHigh << 16);
|
||||
if (Ia32Gdt[Index].Bits.Granularity == 1) {
|
||||
RegisterGroupSegLim->FsLim = (RegisterGroupSegLim->FsLim << 12) | 0xfff;
|
||||
}
|
||||
|
||||
Index = CpuContext->Es / 8;
|
||||
RegisterGroupSegLim->EsLim = Ia32Gdt[Index].Bits.LimitLow + (Ia32Gdt[Index].Bits.LimitHigh << 16);
|
||||
if (Ia32Gdt[Index].Bits.Granularity == 1) {
|
||||
RegisterGroupSegLim->EsLim = (RegisterGroupSegLim->EsLim << 12) | 0xfff;
|
||||
}
|
||||
|
||||
Index = CpuContext->Ds / 8;
|
||||
RegisterGroupSegLim->DsLim = Ia32Gdt[Index].Bits.LimitLow + (Ia32Gdt[Index].Bits.LimitHigh << 16);
|
||||
if (Ia32Gdt[Index].Bits.Granularity == 1) {
|
||||
RegisterGroupSegLim->DsLim = (RegisterGroupSegLim->DsLim << 12) | 0xfff;
|
||||
}
|
||||
|
||||
RegisterGroupSegLim->LdtLim = 0xffff;
|
||||
RegisterGroupSegLim->TssLim = 0xffff;
|
||||
}
|
||||
|
||||
/**
|
||||
Read group register by group index.
|
||||
|
||||
@param[in] CpuContext Pointer to saved CPU context.
|
||||
@param[in] GroupIndex Group Index.
|
||||
|
||||
@retval RETURN_SUCCESS Read successfully.
|
||||
@retval RETURN_NOT_SUPPORTED Group index cannot be supported.
|
||||
|
||||
**/
|
||||
RETURN_STATUS
|
||||
ArchReadRegisterGroup (
|
||||
IN DEBUG_CPU_CONTEXT *CpuContext,
|
||||
IN UINT8 GroupIndex
|
||||
)
|
||||
{
|
||||
DEBUG_DATA_REPONSE_READ_REGISTER_GROUP RegisterGroup;
|
||||
DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGLIM RegisterGroupSegLim;
|
||||
DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGBASE RegisterGroupSegBase;
|
||||
|
||||
switch (GroupIndex) {
|
||||
case SOFT_DEBUGGER_REGISTER_GROUP_GPDRS32:
|
||||
ReadRegisterGroup (CpuContext, &RegisterGroup);
|
||||
SendDataResponsePacket (CpuContext, (UINT8 *) &RegisterGroup, (UINT16) sizeof (DEBUG_DATA_REPONSE_READ_REGISTER_GROUP));
|
||||
break;
|
||||
|
||||
case SOFT_DEBUGGER_REGISTER_GROUP_SEGMENT_LIMITS32:
|
||||
ReadRegisterGroupSegLim (CpuContext, &RegisterGroupSegLim);
|
||||
SendDataResponsePacket (CpuContext, (UINT8 *) &RegisterGroupSegLim, (UINT16) sizeof (DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGLIM));
|
||||
break;
|
||||
|
||||
case SOFT_DEBUGGER_REGISTER_GROUP_SEGMENT_BASES32:
|
||||
ReadRegisterGroupSegBase (CpuContext, &RegisterGroupSegBase);
|
||||
SendDataResponsePacket (CpuContext, (UINT8 *) &RegisterGroupSegBase, (UINT16) sizeof (DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGBASE));
|
||||
break;
|
||||
|
||||
default:
|
||||
return RETURN_UNSUPPORTED;
|
||||
}
|
||||
|
||||
return RETURN_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
Read segment selector by register index.
|
||||
|
||||
@param[in] CpuContext Pointer to saved CPU context.
|
||||
@param[in] RegisterIndex Register Index.
|
||||
|
||||
@return Value of segment selector.
|
||||
|
||||
**/
|
||||
UINT64
|
||||
ReadRegisterSelectorByIndex (
|
||||
IN DEBUG_CPU_CONTEXT *CpuContext,
|
||||
IN UINT8 RegisterIndex
|
||||
)
|
||||
{
|
||||
IA32_DESCRIPTOR *Ia32Descriptor;
|
||||
IA32_GDT *Ia32Gdt;
|
||||
UINT16 Selector;
|
||||
UINT32 Data32;
|
||||
|
||||
Ia32Descriptor = (IA32_DESCRIPTOR *) CpuContext->Gdtr;
|
||||
Ia32Gdt = (IA32_GDT *) (Ia32Descriptor->Base);
|
||||
|
||||
Selector = 0;
|
||||
|
||||
switch (RegisterIndex) {
|
||||
case SOFT_DEBUGGER_REGISTER_CSAS:
|
||||
Selector = (UINT16) CpuContext->Cs;
|
||||
break;
|
||||
case SOFT_DEBUGGER_REGISTER_SSAS:
|
||||
Selector = (UINT16) CpuContext->Ss;
|
||||
break;
|
||||
case SOFT_DEBUGGER_REGISTER_GSAS:
|
||||
Selector = (UINT16) CpuContext->Gs;
|
||||
break;
|
||||
case SOFT_DEBUGGER_REGISTER_FSAS:
|
||||
Selector = (UINT16) CpuContext->Fs;
|
||||
break;
|
||||
case SOFT_DEBUGGER_REGISTER_ESAS:
|
||||
Selector = (UINT16) CpuContext->Es;
|
||||
break;
|
||||
case SOFT_DEBUGGER_REGISTER_DSAS:
|
||||
Selector = (UINT16) CpuContext->Ds;
|
||||
case SOFT_DEBUGGER_REGISTER_LDTAS:
|
||||
case SOFT_DEBUGGER_REGISTER_TSSAS:
|
||||
return 0x00820000;
|
||||
break;
|
||||
}
|
||||
|
||||
Data32 = (UINT32) RShiftU64 (Ia32Gdt[Selector / 8].Uint64, 24);
|
||||
return (Data32 & (UINT32)(~0xff)) | Selector;
|
||||
|
||||
}
|
||||
|
||||
|
|
@ -1,160 +0,0 @@
|
|||
/** @file
|
||||
IA32 register defintions needed by debug transfer protocol.
|
||||
|
||||
Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef _ARCH_REGISTERS_H_
|
||||
#define _ARCH_REGISTERS_H_
|
||||
|
||||
#pragma pack(1)
|
||||
|
||||
///
|
||||
/// FXSAVE_STATE
|
||||
/// FP / MMX / XMM registers (see fxrstor instruction definition)
|
||||
///
|
||||
typedef struct {
|
||||
UINT16 Fcw;
|
||||
UINT16 Fsw;
|
||||
UINT16 Ftw;
|
||||
UINT16 Opcode;
|
||||
UINT32 Eip;
|
||||
UINT16 Cs;
|
||||
UINT16 Reserved1;
|
||||
UINT32 DataOffset;
|
||||
UINT16 Ds;
|
||||
UINT8 Reserved2[2];
|
||||
UINT32 Mxcsr;
|
||||
UINT32 Mxcsr_Mask;
|
||||
UINT8 St0Mm0[10];
|
||||
UINT8 Reserved3[6];
|
||||
UINT8 St1Mm1[10];
|
||||
UINT8 Reserved4[6];
|
||||
UINT8 St2Mm2[10];
|
||||
UINT8 Reserved5[6];
|
||||
UINT8 St3Mm3[10];
|
||||
UINT8 Reserved6[6];
|
||||
UINT8 St4Mm4[10];
|
||||
UINT8 Reserved7[6];
|
||||
UINT8 St5Mm5[10];
|
||||
UINT8 Reserved8[6];
|
||||
UINT8 St6Mm6[10];
|
||||
UINT8 Reserved9[6];
|
||||
UINT8 St7Mm7[10];
|
||||
UINT8 Reserved10[6];
|
||||
UINT8 Xmm0[16];
|
||||
UINT8 Xmm1[16];
|
||||
UINT8 Xmm2[16];
|
||||
UINT8 Xmm3[16];
|
||||
UINT8 Xmm4[16];
|
||||
UINT8 Xmm5[16];
|
||||
UINT8 Xmm6[16];
|
||||
UINT8 Xmm7[16];
|
||||
UINT8 Reserved11[14 * 16];
|
||||
} DEBUG_DATA_IA32_FX_SAVE_STATE;
|
||||
|
||||
///
|
||||
/// IA-32 processor context definition
|
||||
///
|
||||
typedef struct {
|
||||
DEBUG_DATA_IA32_FX_SAVE_STATE FxSaveState;
|
||||
UINT32 Dr0;
|
||||
UINT32 Dr1;
|
||||
UINT32 Dr2;
|
||||
UINT32 Dr3;
|
||||
UINT32 Dr6;
|
||||
UINT32 Dr7;
|
||||
UINT32 Eflags;
|
||||
UINT32 Ldtr;
|
||||
UINT32 Tr;
|
||||
UINT32 Gdtr[2];
|
||||
UINT32 Idtr[2];
|
||||
UINT32 Eip;
|
||||
UINT32 Gs;
|
||||
UINT32 Fs;
|
||||
UINT32 Es;
|
||||
UINT32 Ds;
|
||||
UINT32 Cs;
|
||||
UINT32 Ss;
|
||||
UINT32 Cr0;
|
||||
UINT32 Cr1; ///< Reserved
|
||||
UINT32 Cr2;
|
||||
UINT32 Cr3;
|
||||
UINT32 Cr4;
|
||||
UINT32 Edi;
|
||||
UINT32 Esi;
|
||||
UINT32 Ebp;
|
||||
UINT32 Esp;
|
||||
UINT32 Edx;
|
||||
UINT32 Ecx;
|
||||
UINT32 Ebx;
|
||||
UINT32 Eax;
|
||||
} DEBUG_DATA_IA32_SYSTEM_CONTEXT;
|
||||
|
||||
///
|
||||
/// IA32 GROUP register
|
||||
///
|
||||
typedef struct {
|
||||
UINT16 Cs;
|
||||
UINT16 Ds;
|
||||
UINT16 Es;
|
||||
UINT16 Fs;
|
||||
UINT16 Gs;
|
||||
UINT16 Ss;
|
||||
UINT32 Eflags;
|
||||
UINT32 Ebp;
|
||||
UINT32 Eip;
|
||||
UINT32 Esp;
|
||||
UINT32 Eax;
|
||||
UINT32 Ebx;
|
||||
UINT32 Ecx;
|
||||
UINT32 Edx;
|
||||
UINT32 Esi;
|
||||
UINT32 Edi;
|
||||
UINT32 Dr0;
|
||||
UINT32 Dr1;
|
||||
UINT32 Dr2;
|
||||
UINT32 Dr3;
|
||||
UINT32 Dr6;
|
||||
UINT32 Dr7;
|
||||
} DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_IA32;
|
||||
|
||||
///
|
||||
/// IA32 Segment Limit GROUP register
|
||||
///
|
||||
typedef struct {
|
||||
UINT32 CsLim;
|
||||
UINT32 SsLim;
|
||||
UINT32 GsLim;
|
||||
UINT32 FsLim;
|
||||
UINT32 EsLim;
|
||||
UINT32 DsLim;
|
||||
UINT32 LdtLim;
|
||||
UINT32 TssLim;
|
||||
} DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGLIM_IA32;
|
||||
|
||||
///
|
||||
/// IA32 Segment Base GROUP register
|
||||
///
|
||||
typedef struct {
|
||||
UINT32 CsBas;
|
||||
UINT32 SsBas;
|
||||
UINT32 GsBas;
|
||||
UINT32 FsBas;
|
||||
UINT32 EsBas;
|
||||
UINT32 DsBas;
|
||||
UINT32 LdtBas;
|
||||
UINT32 TssBas;
|
||||
} DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGBASE_IA32;
|
||||
|
||||
#pragma pack()
|
||||
|
||||
#endif
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
#------------------------------------------------------------------------------
|
||||
#
|
||||
# Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
|
||||
# Copyright (c) 2010 - 2012, Intel Corporation. All rights reserved.<BR>
|
||||
# This program and the accompanying materials
|
||||
# are licensed and made available under the terms and conditions of the BSD License
|
||||
# which accompanies this distribution. The full text of the license may be found at
|
||||
|
|
@ -281,6 +281,9 @@ NoExtrPush:
|
|||
movl %esp,%edi
|
||||
.byte 0x0f, 0xae, 0x07 # fxsave [edi]
|
||||
|
||||
## save the exception data
|
||||
pushl 8(%esp)
|
||||
|
||||
## Clear Direction Flag
|
||||
cld
|
||||
|
||||
|
|
@ -290,6 +293,9 @@ NoExtrPush:
|
|||
call ASM_PFX(InterruptProcess)
|
||||
addl $8,%esp
|
||||
|
||||
## skip the exception data
|
||||
addl $4,%esp
|
||||
|
||||
## FX_SAVE_STATE_IA32 FxSaveState;
|
||||
movl %esp,%esi
|
||||
.byte 0x0f, 0xae, 0x0e # fxrstor [esi]
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
;------------------------------------------------------------------------------
|
||||
;
|
||||
; Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
|
||||
; Copyright (c) 2010 - 2012, Intel Corporation. All rights reserved.<BR>
|
||||
; This program and the accompanying materials
|
||||
; are licensed and made available under the terms and conditions of the BSD License
|
||||
; which accompanies this distribution. The full text of the license may be found at
|
||||
|
|
@ -283,6 +283,9 @@ NoExtrPush:
|
|||
mov edi, esp
|
||||
db 0fh, 0aeh, 00000111y ;fxsave [edi]
|
||||
|
||||
;; save the exception data
|
||||
push dword ptr [ebp + 8]
|
||||
|
||||
;; Clear Direction Flag
|
||||
cld
|
||||
|
||||
|
|
@ -292,6 +295,9 @@ NoExtrPush:
|
|||
call InterruptProcess
|
||||
add esp, 8
|
||||
|
||||
; skip the exception data
|
||||
add esp, 4
|
||||
|
||||
;; FX_SAVE_STATE_IA32 FxSaveState;
|
||||
mov esi, esp
|
||||
db 0fh, 0aeh, 00001110y ; fxrstor [esi]
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/** @file
|
||||
Supporting functions for x64 architecture.
|
||||
Supporting functions for X64 architecture.
|
||||
|
||||
Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
|
||||
Copyright (c) 2010 - 2012, Intel Corporation. All rights reserved.<BR>
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
|
|
@ -14,199 +14,6 @@
|
|||
|
||||
#include "DebugAgent.h"
|
||||
|
||||
/**
|
||||
Read the offset of FP / MMX / XMM registers by register index.
|
||||
|
||||
@param[in] Index Register index.
|
||||
@param[out] Width Register width returned.
|
||||
|
||||
@return Offset in register address range.
|
||||
|
||||
**/
|
||||
UINT16
|
||||
ArchReadFxStatOffset (
|
||||
IN UINT8 Index,
|
||||
OUT UINT8 *Width
|
||||
)
|
||||
{
|
||||
if (Index < SOFT_DEBUGGER_REGISTER_ST0) {
|
||||
switch (Index) {
|
||||
case SOFT_DEBUGGER_REGISTER_FP_FCW:
|
||||
*Width = (UINT8) sizeof (UINT16);
|
||||
return OFFSET_OF(DEBUG_DATA_X64_FX_SAVE_STATE, Fcw);
|
||||
|
||||
case SOFT_DEBUGGER_REGISTER_FP_FSW:
|
||||
*Width = (UINT8) sizeof (UINT16);
|
||||
return OFFSET_OF(DEBUG_DATA_X64_FX_SAVE_STATE, Fsw);
|
||||
|
||||
case SOFT_DEBUGGER_REGISTER_FP_FTW:
|
||||
*Width = (UINT8) sizeof (UINT16);
|
||||
return OFFSET_OF(DEBUG_DATA_X64_FX_SAVE_STATE, Ftw);
|
||||
|
||||
case SOFT_DEBUGGER_REGISTER_FP_OPCODE:
|
||||
*Width = (UINT8) sizeof (UINT16);
|
||||
return OFFSET_OF(DEBUG_DATA_X64_FX_SAVE_STATE, Opcode);
|
||||
|
||||
case SOFT_DEBUGGER_REGISTER_FP_EIP:
|
||||
*Width = (UINT8) sizeof (UINTN);
|
||||
return OFFSET_OF(DEBUG_DATA_X64_FX_SAVE_STATE, Rip);
|
||||
|
||||
case SOFT_DEBUGGER_REGISTER_FP_DATAOFFSET:
|
||||
*Width = (UINT8) sizeof (UINTN);
|
||||
return OFFSET_OF(DEBUG_DATA_X64_FX_SAVE_STATE, DataOffset);
|
||||
|
||||
case SOFT_DEBUGGER_REGISTER_FP_MXCSR:
|
||||
*Width = (UINT8) sizeof (UINT32);
|
||||
return OFFSET_OF(DEBUG_DATA_X64_FX_SAVE_STATE, Mxcsr);
|
||||
|
||||
case SOFT_DEBUGGER_REGISTER_FP_MXCSR_MASK:
|
||||
*Width = (UINT8) sizeof (UINT32);
|
||||
return OFFSET_OF(DEBUG_DATA_X64_FX_SAVE_STATE, Mxcsr_Mask);
|
||||
|
||||
default:
|
||||
return (UINT16) (-1);
|
||||
}
|
||||
}
|
||||
|
||||
if (Index < SOFT_DEBUGGER_REGISTER_XMM0) {
|
||||
*Width = 10;
|
||||
} else if (Index < SOFT_DEBUGGER_REGISTER_MM0 ) {
|
||||
*Width = 16;
|
||||
} else {
|
||||
*Width = 8;
|
||||
Index -= SOFT_DEBUGGER_REGISTER_MM0 - SOFT_DEBUGGER_REGISTER_ST0;
|
||||
}
|
||||
|
||||
return OFFSET_OF(DEBUG_DATA_X64_FX_SAVE_STATE, St0Mm0) + (Index - SOFT_DEBUGGER_REGISTER_ST0) * 16;
|
||||
}
|
||||
|
||||
/**
|
||||
Write specified register into save CPU context.
|
||||
|
||||
@param[in] CpuContext Pointer to saved CPU context.
|
||||
@param[in] Index Register index value.
|
||||
@param[in] Offset Offset in register address range
|
||||
@param[in] Width Data width to read.
|
||||
@param[in] RegisterBuffer Pointer to input buffer with data.
|
||||
|
||||
**/
|
||||
VOID
|
||||
ArchWriteRegisterBuffer (
|
||||
IN DEBUG_CPU_CONTEXT *CpuContext,
|
||||
IN UINT8 Index,
|
||||
IN UINT8 Offset,
|
||||
IN UINT8 Width,
|
||||
IN UINT8 *RegisterBuffer
|
||||
)
|
||||
{
|
||||
UINT8 *Buffer;
|
||||
if (Index < SOFT_DEBUGGER_REGISTER_FP_BASE) {
|
||||
Buffer = (UINT8 *) CpuContext + sizeof (DEBUG_DATA_X64_FX_SAVE_STATE) + Index * 8;
|
||||
} else {
|
||||
//
|
||||
// If it is MMX register, adjust its index position
|
||||
//
|
||||
if (Index >= SOFT_DEBUGGER_REGISTER_MM0) {
|
||||
Index -= SOFT_DEBUGGER_REGISTER_MM0 - SOFT_DEBUGGER_REGISTER_ST0;
|
||||
}
|
||||
|
||||
//
|
||||
// FPU/MMX/XMM registers
|
||||
//
|
||||
Buffer = (UINT8 *) CpuContext + ArchReadFxStatOffset (Index, &Width);
|
||||
}
|
||||
|
||||
CopyMem (Buffer + Offset, RegisterBuffer, Width);
|
||||
}
|
||||
|
||||
/**
|
||||
Read register value from saved CPU context.
|
||||
|
||||
@param[in] CpuContext Pointer to saved CPU context.
|
||||
@param[in] Index Register index value.
|
||||
@param[in] Offset Offset in register address range
|
||||
@param[in] Width Data width to read.
|
||||
|
||||
@return The address of register value.
|
||||
|
||||
**/
|
||||
UINT8 *
|
||||
ArchReadRegisterBuffer (
|
||||
IN DEBUG_CPU_CONTEXT *CpuContext,
|
||||
IN UINT8 Index,
|
||||
IN UINT8 Offset,
|
||||
IN UINT8 *Width
|
||||
)
|
||||
{
|
||||
UINT8 *Buffer;
|
||||
|
||||
if (Index < SOFT_DEBUGGER_REGISTER_FP_BASE) {
|
||||
Buffer = (UINT8 *) CpuContext + sizeof (DEBUG_DATA_X64_FX_SAVE_STATE) + Index * 8;
|
||||
if (*Width == 0) {
|
||||
*Width = (UINT8) sizeof (UINTN);
|
||||
}
|
||||
} else {
|
||||
//
|
||||
// FPU/MMX/XMM registers
|
||||
//
|
||||
Buffer = (UINT8 *) CpuContext + ArchReadFxStatOffset (Index, Width);
|
||||
}
|
||||
|
||||
return Buffer;
|
||||
}
|
||||
|
||||
/**
|
||||
Read group register of common registers.
|
||||
|
||||
@param[in] CpuContext Pointer to saved CPU context.
|
||||
@param[in] RegisterGroup Pointer to Group registers.
|
||||
|
||||
**/
|
||||
VOID
|
||||
ReadRegisterGroup (
|
||||
IN DEBUG_CPU_CONTEXT *CpuContext,
|
||||
IN DEBUG_DATA_REPONSE_READ_REGISTER_GROUP *RegisterGroup
|
||||
)
|
||||
{
|
||||
RegisterGroup->Cs = (UINT16) CpuContext->Cs;
|
||||
RegisterGroup->Ds = (UINT16) CpuContext->Ds;
|
||||
RegisterGroup->Es = (UINT16) CpuContext->Es;
|
||||
RegisterGroup->Fs = (UINT16) CpuContext->Fs;
|
||||
RegisterGroup->Gs = (UINT16) CpuContext->Gs;
|
||||
RegisterGroup->Ss = (UINT16) CpuContext->Ss;
|
||||
RegisterGroup->Eflags = (UINT32) CpuContext->Eflags;
|
||||
RegisterGroup->Rbp = CpuContext->Rbp;
|
||||
RegisterGroup->Eip = CpuContext->Eip;
|
||||
RegisterGroup->Rsp = CpuContext->Rsp;
|
||||
RegisterGroup->Eax = CpuContext->Rax;
|
||||
RegisterGroup->Rbx = CpuContext->Rbx;
|
||||
RegisterGroup->Rcx = CpuContext->Rcx;
|
||||
RegisterGroup->Rdx = CpuContext->Rdx;
|
||||
RegisterGroup->Rsi = CpuContext->Rsi;
|
||||
RegisterGroup->Rdi = CpuContext->Rdi;
|
||||
RegisterGroup->R8 = CpuContext->R8;
|
||||
RegisterGroup->R9 = CpuContext->R9;
|
||||
RegisterGroup->R10 = CpuContext->R10;
|
||||
RegisterGroup->R11 = CpuContext->R11;
|
||||
RegisterGroup->R12 = CpuContext->R12;
|
||||
RegisterGroup->R13 = CpuContext->R13;
|
||||
RegisterGroup->R14 = CpuContext->R14;
|
||||
RegisterGroup->R15 = CpuContext->R15;
|
||||
RegisterGroup->Dr0 = CpuContext->Dr0;
|
||||
RegisterGroup->Dr1 = CpuContext->Dr1;
|
||||
RegisterGroup->Dr2 = CpuContext->Dr2;
|
||||
RegisterGroup->Dr3 = CpuContext->Dr3;
|
||||
RegisterGroup->Dr6 = CpuContext->Dr6;
|
||||
RegisterGroup->Dr7 = CpuContext->Dr7;
|
||||
RegisterGroup->Cr0 = CpuContext->Cr0;
|
||||
RegisterGroup->Cr2 = CpuContext->Cr2;
|
||||
RegisterGroup->Cr3 = CpuContext->Cr3;
|
||||
RegisterGroup->Cr4 = CpuContext->Cr4;
|
||||
RegisterGroup->Cr8 = CpuContext->Cr8;
|
||||
|
||||
CopyMem ((UINT8 *) &RegisterGroup->Xmm0[0], (UINT8 *) &CpuContext->FxSaveState.Xmm0[0], 16 * 10);
|
||||
}
|
||||
|
||||
/**
|
||||
Initialize IDT entries to support source level debug.
|
||||
|
||||
|
|
@ -252,4 +59,9 @@ InitializeDebugIdt (
|
|||
IdtEntry[DEBUG_TIMER_VECTOR].Bits.OffsetUpper = (UINT32)((UINTN)InterruptHandler >> 32);
|
||||
IdtEntry[DEBUG_TIMER_VECTOR].Bits.Selector = CodeSegment;
|
||||
IdtEntry[DEBUG_TIMER_VECTOR].Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32;
|
||||
|
||||
//
|
||||
// Set DE flag in CR4 to enable IO breakpoint
|
||||
//
|
||||
AsmWriteCr4 (AsmReadCr4 () | BIT3);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/** @file
|
||||
X64 specific defintions for debug agent library instance.
|
||||
|
||||
Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
|
||||
Copyright (c) 2010 - 2012, Intel Corporation. All rights reserved.<BR>
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
|
|
@ -15,17 +15,13 @@
|
|||
#ifndef _ARCH_DEBUG_SUPPORT_H_
|
||||
#define _ARCH_DEBUG_SUPPORT_H_
|
||||
|
||||
#include "ArchRegisters.h"
|
||||
#include "ProcessorContext.h"
|
||||
#include "TransferProtocol.h"
|
||||
|
||||
typedef DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_X64 DEBUG_DATA_REPONSE_READ_REGISTER_GROUP;
|
||||
typedef DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGLIM_X64 DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGLIM;
|
||||
typedef DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGBASE_X64 DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGBASE;
|
||||
|
||||
#define DEBUG_SW_BREAKPOINT_SYMBOL 0xcc
|
||||
|
||||
#define DEBUG_ARCH_SYMBOL DEBUG_DATA_BREAK_CPU_ARCH_X64
|
||||
|
||||
typedef DEBUG_DATA_X64_FX_SAVE_STATE DEBUG_DATA_FX_SAVE_STATE;
|
||||
typedef DEBUG_DATA_X64_SYSTEM_CONTEXT DEBUG_CPU_CONTEXT;
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,259 +0,0 @@
|
|||
/** @file
|
||||
x64 Group registers read support functions.
|
||||
|
||||
Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#include "DebugAgent.h"
|
||||
|
||||
/**
|
||||
Read segment selector by register index.
|
||||
|
||||
@param[in] CpuContext Pointer to saved CPU context.
|
||||
@param[in] RegisterIndex Register Index.
|
||||
|
||||
@return Value of segment selector.
|
||||
|
||||
**/
|
||||
UINT64
|
||||
ReadRegisterSelectorByIndex (
|
||||
IN DEBUG_CPU_CONTEXT *CpuContext,
|
||||
IN UINT8 RegisterIndex
|
||||
)
|
||||
{
|
||||
IA32_DESCRIPTOR *Ia32Descriptor;
|
||||
IA32_GDT *Ia32Gdt;
|
||||
UINT16 Selector;
|
||||
UINT32 Data32;
|
||||
|
||||
Ia32Descriptor = (IA32_DESCRIPTOR *) CpuContext->Gdtr;
|
||||
Ia32Gdt = (IA32_GDT *) (Ia32Descriptor->Base);
|
||||
|
||||
Selector = 0;
|
||||
|
||||
switch (RegisterIndex) {
|
||||
case SOFT_DEBUGGER_REGISTER_CSAS:
|
||||
Selector = (UINT16) CpuContext->Cs;
|
||||
break;
|
||||
case SOFT_DEBUGGER_REGISTER_SSAS:
|
||||
Selector = (UINT16) CpuContext->Ss;
|
||||
break;
|
||||
case SOFT_DEBUGGER_REGISTER_GSAS:
|
||||
Selector = (UINT16) CpuContext->Gs;
|
||||
break;
|
||||
case SOFT_DEBUGGER_REGISTER_FSAS:
|
||||
Selector = (UINT16) CpuContext->Fs;
|
||||
break;
|
||||
case SOFT_DEBUGGER_REGISTER_ESAS:
|
||||
Selector = (UINT16) CpuContext->Es;
|
||||
break;
|
||||
case SOFT_DEBUGGER_REGISTER_DSAS:
|
||||
Selector = (UINT16) CpuContext->Ds;
|
||||
case SOFT_DEBUGGER_REGISTER_LDTAS:
|
||||
case SOFT_DEBUGGER_REGISTER_TSSAS:
|
||||
return 0x00820000;
|
||||
break;
|
||||
}
|
||||
|
||||
Data32 = (UINT32) RShiftU64 (Ia32Gdt[Selector / 8].Uint64, 24);
|
||||
return (Data32 & (UINT32)(~0xff)) | Selector;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
Read group register of Segment Base.
|
||||
|
||||
@param[in] CpuContext Pointer to saved CPU context.
|
||||
@param[in] RegisterGroupSegBase Pointer to Group registers.
|
||||
|
||||
**/
|
||||
VOID
|
||||
ReadRegisterGroupSegBase (
|
||||
IN DEBUG_CPU_CONTEXT *CpuContext,
|
||||
IN DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGBASE *RegisterGroupSegBase
|
||||
)
|
||||
{
|
||||
IA32_DESCRIPTOR *Ia32Descriptor;
|
||||
IA32_GDT *Ia32Gdt;
|
||||
UINTN Index;
|
||||
|
||||
Ia32Descriptor = (IA32_DESCRIPTOR *) CpuContext->Gdtr;
|
||||
Ia32Gdt = (IA32_GDT *) (Ia32Descriptor->Base);
|
||||
|
||||
Index = CpuContext->Cs / 8;
|
||||
RegisterGroupSegBase->CsBas = (Ia32Gdt[Index].Bits.BaseLow) + (Ia32Gdt[Index].Bits.BaseMid << 16) + (Ia32Gdt[Index].Bits.BaseMid << 24);
|
||||
Index = CpuContext->Ss / 8;
|
||||
RegisterGroupSegBase->SsBas = (Ia32Gdt[Index].Bits.BaseLow) + (Ia32Gdt[Index].Bits.BaseMid << 16) + (Ia32Gdt[Index].Bits.BaseMid << 24);
|
||||
Index = CpuContext->Gs / 8;
|
||||
RegisterGroupSegBase->GsBas = (Ia32Gdt[Index].Bits.BaseLow) + (Ia32Gdt[Index].Bits.BaseMid << 16) + (Ia32Gdt[Index].Bits.BaseMid << 24);
|
||||
Index = CpuContext->Fs / 8;
|
||||
RegisterGroupSegBase->FsBas = (Ia32Gdt[Index].Bits.BaseLow) + (Ia32Gdt[Index].Bits.BaseMid << 16) + (Ia32Gdt[Index].Bits.BaseMid << 24);
|
||||
Index = CpuContext->Es / 8;
|
||||
RegisterGroupSegBase->EsBas = (Ia32Gdt[Index].Bits.BaseLow) + (Ia32Gdt[Index].Bits.BaseMid << 16) + (Ia32Gdt[Index].Bits.BaseMid << 24);
|
||||
Index = CpuContext->Ds / 8;
|
||||
RegisterGroupSegBase->DsBas = (Ia32Gdt[Index].Bits.BaseLow) + (Ia32Gdt[Index].Bits.BaseMid << 16) + (Ia32Gdt[Index].Bits.BaseMid << 24);
|
||||
|
||||
RegisterGroupSegBase->LdtBas = 0;
|
||||
RegisterGroupSegBase->TssBas = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
Read group register of Segment Limit.
|
||||
|
||||
@param[in] CpuContext Pointer to saved CPU context.
|
||||
@param[in] RegisterGroupSegLim Pointer to Group registers.
|
||||
|
||||
**/
|
||||
VOID
|
||||
ReadRegisterGroupSegLim (
|
||||
IN DEBUG_CPU_CONTEXT *CpuContext,
|
||||
IN DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGLIM *RegisterGroupSegLim
|
||||
)
|
||||
{
|
||||
IA32_DESCRIPTOR *Ia32Descriptor;
|
||||
IA32_GDT *Ia32Gdt;
|
||||
UINTN Index;
|
||||
|
||||
Ia32Descriptor = (IA32_DESCRIPTOR *) CpuContext->Gdtr;
|
||||
Ia32Gdt = (IA32_GDT *) (Ia32Descriptor->Base);
|
||||
|
||||
Index = CpuContext->Cs / 8;
|
||||
RegisterGroupSegLim->CsLim = Ia32Gdt[Index].Bits.LimitLow + (Ia32Gdt[Index].Bits.LimitHigh << 16);
|
||||
if (Ia32Gdt[Index].Bits.Granularity == 1) {
|
||||
RegisterGroupSegLim->CsLim = (RegisterGroupSegLim->CsLim << 12) | 0xfff;
|
||||
}
|
||||
|
||||
Index = CpuContext->Ss / 8;
|
||||
RegisterGroupSegLim->SsLim = Ia32Gdt[Index].Bits.LimitLow + (Ia32Gdt[Index].Bits.LimitHigh << 16);
|
||||
if (Ia32Gdt[Index].Bits.Granularity == 1) {
|
||||
RegisterGroupSegLim->SsLim = (RegisterGroupSegLim->SsLim << 12) | 0xfff;
|
||||
}
|
||||
|
||||
Index = CpuContext->Gs / 8;
|
||||
RegisterGroupSegLim->GsLim = Ia32Gdt[Index].Bits.LimitLow + (Ia32Gdt[Index].Bits.LimitHigh << 16);
|
||||
if (Ia32Gdt[Index].Bits.Granularity == 1) {
|
||||
RegisterGroupSegLim->GsLim = (RegisterGroupSegLim->GsLim << 12) | 0xfff;
|
||||
}
|
||||
|
||||
Index = CpuContext->Fs / 8;
|
||||
RegisterGroupSegLim->FsLim = Ia32Gdt[Index].Bits.LimitLow + (Ia32Gdt[Index].Bits.LimitHigh << 16);
|
||||
if (Ia32Gdt[Index].Bits.Granularity == 1) {
|
||||
RegisterGroupSegLim->FsLim = (RegisterGroupSegLim->FsLim << 12) | 0xfff;
|
||||
}
|
||||
|
||||
Index = CpuContext->Es / 8;
|
||||
RegisterGroupSegLim->EsLim = Ia32Gdt[Index].Bits.LimitLow + (Ia32Gdt[Index].Bits.LimitHigh << 16);
|
||||
if (Ia32Gdt[Index].Bits.Granularity == 1) {
|
||||
RegisterGroupSegLim->EsLim = (RegisterGroupSegLim->EsLim << 12) | 0xfff;
|
||||
}
|
||||
|
||||
Index = CpuContext->Ds / 8;
|
||||
RegisterGroupSegLim->DsLim = Ia32Gdt[Index].Bits.LimitLow + (Ia32Gdt[Index].Bits.LimitHigh << 16);
|
||||
if (Ia32Gdt[Index].Bits.Granularity == 1) {
|
||||
RegisterGroupSegLim->DsLim = (RegisterGroupSegLim->DsLim << 12) | 0xfff;
|
||||
}
|
||||
|
||||
RegisterGroupSegLim->LdtLim = 0xffff;
|
||||
RegisterGroupSegLim->TssLim = 0xffff;
|
||||
}
|
||||
|
||||
/**
|
||||
Read group register by group index.
|
||||
|
||||
@param[in] CpuContext Pointer to saved CPU context.
|
||||
@param[in] GroupIndex Group Index.
|
||||
|
||||
@retval RETURN_SUCCESS Read successfully.
|
||||
@retval RETURN_NOT_SUPPORTED Group index cannot be supported.
|
||||
|
||||
**/
|
||||
RETURN_STATUS
|
||||
ArchReadRegisterGroup (
|
||||
IN DEBUG_CPU_CONTEXT *CpuContext,
|
||||
IN UINT8 GroupIndex
|
||||
)
|
||||
{
|
||||
UINTN DataN;
|
||||
DEBUG_DATA_REPONSE_READ_REGISTER_GROUP RegisterGroup;
|
||||
DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGMENT_BAS_LIM RegisterGroupBasLim;
|
||||
DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGMENT_BASES_X64 RegisterGroupBases64;
|
||||
|
||||
switch (GroupIndex) {
|
||||
case SOFT_DEBUGGER_REGISTER_GROUP_SEGMENT64:
|
||||
ReadRegisterGroup (CpuContext, &RegisterGroup);
|
||||
SendDataResponsePacket (CpuContext, (UINT8 *) &RegisterGroup, (UINT16) sizeof (DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGMENT));
|
||||
break;
|
||||
|
||||
case SOFT_DEBUGGER_REGISTER_GROUP_SEGMENT_BAS_LIM64:
|
||||
DataN = (UINTN) (CpuContext->Idtr[0] & 0xffff);
|
||||
RegisterGroupBasLim.IdtLim = DataN;
|
||||
DataN = (UINTN) (CpuContext->Gdtr[0] & 0xffff);
|
||||
RegisterGroupBasLim.GdtLim = DataN;
|
||||
DataN = (UINTN) RShiftU64 (CpuContext->Idtr[0], 16);
|
||||
DataN |= (UINTN) LShiftU64 (CpuContext->Idtr[1], sizeof (UINTN) * 8 - 16);
|
||||
RegisterGroupBasLim.IdtBas = DataN;
|
||||
DataN = (UINTN) RShiftU64 (CpuContext->Gdtr[0], 16);
|
||||
DataN |= (UINTN) LShiftU64 (CpuContext->Gdtr[1], sizeof (UINTN) * 8 - 16);
|
||||
RegisterGroupBasLim.GdtBas = DataN;
|
||||
|
||||
ReadRegisterGroupSegLim (CpuContext, (DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGLIM *) &RegisterGroupBasLim.CsLim);
|
||||
ReadRegisterGroupSegBase (CpuContext, (DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGBASE *) &RegisterGroupBasLim.CsBas);
|
||||
|
||||
SendDataResponsePacket (CpuContext, (UINT8 *) &RegisterGroupBasLim, (UINT16) sizeof (DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGMENT_BAS_LIM));
|
||||
break;
|
||||
|
||||
case SOFT_DEBUGGER_REGISTER_GROUP_GP2_64:
|
||||
ReadRegisterGroup (CpuContext, &RegisterGroup);
|
||||
SendDataResponsePacket (CpuContext, (UINT8 *) &RegisterGroup.Eflags, (UINT16) sizeof (DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_GP2));
|
||||
break;
|
||||
|
||||
case SOFT_DEBUGGER_REGISTER_GROUP_GP64:
|
||||
ReadRegisterGroup (CpuContext, &RegisterGroup);
|
||||
SendDataResponsePacket (CpuContext, (UINT8 *) &RegisterGroup.Eax, (UINT16) sizeof (DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_GP));
|
||||
break;
|
||||
|
||||
case SOFT_DEBUGGER_REGISTER_GROUP_DR64:
|
||||
ReadRegisterGroup (CpuContext, &RegisterGroup);
|
||||
SendDataResponsePacket (CpuContext, (UINT8 *) &RegisterGroup.Dr0, (UINT16) sizeof (DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_DR));
|
||||
break;
|
||||
|
||||
case SOFT_DEBUGGER_REGISTER_GROUP_SEGMENT_BASES64:
|
||||
RegisterGroupBases64.Ldtr = (UINT16) CpuContext->Ldtr;
|
||||
RegisterGroupBases64.Tr = (UINT16) CpuContext->Tr;
|
||||
|
||||
RegisterGroupBases64.Csas = ReadRegisterSelectorByIndex (CpuContext, SOFT_DEBUGGER_REGISTER_CSAS);
|
||||
RegisterGroupBases64.Ssas = ReadRegisterSelectorByIndex (CpuContext, SOFT_DEBUGGER_REGISTER_SSAS);
|
||||
RegisterGroupBases64.Gsas = ReadRegisterSelectorByIndex (CpuContext, SOFT_DEBUGGER_REGISTER_GSAS);
|
||||
RegisterGroupBases64.Fsas = ReadRegisterSelectorByIndex (CpuContext, SOFT_DEBUGGER_REGISTER_FSAS);
|
||||
RegisterGroupBases64.Esas = ReadRegisterSelectorByIndex (CpuContext, SOFT_DEBUGGER_REGISTER_ESAS);
|
||||
RegisterGroupBases64.Dsas = ReadRegisterSelectorByIndex (CpuContext, SOFT_DEBUGGER_REGISTER_DSAS);
|
||||
RegisterGroupBases64.Ldtas = ReadRegisterSelectorByIndex (CpuContext, SOFT_DEBUGGER_REGISTER_LDTAS);
|
||||
RegisterGroupBases64.Tssas = ReadRegisterSelectorByIndex (CpuContext, SOFT_DEBUGGER_REGISTER_TSSAS);
|
||||
|
||||
SendDataResponsePacket (CpuContext, (UINT8 *) &RegisterGroupBases64, (UINT16) sizeof (DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGMENT_BASES_X64));
|
||||
break;
|
||||
|
||||
case SOFT_DEBUGGER_REGISTER_GROUP_CR64:
|
||||
ReadRegisterGroup (CpuContext, &RegisterGroup);
|
||||
SendDataResponsePacket (CpuContext, (UINT8 *) &RegisterGroup.Dr7 + 8, (UINT16) sizeof (DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_CR));
|
||||
break;
|
||||
|
||||
case SOFT_DEBUGGER_REGISTER_GROUP_XMM64:
|
||||
ReadRegisterGroup (CpuContext, &RegisterGroup);
|
||||
SendDataResponsePacket (CpuContext, (UINT8 *) &RegisterGroup.Dr7 + 8 * 6, (UINT16) sizeof (DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_XMM));
|
||||
break;
|
||||
|
||||
default:
|
||||
return RETURN_UNSUPPORTED;
|
||||
}
|
||||
|
||||
return RETURN_SUCCESS;
|
||||
}
|
||||
|
|
@ -1,332 +0,0 @@
|
|||
/** @file
|
||||
X64 register defintions needed by debug transfer protocol.
|
||||
|
||||
Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef _ARCH_REGISTERS_H_
|
||||
#define _ARCH_REGISTERS_H_
|
||||
|
||||
#pragma pack(1)
|
||||
|
||||
///
|
||||
/// FXSAVE_STATE (promoted operation)
|
||||
/// FP / MMX / XMM registers (see fxrstor instruction definition)
|
||||
///
|
||||
typedef struct {
|
||||
UINT16 Fcw;
|
||||
UINT16 Fsw;
|
||||
UINT16 Ftw;
|
||||
UINT16 Opcode;
|
||||
UINT64 Rip;
|
||||
UINT64 DataOffset;
|
||||
UINT32 Mxcsr;
|
||||
UINT32 Mxcsr_Mask;
|
||||
UINT8 St0Mm0[10];
|
||||
UINT8 Reserved2[6];
|
||||
UINT8 St1Mm1[10];
|
||||
UINT8 Reserved3[6];
|
||||
UINT8 St2Mm2[10];
|
||||
UINT8 Reserved4[6];
|
||||
UINT8 St3Mm3[10];
|
||||
UINT8 Reserved5[6];
|
||||
UINT8 St4Mm4[10];
|
||||
UINT8 Reserved6[6];
|
||||
UINT8 St5Mm5[10];
|
||||
UINT8 Reserved7[6];
|
||||
UINT8 St6Mm6[10];
|
||||
UINT8 Reserved8[6];
|
||||
UINT8 St7Mm7[10];
|
||||
UINT8 Reserved9[6];
|
||||
UINT8 Xmm0[16];
|
||||
UINT8 Xmm1[16];
|
||||
UINT8 Xmm2[16];
|
||||
UINT8 Xmm3[16];
|
||||
UINT8 Xmm4[16];
|
||||
UINT8 Xmm5[16];
|
||||
UINT8 Xmm6[16];
|
||||
UINT8 Xmm7[16];
|
||||
UINT8 Xmm8[16];
|
||||
UINT8 Xmm9[16];
|
||||
UINT8 Xmm10[16];
|
||||
UINT8 Xmm11[16];
|
||||
UINT8 Xmm12[16];
|
||||
UINT8 Xmm13[16];
|
||||
UINT8 Xmm14[16];
|
||||
UINT8 Xmm15[16];
|
||||
UINT8 Reserved11[6 * 16];
|
||||
} DEBUG_DATA_X64_FX_SAVE_STATE;
|
||||
|
||||
///
|
||||
/// x64 processor context definition
|
||||
///
|
||||
typedef struct {
|
||||
DEBUG_DATA_X64_FX_SAVE_STATE FxSaveState;
|
||||
UINT64 Dr0;
|
||||
UINT64 Dr1;
|
||||
UINT64 Dr2;
|
||||
UINT64 Dr3;
|
||||
UINT64 Dr6;
|
||||
UINT64 Dr7;
|
||||
UINT64 Eflags;
|
||||
UINT64 Ldtr;
|
||||
UINT64 Tr;
|
||||
UINT64 Gdtr[2];
|
||||
UINT64 Idtr[2];
|
||||
UINT64 Eip;
|
||||
UINT64 Gs;
|
||||
UINT64 Fs;
|
||||
UINT64 Es;
|
||||
UINT64 Ds;
|
||||
UINT64 Cs;
|
||||
UINT64 Ss;
|
||||
UINT64 Cr0;
|
||||
UINT64 Cr1; /* Reserved */
|
||||
UINT64 Cr2;
|
||||
UINT64 Cr3;
|
||||
UINT64 Cr4;
|
||||
UINT64 Rdi;
|
||||
UINT64 Rsi;
|
||||
UINT64 Rbp;
|
||||
UINT64 Rsp;
|
||||
UINT64 Rdx;
|
||||
UINT64 Rcx;
|
||||
UINT64 Rbx;
|
||||
UINT64 Rax;
|
||||
UINT64 Cr8;
|
||||
UINT64 R8;
|
||||
UINT64 R9;
|
||||
UINT64 R10;
|
||||
UINT64 R11;
|
||||
UINT64 R12;
|
||||
UINT64 R13;
|
||||
UINT64 R14;
|
||||
UINT64 R15;
|
||||
} DEBUG_DATA_X64_SYSTEM_CONTEXT;
|
||||
|
||||
|
||||
///
|
||||
/// x64 GROUP register
|
||||
///
|
||||
typedef struct {
|
||||
UINT16 Cs;
|
||||
UINT16 Ds;
|
||||
UINT16 Es;
|
||||
UINT16 Fs;
|
||||
UINT16 Gs;
|
||||
UINT16 Ss;
|
||||
UINT32 Eflags;
|
||||
UINT64 Rbp;
|
||||
UINT64 Eip;
|
||||
UINT64 Rsp;
|
||||
UINT64 Eax;
|
||||
UINT64 Rbx;
|
||||
UINT64 Rcx;
|
||||
UINT64 Rdx;
|
||||
UINT64 Rsi;
|
||||
UINT64 Rdi;
|
||||
UINT64 R8;
|
||||
UINT64 R9;
|
||||
UINT64 R10;
|
||||
UINT64 R11;
|
||||
UINT64 R12;
|
||||
UINT64 R13;
|
||||
UINT64 R14;
|
||||
UINT64 R15;
|
||||
UINT64 Dr0;
|
||||
UINT64 Dr1;
|
||||
UINT64 Dr2;
|
||||
UINT64 Dr3;
|
||||
UINT64 Dr6;
|
||||
UINT64 Dr7;
|
||||
UINT64 Cr0;
|
||||
UINT64 Cr2;
|
||||
UINT64 Cr3;
|
||||
UINT64 Cr4;
|
||||
UINT64 Cr8;
|
||||
UINT8 Xmm0[16];
|
||||
UINT8 Xmm1[16];
|
||||
UINT8 Xmm2[16];
|
||||
UINT8 Xmm3[16];
|
||||
UINT8 Xmm4[16];
|
||||
UINT8 Xmm5[16];
|
||||
UINT8 Xmm6[16];
|
||||
UINT8 Xmm7[16];
|
||||
UINT8 Xmm8[16];
|
||||
UINT8 Xmm9[16];
|
||||
UINT8 Xmm10[16];
|
||||
UINT8 Xmm11[16];
|
||||
UINT8 Xmm12[16];
|
||||
UINT8 Xmm13[16];
|
||||
UINT8 Xmm14[16];
|
||||
UINT8 Xmm15[16];
|
||||
} DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_X64;
|
||||
|
||||
///
|
||||
/// x64 Segment Limit GROUP register
|
||||
///
|
||||
typedef struct {
|
||||
UINT64 CsLim;
|
||||
UINT64 SsLim;
|
||||
UINT64 GsLim;
|
||||
UINT64 FsLim;
|
||||
UINT64 EsLim;
|
||||
UINT64 DsLim;
|
||||
UINT64 LdtLim;
|
||||
UINT64 TssLim;
|
||||
} DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGLIM_X64;
|
||||
|
||||
///
|
||||
/// x64 Segment Base GROUP register
|
||||
///
|
||||
typedef struct {
|
||||
UINT64 CsBas;
|
||||
UINT64 SsBas;
|
||||
UINT64 GsBas;
|
||||
UINT64 FsBas;
|
||||
UINT64 EsBas;
|
||||
UINT64 DsBas;
|
||||
UINT64 LdtBas;
|
||||
UINT64 TssBas;
|
||||
} DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGBASE_X64;
|
||||
|
||||
///
|
||||
/// x64 Segment Base/Limit GROUP register
|
||||
///
|
||||
typedef struct {
|
||||
UINT64 IdtBas;
|
||||
UINT64 IdtLim;
|
||||
UINT64 GdtBas;
|
||||
UINT64 GdtLim;
|
||||
UINT64 CsLim;
|
||||
UINT64 SsLim;
|
||||
UINT64 GsLim;
|
||||
UINT64 FsLim;
|
||||
UINT64 EsLim;
|
||||
UINT64 DsLim;
|
||||
UINT64 LdtLim;
|
||||
UINT64 TssLim;
|
||||
UINT64 CsBas;
|
||||
UINT64 SsBas;
|
||||
UINT64 GsBas;
|
||||
UINT64 FsBas;
|
||||
UINT64 EsBas;
|
||||
UINT64 DsBas;
|
||||
UINT64 LdtBas;
|
||||
UINT64 TssBas;
|
||||
} DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGMENT_BAS_LIM;
|
||||
|
||||
///
|
||||
/// x64 register GROUP register
|
||||
///
|
||||
typedef struct {
|
||||
UINT32 Eflags;
|
||||
UINT64 Rbp;
|
||||
UINT64 Eip;
|
||||
UINT64 Rsp;
|
||||
} DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_GP2;
|
||||
|
||||
///
|
||||
/// x64 general register GROUP register
|
||||
///
|
||||
typedef struct {
|
||||
UINT64 Eax;
|
||||
UINT64 Rbx;
|
||||
UINT64 Rcx;
|
||||
UINT64 Rdx;
|
||||
UINT64 Rsi;
|
||||
UINT64 Rdi;
|
||||
UINT64 R8;
|
||||
UINT64 R9;
|
||||
UINT64 R10;
|
||||
UINT64 R11;
|
||||
UINT64 R12;
|
||||
UINT64 R13;
|
||||
UINT64 R14;
|
||||
UINT64 R15;
|
||||
} DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_GP;
|
||||
|
||||
///
|
||||
/// x64 Segment GROUP register
|
||||
///
|
||||
typedef struct {
|
||||
UINT16 Cs;
|
||||
UINT16 Ds;
|
||||
UINT16 Es;
|
||||
UINT16 Fs;
|
||||
UINT16 Gs;
|
||||
UINT16 Ss;
|
||||
} DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGMENT;
|
||||
|
||||
///
|
||||
/// x64 Debug Register GROUP register
|
||||
///
|
||||
typedef struct {
|
||||
UINT64 Dr0;
|
||||
UINT64 Dr1;
|
||||
UINT64 Dr2;
|
||||
UINT64 Dr3;
|
||||
UINT64 Dr6;
|
||||
UINT64 Dr7;
|
||||
} DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_DR;
|
||||
|
||||
///
|
||||
/// x64 Control Register GROUP register
|
||||
///
|
||||
typedef struct {
|
||||
UINT64 Cr0;
|
||||
UINT64 Cr2;
|
||||
UINT64 Cr3;
|
||||
UINT64 Cr4;
|
||||
UINT64 Cr8;
|
||||
} DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_CR;
|
||||
|
||||
///
|
||||
/// x64 XMM Register GROUP register
|
||||
///
|
||||
typedef struct {
|
||||
UINT8 Xmm0[16];
|
||||
UINT8 Xmm1[16];
|
||||
UINT8 Xmm2[16];
|
||||
UINT8 Xmm3[16];
|
||||
UINT8 Xmm4[16];
|
||||
UINT8 Xmm5[16];
|
||||
UINT8 Xmm6[16];
|
||||
UINT8 Xmm7[16];
|
||||
UINT8 Xmm8[16];
|
||||
UINT8 Xmm9[16];
|
||||
UINT8 Xmm10[16];
|
||||
UINT8 Xmm11[16];
|
||||
UINT8 Xmm12[16];
|
||||
UINT8 Xmm13[16];
|
||||
UINT8 Xmm14[16];
|
||||
UINT8 Xmm15[16];
|
||||
} DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_XMM;
|
||||
|
||||
///
|
||||
/// x64 Segment Base GROUP register
|
||||
///
|
||||
typedef struct {
|
||||
UINT16 Ldtr;
|
||||
UINT16 Tr;
|
||||
UINT64 Csas;
|
||||
UINT64 Ssas;
|
||||
UINT64 Gsas;
|
||||
UINT64 Fsas;
|
||||
UINT64 Esas;
|
||||
UINT64 Dsas;
|
||||
UINT64 Ldtas;
|
||||
UINT64 Tssas;
|
||||
} DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGMENT_BASES_X64;
|
||||
|
||||
#pragma pack()
|
||||
|
||||
#endif
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
#------------------------------------------------------------------------------
|
||||
#
|
||||
# Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
|
||||
# Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
|
||||
# This program and the accompanying materials
|
||||
# are licensed and made available under the terms and conditions of the BSD License
|
||||
# which accompanies this distribution. The full text of the license may be found at
|
||||
|
|
@ -302,6 +302,9 @@ NoExtrPush:
|
|||
movq %rsp, %rdi
|
||||
.byte 0x0f, 0xae, 0b00000111
|
||||
|
||||
## save the exception data;
|
||||
pushq 16(%rbp)
|
||||
|
||||
## Clear Direction Flag
|
||||
cld
|
||||
|
||||
|
|
@ -313,9 +316,12 @@ NoExtrPush:
|
|||
# Per X64 calling convention, allocate maximum parameter stack space
|
||||
# and make sure RSP is 16-byte aligned
|
||||
#
|
||||
subq $(4 * 8), %rsp
|
||||
subq $(32 + 8), %rsp
|
||||
call ASM_PFX(InterruptProcess)
|
||||
addq $(4 * 8), %rsp
|
||||
addq $(32 + 8), %rsp
|
||||
|
||||
## skip the exception data;
|
||||
addq $8, %rsp
|
||||
|
||||
## FX_SAVE_STATE_X64 FxSaveState;
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
;------------------------------------------------------------------------------
|
||||
;
|
||||
; Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
|
||||
; Copyright (c) 2010 - 2012, Intel Corporation. All rights reserved.<BR>
|
||||
; This program and the accompanying materials
|
||||
; are licensed and made available under the terms and conditions of the BSD License
|
||||
; which accompanies this distribution. The full text of the license may be found at
|
||||
|
|
@ -263,9 +263,12 @@ NoExtrPush:
|
|||
push rax
|
||||
|
||||
sub rsp, 512
|
||||
mov rdi, rsp
|
||||
mov rdi, rsp
|
||||
db 0fh, 0aeh, 00000111y ;fxsave [rdi]
|
||||
|
||||
;; save the exception data
|
||||
push qword ptr [rbp + 16]
|
||||
|
||||
;; Clear Direction Flag
|
||||
cld
|
||||
|
||||
|
|
@ -273,9 +276,16 @@ NoExtrPush:
|
|||
mov rdx, rsp ; Structure
|
||||
mov r15, rcx ; save vector in r15
|
||||
|
||||
sub rsp, 32
|
||||
;
|
||||
; Per X64 calling convention, allocate maximum parameter stack space
|
||||
; and make sure RSP is 16-byte aligned
|
||||
;
|
||||
sub rsp, 32 + 8
|
||||
call InterruptProcess
|
||||
add rsp, 32
|
||||
add rsp, 32 + 8
|
||||
|
||||
;; skip the exception data
|
||||
add rsp, 8
|
||||
|
||||
mov rsi, rsp
|
||||
db 0fh, 0aeh, 00001110y ; fxrstor [rsi]
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/** @file
|
||||
Debug Agent library implementition for Dxe Core and Dxr modules.
|
||||
|
||||
Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
|
||||
Copyright (c) 2010 - 2012, Intel Corporation. All rights reserved.<BR>
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
|
|
@ -15,13 +15,9 @@
|
|||
#include "DxeDebugAgentLib.h"
|
||||
|
||||
DEBUG_AGENT_MAILBOX mMailbox;
|
||||
|
||||
DEBUG_AGENT_MAILBOX *mMailboxPointer;
|
||||
|
||||
IA32_IDT_GATE_DESCRIPTOR mIdtEntryTable[33];
|
||||
|
||||
BOOLEAN mConfigurationTableNeeded = FALSE;
|
||||
|
||||
BOOLEAN mDxeCoreFlag = FALSE;
|
||||
CONST BOOLEAN MultiProcessorDebugSupport = TRUE;
|
||||
|
||||
/**
|
||||
|
|
@ -31,8 +27,7 @@ CONST BOOLEAN MultiProcessorDebugSupport = TRUE;
|
|||
@param[in] ImageHandle The firmware allocated handle for the EFI image.
|
||||
@param[in] SystemTable A pointer to the EFI System Table.
|
||||
|
||||
@retval RETURN_SUCCESS Allocate the global memory space to store guid and function tables.
|
||||
@retval RETURN_OUT_OF_RESOURCES No enough memory to allocated.
|
||||
@retval RETURN_SUCCESS Allocate the global memory space to store guid and function tables.
|
||||
|
||||
**/
|
||||
RETURN_STATUS
|
||||
|
|
@ -44,11 +39,34 @@ DxeDebugAgentLibConstructor (
|
|||
{
|
||||
EFI_STATUS Status;
|
||||
EFI_PHYSICAL_ADDRESS Address;
|
||||
EFI_EVENT Event;
|
||||
VOID *EventRegistration;
|
||||
|
||||
if (!mConfigurationTableNeeded) {
|
||||
if (!mDxeCoreFlag) {
|
||||
return RETURN_SUCCESS;
|
||||
}
|
||||
|
||||
Status = gBS->CreateEvent (
|
||||
EVT_NOTIFY_SIGNAL,
|
||||
TPL_CALLBACK,
|
||||
InstallSerialIoNotification,
|
||||
NULL,
|
||||
&Event
|
||||
);
|
||||
ASSERT_EFI_ERROR (Status);
|
||||
|
||||
//
|
||||
// Register for protocol notifications on this event
|
||||
//
|
||||
|
||||
Status = gBS->RegisterProtocolNotify (
|
||||
&gEfiPcdProtocolGuid,
|
||||
Event,
|
||||
&EventRegistration
|
||||
);
|
||||
|
||||
ASSERT_EFI_ERROR (Status);
|
||||
|
||||
Address = 0;
|
||||
Status = gBS->AllocatePages (
|
||||
AllocateAnyPages,
|
||||
|
|
@ -56,9 +74,7 @@ DxeDebugAgentLibConstructor (
|
|||
EFI_SIZE_TO_PAGES (sizeof (DEBUG_AGENT_MAILBOX)),
|
||||
&Address
|
||||
);
|
||||
if (EFI_ERROR (Status)) {
|
||||
return Status;
|
||||
}
|
||||
ASSERT_EFI_ERROR (Status);
|
||||
|
||||
CopyMem (
|
||||
(UINT8 *) (UINTN) Address,
|
||||
|
|
@ -68,7 +84,10 @@ DxeDebugAgentLibConstructor (
|
|||
|
||||
mMailboxPointer = (DEBUG_AGENT_MAILBOX *) (UINTN) Address;
|
||||
|
||||
return gBS->InstallConfigurationTable (&gEfiDebugAgentGuid, (VOID *) mMailboxPointer);
|
||||
Status = gBS->InstallConfigurationTable (&gEfiDebugAgentGuid, (VOID *) mMailboxPointer);
|
||||
ASSERT_EFI_ERROR (Status);
|
||||
|
||||
return Status;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -168,8 +187,13 @@ InitializeDebugAgent (
|
|||
//
|
||||
// Try to get Mailbox from GUIDed HOB.
|
||||
//
|
||||
mConfigurationTableNeeded = TRUE;
|
||||
mDxeCoreFlag = TRUE;
|
||||
Mailbox = GetMailboxFromHob (Context);
|
||||
|
||||
//
|
||||
// Clear Break CPU index value
|
||||
//
|
||||
mDebugMpContext.BreakAtCpuIndex = (UINT32) -1;
|
||||
|
||||
} else if (InitFlag == DEBUG_AGENT_INIT_DXE_AP) {
|
||||
|
||||
|
|
@ -189,7 +213,6 @@ InitializeDebugAgent (
|
|||
// If Mailbox exists, copy it into one global variable.
|
||||
//
|
||||
CopyMem (&mMailbox, Mailbox, sizeof (DEBUG_AGENT_MAILBOX));
|
||||
mMailbox.DebugPortHandle = 0;
|
||||
} else {
|
||||
//
|
||||
// If Mailbox not exists, used the local Mailbox.
|
||||
|
|
@ -207,6 +230,7 @@ InitializeDebugAgent (
|
|||
if (IdtEntryCount < 33) {
|
||||
Idtr.Limit = (UINT16) (sizeof (IA32_IDT_GATE_DESCRIPTOR) * 33 - 1);
|
||||
Idtr.Base = (UINTN) &mIdtEntryTable;
|
||||
ZeroMem (&mIdtEntryTable, Idtr.Limit + 1);
|
||||
AsmWriteIdtr ((IA32_DESCRIPTOR *) &Idtr);
|
||||
}
|
||||
|
||||
|
|
@ -218,7 +242,7 @@ InitializeDebugAgent (
|
|||
//
|
||||
// Initialize debug communication port
|
||||
//
|
||||
mMailboxPointer->DebugPortHandle = (UINT64) (UINTN)DebugPortInitialize (NULL, NULL);
|
||||
mMailboxPointer->DebugPortHandle = (UINT64) (UINTN)DebugPortInitialize ((VOID *)(UINTN)mMailbox.DebugPortHandle, NULL);
|
||||
|
||||
InitializeSpinLock (&mDebugMpContext.MpContextSpinLock);
|
||||
InitializeSpinLock (&mDebugMpContext.DebugPortSpinLock);
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/** @file
|
||||
Header file for Dxe Core Debug Agent Library instance.
|
||||
|
||||
Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
|
||||
Copyright (c) 2010 - 2012, Intel Corporation. All rights reserved.<BR>
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
|
|
@ -17,9 +17,29 @@
|
|||
|
||||
#include <PiDxe.h>
|
||||
|
||||
#include <Protocol/SerialIo.h>
|
||||
#include <Protocol/DevicePath.h>
|
||||
#include <Protocol/PiPcd.h>
|
||||
|
||||
#include <Library/UefiBootServicesTableLib.h>
|
||||
#include <Library/UefiLib.h>
|
||||
#include <Library/DevicePathLib.h>
|
||||
|
||||
#include "DebugAgent.h"
|
||||
|
||||
/**
|
||||
Notification function on EFI PCD protocol to install EFI Serial IO protocol based
|
||||
on Debug Communication Library.
|
||||
|
||||
@param[in] Event The event of notify protocol.
|
||||
@param[in] Context Notify event context.
|
||||
|
||||
**/
|
||||
VOID
|
||||
EFIAPI
|
||||
InstallSerialIoNotification (
|
||||
IN EFI_EVENT Event,
|
||||
IN VOID *Context
|
||||
);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -0,0 +1,722 @@
|
|||
/** @file
|
||||
Install Serial IO Protocol that layers on top of a Debug Communication Library instance.
|
||||
|
||||
Copyright (c) 2012, Intel Corporation. All rights reserved.<BR>
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#include "DxeDebugAgentLib.h"
|
||||
|
||||
//
|
||||
// Serial I/O Protocol Interface defintions.
|
||||
//
|
||||
|
||||
/**
|
||||
Reset serial device.
|
||||
|
||||
@param[in] This Pointer to EFI_SERIAL_IO_PROTOCOL.
|
||||
|
||||
@retval EFI_SUCCESS Reset successfully.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
SerialReset (
|
||||
IN EFI_SERIAL_IO_PROTOCOL *This
|
||||
);
|
||||
|
||||
/**
|
||||
Set new attributes to a serial device.
|
||||
|
||||
@param[in] This Pointer to EFI_SERIAL_IO_PROTOCOL.
|
||||
@param[in] BaudRate The baudrate of the serial device.
|
||||
@param[in] ReceiveFifoDepth The depth of receive FIFO buffer.
|
||||
@param[in] Timeout The request timeout for a single char.
|
||||
@param[in] Parity The type of parity used in serial device.
|
||||
@param[in] DataBits Number of databits used in serial device.
|
||||
@param[in] StopBits Number of stopbits used in serial device.
|
||||
|
||||
@retval EFI_SUCCESS The new attributes were set.
|
||||
@retval EFI_INVALID_PARAMETER One or more attributes have an unsupported value.
|
||||
@retval EFI_DEVICE_ERROR The serial device is not functioning correctly (no return).
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
SerialSetAttributes (
|
||||
IN EFI_SERIAL_IO_PROTOCOL *This,
|
||||
IN UINT64 BaudRate,
|
||||
IN UINT32 ReceiveFifoDepth,
|
||||
IN UINT32 Timeout,
|
||||
IN EFI_PARITY_TYPE Parity,
|
||||
IN UINT8 DataBits,
|
||||
IN EFI_STOP_BITS_TYPE StopBits
|
||||
);
|
||||
|
||||
/**
|
||||
Set Control Bits.
|
||||
|
||||
@param[in] This Pointer to EFI_SERIAL_IO_PROTOCOL.
|
||||
@param[in] Control Control bits that can be settable.
|
||||
|
||||
@retval EFI_SUCCESS New Control bits were set successfully.
|
||||
@retval EFI_UNSUPPORTED The Control bits wanted to set are not supported.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
SerialSetControl (
|
||||
IN EFI_SERIAL_IO_PROTOCOL *This,
|
||||
IN UINT32 Control
|
||||
);
|
||||
|
||||
/**
|
||||
Get ControlBits.
|
||||
|
||||
@param[in] This Pointer to EFI_SERIAL_IO_PROTOCOL.
|
||||
@param[out] Control Control signals of the serial device.
|
||||
|
||||
@retval EFI_SUCCESS Get Control signals successfully.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
SerialGetControl (
|
||||
IN EFI_SERIAL_IO_PROTOCOL *This,
|
||||
OUT UINT32 *Control
|
||||
);
|
||||
|
||||
/**
|
||||
Write the specified number of bytes to serial device.
|
||||
|
||||
@param[in] This Pointer to EFI_SERIAL_IO_PROTOCOL.
|
||||
@param[in, out] BufferSize On input the size of Buffer, on output the amount of
|
||||
data actually written.
|
||||
@param[in] Buffer The buffer of data to write.
|
||||
|
||||
@retval EFI_SUCCESS The data were written successfully.
|
||||
@retval EFI_DEVICE_ERROR The device reported an error.
|
||||
@retval EFI_TIMEOUT The write operation was stopped due to timeout.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
SerialWrite (
|
||||
IN EFI_SERIAL_IO_PROTOCOL *This,
|
||||
IN OUT UINTN *BufferSize,
|
||||
IN VOID *Buffer
|
||||
);
|
||||
|
||||
/**
|
||||
Read the specified number of bytes from serial device.
|
||||
|
||||
@param[in] This Pointer to EFI_SERIAL_IO_PROTOCOL.
|
||||
@param[in, out] BufferSize On input the size of Buffer, on output the amount of
|
||||
data returned in buffer.
|
||||
@param[out] Buffer The buffer to return the data into.
|
||||
|
||||
@retval EFI_SUCCESS The data were read successfully.
|
||||
@retval EFI_DEVICE_ERROR The device reported an error.
|
||||
@retval EFI_TIMEOUT The read operation was stopped due to timeout.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
SerialRead (
|
||||
IN EFI_SERIAL_IO_PROTOCOL *This,
|
||||
IN OUT UINTN *BufferSize,
|
||||
OUT VOID *Buffer
|
||||
);
|
||||
|
||||
//
|
||||
// Serial Driver Defaults
|
||||
//
|
||||
#define SERIAL_PORT_DEFAULT_RECEIVE_FIFO_DEPTH 1
|
||||
#define SERIAL_PORT_DEFAULT_TIMEOUT 1000000
|
||||
#define SERIAL_PORT_DEFAULT_CONTROL_MASK 0
|
||||
#define SERIAL_PORT_LOOPBACK_BUFFER_FULL BIT8
|
||||
|
||||
//
|
||||
// EFI_SERIAL_IO_MODE instance
|
||||
//
|
||||
EFI_SERIAL_IO_MODE mSerialIoMode = {
|
||||
SERIAL_PORT_DEFAULT_CONTROL_MASK,
|
||||
SERIAL_PORT_DEFAULT_TIMEOUT,
|
||||
0, // BaudRate
|
||||
SERIAL_PORT_DEFAULT_RECEIVE_FIFO_DEPTH,
|
||||
0, // DataBits
|
||||
0, // Parity
|
||||
0 // StopBits
|
||||
};
|
||||
|
||||
//
|
||||
// EFI_SERIAL_IO_PROTOCOL instance
|
||||
//
|
||||
EFI_SERIAL_IO_PROTOCOL mSerialIo = {
|
||||
SERIAL_IO_INTERFACE_REVISION,
|
||||
SerialReset,
|
||||
SerialSetAttributes,
|
||||
SerialSetControl,
|
||||
SerialGetControl,
|
||||
SerialWrite,
|
||||
SerialRead,
|
||||
&mSerialIoMode
|
||||
};
|
||||
|
||||
//
|
||||
// Serial IO Device Path definition
|
||||
//
|
||||
typedef struct {
|
||||
VENDOR_DEVICE_PATH VendorDevicePath;
|
||||
UART_DEVICE_PATH UartDevicePath;
|
||||
EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
|
||||
} SERIAL_IO_DEVICE_PATH;
|
||||
|
||||
//
|
||||
// Serial IO Device Patch instance
|
||||
//
|
||||
SERIAL_IO_DEVICE_PATH mSerialIoDevicePath = {
|
||||
{
|
||||
{
|
||||
HARDWARE_DEVICE_PATH,
|
||||
HW_VENDOR_DP,
|
||||
(UINT8) (sizeof (VENDOR_DEVICE_PATH)),
|
||||
(UINT8) ((sizeof (VENDOR_DEVICE_PATH)) >> 8)
|
||||
},
|
||||
EFI_DEBUG_AGENT_GUID,
|
||||
},
|
||||
{
|
||||
{
|
||||
MESSAGING_DEVICE_PATH,
|
||||
MSG_UART_DP,
|
||||
(UINT8) (sizeof (UART_DEVICE_PATH)),
|
||||
(UINT8) ((sizeof (UART_DEVICE_PATH)) >> 8)
|
||||
},
|
||||
0,
|
||||
0, // BaudRate
|
||||
0, // DataBits
|
||||
0, // Parity
|
||||
0, // StopBits
|
||||
},
|
||||
{
|
||||
END_DEVICE_PATH_TYPE,
|
||||
END_ENTIRE_DEVICE_PATH_SUBTYPE,
|
||||
{
|
||||
END_DEVICE_PATH_LENGTH,
|
||||
0
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
#define DEBGU_SERIAL_IO_FIFO_DEPTH 10
|
||||
//
|
||||
// Data buffer for Terminal input character and Debug Symbols.
|
||||
// The depth is DEBGU_SERIAL_IO_FIFO_DEPTH.
|
||||
// Fields:
|
||||
// First UINT8: The index of the first data in array Data[].
|
||||
// Last UINT8: The index, which you can put a new data into array Data[].
|
||||
// Surplus UINT8: Identify how many data you can put into array Data[].
|
||||
// Data[] UINT8: An array, which used to store data.
|
||||
//
|
||||
typedef struct {
|
||||
UINT8 First;
|
||||
UINT8 Last;
|
||||
UINT8 Surplus;
|
||||
UINT8 Data[DEBGU_SERIAL_IO_FIFO_DEPTH];
|
||||
} DEBUG_SERIAL_FIFO;
|
||||
|
||||
//
|
||||
// Global Varibles
|
||||
//
|
||||
EFI_HANDLE mSerialIoHandle = NULL;
|
||||
UINTN mLoopbackBuffer = 0;
|
||||
DEBUG_SERIAL_FIFO mSerialFifoForTerminal = {0, 0, DEBGU_SERIAL_IO_FIFO_DEPTH, { 0 }};
|
||||
DEBUG_SERIAL_FIFO mSerialFifoForDebug = {0, 0, DEBGU_SERIAL_IO_FIFO_DEPTH, { 0 }};
|
||||
|
||||
/**
|
||||
Detect whether specific FIFO is empty or not.
|
||||
|
||||
@param[in] Fifo A pointer to the Data Structure DEBUG_SERIAL_FIFO.
|
||||
|
||||
@return whether specific FIFO is empty or not.
|
||||
|
||||
**/
|
||||
BOOLEAN
|
||||
IsDebugTermianlFifoEmpty (
|
||||
IN DEBUG_SERIAL_FIFO *Fifo
|
||||
)
|
||||
{
|
||||
if (Fifo->Surplus == DEBGU_SERIAL_IO_FIFO_DEPTH) {
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
/**
|
||||
Detect whether specific FIFO is full or not.
|
||||
|
||||
@param[in] Fifo A pointer to the Data Structure DEBUG_SERIAL_FIFO.
|
||||
|
||||
@return whether specific FIFO is full or not.
|
||||
|
||||
**/
|
||||
BOOLEAN
|
||||
IsDebugTerminalFifoFull (
|
||||
IN DEBUG_SERIAL_FIFO *Fifo
|
||||
)
|
||||
|
||||
{
|
||||
if (Fifo->Surplus == 0) {
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
/**
|
||||
Add data to specific FIFO.
|
||||
|
||||
@param[in] Fifo A pointer to the Data Structure DEBUG_SERIAL_FIFO.
|
||||
@param[in] Data The data added to FIFO.
|
||||
|
||||
@retval EFI_SUCCESS Add data to specific FIFO successfully.
|
||||
@retval EFI_OUT_OF_RESOURCE Failed to add data because FIFO is already full.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
DebugTerminalFifoAdd (
|
||||
IN DEBUG_SERIAL_FIFO *Fifo,
|
||||
IN UINT8 Data
|
||||
)
|
||||
|
||||
{
|
||||
//
|
||||
// if FIFO full can not add data
|
||||
//
|
||||
if (IsDebugTerminalFifoFull (Fifo)) {
|
||||
return EFI_OUT_OF_RESOURCES;
|
||||
}
|
||||
//
|
||||
// FIFO is not full can add data
|
||||
//
|
||||
Fifo->Data[Fifo->Last] = Data;
|
||||
Fifo->Surplus--;
|
||||
Fifo->Last++;
|
||||
if (Fifo->Last == DEBGU_SERIAL_IO_FIFO_DEPTH) {
|
||||
Fifo->Last = 0;
|
||||
}
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
Remove data from specific FIFO.
|
||||
|
||||
@param[in] Fifo A pointer to the Data Structure DEBUG_SERIAL_FIFO.
|
||||
@param[out] Data The data removed from FIFO.
|
||||
|
||||
@retval EFI_SUCCESS Remove data from specific FIFO successfully.
|
||||
@retval EFI_OUT_OF_RESOURCE Failed to remove data because FIFO is empty.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
DebugTerminalFifoRemove (
|
||||
IN DEBUG_SERIAL_FIFO *Fifo,
|
||||
OUT UINT8 *Data
|
||||
)
|
||||
{
|
||||
//
|
||||
// if FIFO is empty, no data can remove
|
||||
//
|
||||
if (IsDebugTermianlFifoEmpty (Fifo)) {
|
||||
return EFI_OUT_OF_RESOURCES;
|
||||
}
|
||||
//
|
||||
// FIFO is not empty, can remove data
|
||||
//
|
||||
*Data = Fifo->Data[Fifo->First];
|
||||
Fifo->Surplus++;
|
||||
Fifo->First++;
|
||||
if (Fifo->First == DEBGU_SERIAL_IO_FIFO_DEPTH) {
|
||||
Fifo->First = 0;
|
||||
}
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
Notification function on EFI PCD protocol to install EFI Serial IO protocol based
|
||||
on Debug Communication Library.
|
||||
|
||||
@param[in] Event The event of notify protocol.
|
||||
@param[in] Context Notify event context.
|
||||
|
||||
**/
|
||||
VOID
|
||||
EFIAPI
|
||||
InstallSerialIoNotification (
|
||||
IN EFI_EVENT Event,
|
||||
IN VOID *Context
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
|
||||
//
|
||||
// Get Debug Port parameters from PCDs
|
||||
//
|
||||
mSerialIoDevicePath.UartDevicePath.BaudRate = PcdGet64 (PcdUartDefaultBaudRate);
|
||||
mSerialIoDevicePath.UartDevicePath.DataBits = PcdGet8 (PcdUartDefaultDataBits);
|
||||
mSerialIoDevicePath.UartDevicePath.Parity = PcdGet8 (PcdUartDefaultParity);
|
||||
mSerialIoDevicePath.UartDevicePath.StopBits = PcdGet8 (PcdUartDefaultStopBits);
|
||||
|
||||
mSerialIoMode.BaudRate = mSerialIoDevicePath.UartDevicePath.BaudRate;
|
||||
mSerialIoMode.DataBits = mSerialIoDevicePath.UartDevicePath.DataBits;
|
||||
mSerialIoMode.Parity = mSerialIoDevicePath.UartDevicePath.Parity;
|
||||
mSerialIoMode.StopBits = mSerialIoDevicePath.UartDevicePath.StopBits;
|
||||
|
||||
Status = gBS->InstallMultipleProtocolInterfaces (
|
||||
&mSerialIoHandle,
|
||||
&gEfiDevicePathProtocolGuid, &mSerialIoDevicePath,
|
||||
&gEfiSerialIoProtocolGuid, &mSerialIo,
|
||||
NULL
|
||||
);
|
||||
if (EFI_ERROR (Status)) {
|
||||
DEBUG ((EFI_D_ERROR, "Debug Agent: Failed to install EFI Serial IO Protocol on Debug Port!\n"));
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
Reset serial device.
|
||||
|
||||
@param[in] This Pointer to EFI_SERIAL_IO_PROTOCOL.
|
||||
|
||||
@retval EFI_SUCCESS Reset successfully.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
SerialReset (
|
||||
IN EFI_SERIAL_IO_PROTOCOL *This
|
||||
)
|
||||
{
|
||||
mSerialIoMode.ControlMask = SERIAL_PORT_DEFAULT_CONTROL_MASK;
|
||||
mLoopbackBuffer = 0;
|
||||
//
|
||||
// Not reset serial devcie hardware indeed.
|
||||
//
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
Set new attributes to a serial device.
|
||||
|
||||
@param[in] This Pointer to EFI_SERIAL_IO_PROTOCOL.
|
||||
@param[in] BaudRate The baudrate of the serial device.
|
||||
@param[in] ReceiveFifoDepth The depth of receive FIFO buffer.
|
||||
@param[in] Timeout The request timeout for a single char.
|
||||
@param[in] Parity The type of parity used in serial device.
|
||||
@param[in] DataBits Number of databits used in serial device.
|
||||
@param[in] StopBits Number of stopbits used in serial device.
|
||||
|
||||
@retval EFI_SUCCESS The new attributes were set.
|
||||
@retval EFI_INVALID_PARAMETER One or more attributes have an unsupported value.
|
||||
@retval EFI_DEVICE_ERROR The serial device is not functioning correctly (no return).
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
SerialSetAttributes (
|
||||
IN EFI_SERIAL_IO_PROTOCOL *This,
|
||||
IN UINT64 BaudRate,
|
||||
IN UINT32 ReceiveFifoDepth,
|
||||
IN UINT32 Timeout,
|
||||
IN EFI_PARITY_TYPE Parity,
|
||||
IN UINT8 DataBits,
|
||||
IN EFI_STOP_BITS_TYPE StopBits
|
||||
)
|
||||
{
|
||||
//
|
||||
// The Debug Communication Library does not support changing communications parameters, so unless
|
||||
// the request is to use the default value or the value the Debug Communication Library is already
|
||||
// using, then return EFI_INVALID_PARAMETER.
|
||||
//
|
||||
if (BaudRate != 0 && BaudRate != PcdGet64 (PcdUartDefaultBaudRate)) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
if (Parity != DefaultParity && Parity != PcdGet8 (PcdUartDefaultParity)) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
if (DataBits != 0 && DataBits != PcdGet8 (PcdUartDefaultDataBits)) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
if (StopBits != DefaultStopBits && StopBits != PcdGet8 (PcdUartDefaultStopBits)) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
//
|
||||
// Update the Timeout value in the mode structure based on the request.
|
||||
// The Debug Communication Library can not support a timeout on writes, but the timeout on
|
||||
// reads can be provided by this module.
|
||||
//
|
||||
if (Timeout == 0) {
|
||||
mSerialIoMode.Timeout = SERIAL_PORT_DEFAULT_TIMEOUT;
|
||||
} else {
|
||||
mSerialIoMode.Timeout = Timeout;
|
||||
}
|
||||
|
||||
//
|
||||
// Update the ReceiveFifoDepth value in the mode structure based on the request.
|
||||
// This module assumes that the Debug Communication Library uses a FIFO depth of
|
||||
// SERIAL_PORT_DEFAULT_RECEIVE_FIFO_DEPTH. The Debug Communication Library may actually be
|
||||
// using a larger FIFO, but there is no way to tell.
|
||||
//
|
||||
if (ReceiveFifoDepth == 0 || ReceiveFifoDepth >= SERIAL_PORT_DEFAULT_RECEIVE_FIFO_DEPTH) {
|
||||
mSerialIoMode.ReceiveFifoDepth = SERIAL_PORT_DEFAULT_RECEIVE_FIFO_DEPTH;
|
||||
} else {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
Set Control Bits.
|
||||
|
||||
@param[in] This Pointer to EFI_SERIAL_IO_PROTOCOL.
|
||||
@param[in] Control Control bits that can be settable.
|
||||
|
||||
@retval EFI_SUCCESS New Control bits were set successfully.
|
||||
@retval EFI_UNSUPPORTED The Control bits wanted to set are not supported.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
SerialSetControl (
|
||||
IN EFI_SERIAL_IO_PROTOCOL *This,
|
||||
IN UINT32 Control
|
||||
)
|
||||
{
|
||||
//
|
||||
// The only control bit supported by this module is software loopback.
|
||||
// If any other bit is set, then return an error
|
||||
//
|
||||
if ((Control & (~EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE)) != 0) {
|
||||
return EFI_UNSUPPORTED;
|
||||
}
|
||||
mSerialIoMode.ControlMask = Control;
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
Get ControlBits.
|
||||
|
||||
@param[in] This Pointer to EFI_SERIAL_IO_PROTOCOL.
|
||||
@param[out] Control Control signals of the serial device.
|
||||
|
||||
@retval EFI_SUCCESS Get Control signals successfully.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
SerialGetControl (
|
||||
IN EFI_SERIAL_IO_PROTOCOL *This,
|
||||
OUT UINT32 *Control
|
||||
)
|
||||
{
|
||||
DEBUG_PORT_HANDLE Handle;
|
||||
|
||||
Handle = GetDebugPortHandle ();
|
||||
|
||||
//
|
||||
// Always assume the output buffer is empty and the Debug Communication Library can process
|
||||
// more write requests.
|
||||
//
|
||||
*Control = mSerialIoMode.ControlMask | EFI_SERIAL_OUTPUT_BUFFER_EMPTY;
|
||||
|
||||
//
|
||||
// Check to see if the Terminal FIFO is empty and
|
||||
// check to see if the input buffer in the Debug Communication Library is empty
|
||||
//
|
||||
if (!IsDebugTermianlFifoEmpty (&mSerialFifoForTerminal) || DebugPortPollBuffer (Handle)) {
|
||||
*Control &= ~EFI_SERIAL_INPUT_BUFFER_EMPTY;
|
||||
}
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
Write the specified number of bytes to serial device.
|
||||
|
||||
@param[in] This Pointer to EFI_SERIAL_IO_PROTOCOL.
|
||||
@param[in, out] BufferSize On input the size of Buffer, on output the amount of
|
||||
data actually written.
|
||||
@param[in] Buffer The buffer of data to write.
|
||||
|
||||
@retval EFI_SUCCESS The data were written successfully.
|
||||
@retval EFI_DEVICE_ERROR The device reported an error.
|
||||
@retval EFI_TIMEOUT The write operation was stopped due to timeout.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
SerialWrite (
|
||||
IN EFI_SERIAL_IO_PROTOCOL *This,
|
||||
IN OUT UINTN *BufferSize,
|
||||
IN VOID *Buffer
|
||||
)
|
||||
{
|
||||
DEBUG_PORT_HANDLE Handle;
|
||||
|
||||
Handle = GetDebugPortHandle ();
|
||||
|
||||
if ((mSerialIoMode.ControlMask & EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE) != 0) {
|
||||
if (*BufferSize == 0) {
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
if ((mLoopbackBuffer & SERIAL_PORT_LOOPBACK_BUFFER_FULL) != 0) {
|
||||
*BufferSize = 0;
|
||||
return EFI_TIMEOUT;
|
||||
}
|
||||
mLoopbackBuffer = SERIAL_PORT_LOOPBACK_BUFFER_FULL | *(UINT8 *)Buffer;
|
||||
*BufferSize = 1;
|
||||
} else {
|
||||
*BufferSize = DebugPortWriteBuffer (Handle, Buffer, *BufferSize);
|
||||
}
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
Read the specified number of bytes from serial device.
|
||||
|
||||
@param[in] This Pointer to EFI_SERIAL_IO_PROTOCOL.
|
||||
@param[in, out] BufferSize On input the size of Buffer, on output the amount of
|
||||
data returned in buffer.
|
||||
@param[out] Buffer The buffer to return the data into.
|
||||
|
||||
@retval EFI_SUCCESS The data were read successfully.
|
||||
@retval EFI_DEVICE_ERROR The device reported an error.
|
||||
@retval EFI_TIMEOUT The read operation was stopped due to timeout.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
SerialRead (
|
||||
IN EFI_SERIAL_IO_PROTOCOL *This,
|
||||
IN OUT UINTN *BufferSize,
|
||||
OUT VOID *Buffer
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
UINTN Index;
|
||||
UINT8 *Uint8Buffer;
|
||||
BOOLEAN OldInterruptState;
|
||||
DEBUG_PORT_HANDLE Handle;
|
||||
UINT8 Data;
|
||||
|
||||
Handle = GetDebugPortHandle ();
|
||||
|
||||
//
|
||||
// Save and disable Debug Timer interrupt to avoid it to access Debug Port
|
||||
//
|
||||
OldInterruptState = SaveAndSetDebugTimerInterrupt (FALSE);
|
||||
|
||||
Uint8Buffer = (UINT8 *)Buffer;
|
||||
if ((mSerialIoMode.ControlMask & EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE) != 0) {
|
||||
if ((mLoopbackBuffer & SERIAL_PORT_LOOPBACK_BUFFER_FULL) == 0) {
|
||||
return EFI_TIMEOUT;
|
||||
}
|
||||
*Uint8Buffer = (UINT8)(mLoopbackBuffer & 0xff);
|
||||
mLoopbackBuffer = 0;
|
||||
*BufferSize = 1;
|
||||
} else {
|
||||
for (Index = 0; Index < *BufferSize; Index++) {
|
||||
//
|
||||
// Read input character from terminal FIFO firstly
|
||||
//
|
||||
Status = DebugTerminalFifoRemove (&mSerialFifoForTerminal, &Data);
|
||||
if (Status == EFI_SUCCESS) {
|
||||
*Uint8Buffer = Data;
|
||||
Uint8Buffer ++;
|
||||
continue;
|
||||
}
|
||||
//
|
||||
// Read the input character from Debug Port
|
||||
//
|
||||
if (!DebugPortPollBuffer (Handle)) {
|
||||
break;
|
||||
}
|
||||
DebugPortReadBuffer (Handle, &Data, 1, 0);
|
||||
|
||||
if (Data== DEBUG_STARTING_SYMBOL_ATTACH ||
|
||||
Data == DEBUG_STARTING_SYMBOL_BREAK) {
|
||||
//
|
||||
// Add the debug symbol into Debug FIFO
|
||||
//
|
||||
DebugTerminalFifoAdd (&mSerialFifoForDebug, Data);
|
||||
} else {
|
||||
*Uint8Buffer = Data;
|
||||
Uint8Buffer ++;
|
||||
}
|
||||
}
|
||||
*BufferSize = (UINTN)Uint8Buffer - (UINTN)Buffer;
|
||||
}
|
||||
|
||||
//
|
||||
// Restore Debug Timer interrupt
|
||||
//
|
||||
SaveAndSetDebugTimerInterrupt (OldInterruptState);
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
Read the Attach/Break-in symbols from the debug port.
|
||||
|
||||
@param[in] Handle Pointer to Debug Port handle.
|
||||
@param[out] BreakSymbol Returned break symbol.
|
||||
|
||||
@retval EFI_SUCCESS Read the symbol in BreakSymbol.
|
||||
@retval EFI_NOT_FOUND No read the break symbol.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
DebugReadBreakSymbol (
|
||||
IN DEBUG_PORT_HANDLE Handle,
|
||||
OUT UINT8 *BreakSymbol
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
UINT8 Data;
|
||||
|
||||
Status = DebugTerminalFifoRemove (&mSerialFifoForDebug, &Data);
|
||||
if (Status != EFI_SUCCESS) {
|
||||
if (!DebugPortPollBuffer (Handle)) {
|
||||
//
|
||||
// No data in Debug Port buffer.
|
||||
//
|
||||
return EFI_NOT_FOUND;
|
||||
} else {
|
||||
//
|
||||
// Read one character from Debug Port.
|
||||
//
|
||||
DebugPortReadBuffer (Handle, &Data, 1, 0);
|
||||
if ((Data != DEBUG_STARTING_SYMBOL_ATTACH) && (Data != DEBUG_STARTING_SYMBOL_BREAK)) {
|
||||
//
|
||||
// If the data is not Break symbol, add it into Terminal FIFO
|
||||
//
|
||||
DebugTerminalFifoAdd (&mSerialFifoForTerminal, Data);
|
||||
return EFI_NOT_FOUND;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
*BreakSymbol = Data;
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
|
@ -32,6 +32,7 @@
|
|||
[Sources.common]
|
||||
DxeDebugAgent/DxeDebugAgentLib.c
|
||||
DxeDebugAgent/DxeDebugAgentLib.h
|
||||
DxeDebugAgent/SerialIo.c
|
||||
DebugAgentCommon/DebugAgent.c
|
||||
DebugAgentCommon/DebugAgent.h
|
||||
DebugAgentCommon/DebugTimer.c
|
||||
|
|
@ -44,8 +45,6 @@
|
|||
DebugAgentCommon/Ia32/AsmFuncs.asm | MSFT
|
||||
DebugAgentCommon/Ia32/ArchDebugSupport.h
|
||||
DebugAgentCommon/Ia32/ArchDebugSupport.c
|
||||
DebugAgentCommon/Ia32/ArchReadGroupRegister.c
|
||||
DebugAgentCommon/Ia32/ArchRegisters.h
|
||||
DebugAgentCommon/Ia32/DebugException.h
|
||||
|
||||
[Sources.X64]
|
||||
|
|
@ -53,8 +52,6 @@
|
|||
DebugAgentCommon/X64/AsmFuncs.asm | MSFT
|
||||
DebugAgentCommon/X64/ArchDebugSupport.h
|
||||
DebugAgentCommon/X64/ArchDebugSupport.c
|
||||
DebugAgentCommon/X64/ArchReadGroupRegister.c
|
||||
DebugAgentCommon/X64/ArchRegisters.h
|
||||
DebugAgentCommon/X64/DebugException.h
|
||||
|
||||
[Packages]
|
||||
|
|
@ -77,12 +74,22 @@
|
|||
MemoryAllocationLib
|
||||
LocalApicLib
|
||||
TimerLib
|
||||
PrintLib
|
||||
|
||||
[Guids]
|
||||
gEfiDebugAgentGuid ## PRODUCES ## Configuration Table
|
||||
gEfiDebugAgentGuid ## CONSUMES ## HOB
|
||||
|
||||
[Protocols]
|
||||
gEfiSerialIoProtocolGuid ## PRODUCES
|
||||
gEfiDevicePathProtocolGuid ## PRODUCES
|
||||
gEfiPcdProtocolGuid ## NOTIFY
|
||||
|
||||
[Pcd]
|
||||
gEfiMdePkgTokenSpaceGuid.PcdFSBClock ## CONSUMES
|
||||
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate ## CONSUMES
|
||||
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits ## CONSUMES
|
||||
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity ## CONSUMES
|
||||
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits ## CONSUMES
|
||||
gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdExceptionsIgnoredByDebugger ## CONSUMES
|
||||
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/** @file
|
||||
SEC Core Debug Agent Library instance implementition.
|
||||
|
||||
Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>
|
||||
Copyright (c) 2010 - 2012, Intel Corporation. All rights reserved.<BR>
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
|
|
@ -16,6 +16,36 @@
|
|||
|
||||
CONST BOOLEAN MultiProcessorDebugSupport = FALSE;
|
||||
|
||||
/**
|
||||
Read the Attach/Break-in symbols from the debug port.
|
||||
|
||||
@param[in] Handle Pointer to Debug Port handle.
|
||||
@param[out] BreakSymbol Returned break symbol.
|
||||
|
||||
@retval EFI_SUCCESS Read the symbol in BreakSymbol.
|
||||
@retval EFI_NOT_FOUND No read the break symbol.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
DebugReadBreakSymbol (
|
||||
IN DEBUG_PORT_HANDLE Handle,
|
||||
OUT UINT8 *BreakSymbol
|
||||
)
|
||||
{
|
||||
*BreakSymbol = 0;
|
||||
//
|
||||
// If Debug Port buffer has data, read it till it was break symbol or Debug Port buffer emty.
|
||||
//
|
||||
while (DebugPortPollBuffer (Handle)) {
|
||||
DebugPortReadBuffer (Handle, BreakSymbol, 1, 0);
|
||||
if (*BreakSymbol == DEBUG_STARTING_SYMBOL_ATTACH || *BreakSymbol == DEBUG_STARTING_SYMBOL_BREAK) {
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
}
|
||||
|
||||
return EFI_NOT_FOUND;
|
||||
}
|
||||
|
||||
/**
|
||||
Get pointer to Mailbox from IDT entry before memory is ready.
|
||||
|
||||
|
|
@ -230,7 +260,7 @@ InitializeDebugAgent (
|
|||
//
|
||||
// Memory has been ready
|
||||
//
|
||||
if (IsHostConnected()) {
|
||||
if (IsHostAttached()) {
|
||||
//
|
||||
// Trigger one software interrupt to inform HOST
|
||||
//
|
||||
|
|
@ -240,7 +270,8 @@ InitializeDebugAgent (
|
|||
DebugAgentContext = (DEBUG_AGENT_CONTEXT_POSTMEM_SEC *) Context;
|
||||
|
||||
Mailbox = (DEBUG_AGENT_MAILBOX *) GetMailboxPointerInIdtEntry ();
|
||||
Mailbox->DebugPortHandle = Mailbox->DebugPortHandle + DebugAgentContext->StackMigrateOffset;
|
||||
Mailbox->DebugPortHandle = (UINT64)(UINT32)(Mailbox->DebugPortHandle + DebugAgentContext->StackMigrateOffset);
|
||||
Mailbox->DebugFlag.MemoryReady = 1;
|
||||
|
||||
Mailbox = BuildMailboxHob ();
|
||||
Mailbox = (DEBUG_AGENT_MAILBOX *) ((UINTN) Mailbox + DebugAgentContext->HeapMigrateOffset);
|
||||
|
|
@ -305,7 +336,7 @@ InitializeDebugAgentPhase2 (
|
|||
//
|
||||
Phase2Context = (DEBUG_AGENT_PHASE2_CONTEXT *) Context;
|
||||
SecCoreData = (EFI_SEC_PEI_HAND_OFF *)Phase2Context->Context;
|
||||
if ((UINTN)SecCoreData->TemporaryRamBase < BASE_128MB && IsHostConnected ()) {
|
||||
if ((UINTN)SecCoreData->TemporaryRamBase < BASE_128MB && IsHostAttached ()) {
|
||||
TriggerSoftInterrupt (MEMORY_READY_SIGNATURE);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -42,8 +42,6 @@
|
|||
DebugAgentCommon/Ia32/AsmFuncs.asm | MSFT
|
||||
DebugAgentCommon/Ia32/ArchDebugSupport.h
|
||||
DebugAgentCommon/Ia32/ArchDebugSupport.c
|
||||
DebugAgentCommon/Ia32/ArchReadGroupRegister.c
|
||||
DebugAgentCommon/Ia32/ArchRegisters.h
|
||||
DebugAgentCommon/Ia32/DebugException.h
|
||||
|
||||
[Sources.X64]
|
||||
|
|
@ -51,8 +49,6 @@
|
|||
DebugAgentCommon/X64/AsmFuncs.asm | MSFT
|
||||
DebugAgentCommon/X64/ArchDebugSupport.h
|
||||
DebugAgentCommon/X64/ArchDebugSupport.c
|
||||
DebugAgentCommon/X64/ArchReadGroupRegister.c
|
||||
DebugAgentCommon/X64/ArchRegisters.h
|
||||
DebugAgentCommon/X64/DebugException.h
|
||||
|
||||
[Packages]
|
||||
|
|
@ -73,6 +69,7 @@
|
|||
LocalApicLib
|
||||
DebugLib
|
||||
TimerLib
|
||||
PrintLib
|
||||
|
||||
[Guids]
|
||||
gEfiDebugAgentGuid ## PRODUCES ## HOB
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/** @file
|
||||
Debug Agent library implementition.
|
||||
|
||||
Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
|
||||
Copyright (c) 2010 - 2012, Intel Corporation. All rights reserved.<BR>
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
|
|
@ -19,6 +19,27 @@ DEBUG_AGENT_MAILBOX mLocalMailbox;
|
|||
UINTN mSavedDebugRegisters[6];
|
||||
CONST BOOLEAN MultiProcessorDebugSupport = FALSE;
|
||||
|
||||
/**
|
||||
Read the Attach/Break-in symbols from the debug port.
|
||||
|
||||
@param[in] Handle Pointer to Debug Port handle.
|
||||
@param[out] BreakSymbol Returned break symbol.
|
||||
|
||||
@retval EFI_SUCCESS Read the symbol in BreakSymbol.
|
||||
@retval EFI_NOT_FOUND No read the break symbol.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
DebugReadBreakSymbol (
|
||||
IN DEBUG_PORT_HANDLE Handle,
|
||||
OUT UINT8 *BreakSymbol
|
||||
)
|
||||
{
|
||||
//
|
||||
// Smm instance has no debug timer to poll break symbol.
|
||||
//
|
||||
return EFI_NOT_FOUND;
|
||||
}
|
||||
|
||||
/**
|
||||
Get Debug Agent Mailbox pointer.
|
||||
|
|
@ -137,7 +158,7 @@ InitializeDebugAgent (
|
|||
DebugPortHandle = (UINT64) (UINTN)DebugPortInitialize ((DEBUG_PORT_HANDLE) (UINTN)mMailboxPointer->DebugPortHandle, NULL);
|
||||
mMailboxPointer->DebugPortHandle = DebugPortHandle;
|
||||
|
||||
if (mMailboxPointer->DebugFlag.Bits.BreakOnNextSmi == 1) {
|
||||
if (mMailboxPointer->DebugFlag.BreakOnNextSmi == 1) {
|
||||
//
|
||||
// If SMM entry break is set, SMM code will be break at here.
|
||||
//
|
||||
|
|
|
|||
|
|
@ -42,8 +42,6 @@
|
|||
DebugAgentCommon/Ia32/AsmFuncs.asm | MSFT
|
||||
DebugAgentCommon/Ia32/ArchDebugSupport.h
|
||||
DebugAgentCommon/Ia32/ArchDebugSupport.c
|
||||
DebugAgentCommon/Ia32/ArchReadGroupRegister.c
|
||||
DebugAgentCommon/Ia32/ArchRegisters.h
|
||||
DebugAgentCommon/Ia32/DebugException.h
|
||||
|
||||
[Sources.X64]
|
||||
|
|
@ -51,8 +49,6 @@
|
|||
DebugAgentCommon/X64/AsmFuncs.asm | MSFT
|
||||
DebugAgentCommon/X64/ArchDebugSupport.h
|
||||
DebugAgentCommon/X64/ArchDebugSupport.c
|
||||
DebugAgentCommon/X64/ArchReadGroupRegister.c
|
||||
DebugAgentCommon/X64/ArchRegisters.h
|
||||
DebugAgentCommon/X64/DebugException.h
|
||||
|
||||
[Packages]
|
||||
|
|
@ -72,6 +68,7 @@
|
|||
SynchronizationLib
|
||||
LocalApicLib
|
||||
TimerLib
|
||||
PrintLib
|
||||
|
||||
[Guids]
|
||||
gEfiDebugAgentGuid ## CONSUMES ## Configuration Table
|
||||
|
|
|
|||
|
|
@ -99,6 +99,15 @@ typedef struct _USB_DEBUG_PORT_REGISTER {
|
|||
UINT8 Reserved3;
|
||||
}USB_DEBUG_PORT_REGISTER;
|
||||
|
||||
//
|
||||
// The state machine of usb debug port
|
||||
//
|
||||
#define USBDBG_NO_DEV 0 // No device present at debug port
|
||||
#define USBDBG_NO_DBG_CAB 1 // The device attached is not usb debug cable
|
||||
#define USBDBG_DBG_CAB 2 // The device attached is usb debug cable
|
||||
#define USBDBG_INIT_DONE 4 // The usb debug cable device is initialized
|
||||
#define USBDBG_RESET 8 // The system is reset
|
||||
|
||||
#pragma pack(1)
|
||||
//
|
||||
// The internal data structure of DEBUG_PORT_HANDLE, which stores some
|
||||
|
|
@ -109,7 +118,7 @@ typedef struct _USB_DEBUG_PORT_HANDLE{
|
|||
// The usb debug port memory BAR number in EHCI configuration space.
|
||||
//
|
||||
UINT8 DebugPortBarNumber;
|
||||
BOOLEAN Initialized;
|
||||
UINT8 Initialized;
|
||||
//
|
||||
// The offset of usb debug port registers in EHCI memory range.
|
||||
//
|
||||
|
|
@ -117,11 +126,11 @@ typedef struct _USB_DEBUG_PORT_HANDLE{
|
|||
//
|
||||
// The usb debug port memory BAR address.
|
||||
//
|
||||
UINTN UsbDebugPortMemoryBase;
|
||||
UINT32 UsbDebugPortMemoryBase;
|
||||
//
|
||||
// The EHCI memory BAR address.
|
||||
//
|
||||
UINTN EhciMemoryBase;
|
||||
UINT32 EhciMemoryBase;
|
||||
//
|
||||
// The Bulk In endpoint toggle bit.
|
||||
//
|
||||
|
|
@ -289,7 +298,17 @@ UsbDebugPortIn (
|
|||
//
|
||||
// Wait for completing the request
|
||||
//
|
||||
while ((MmioRead32((UINTN)&DebugPortRegister->ControlStatus) & (UINT32)BIT16) == 0);
|
||||
while ((MmioRead32((UINTN)&DebugPortRegister->ControlStatus) & (UINT32)BIT16) == 0) {
|
||||
if ((MmioRead32((UINTN)&DebugPortRegister->ControlStatus) & (USB_DEBUG_PORT_OWNER | USB_DEBUG_PORT_IN_USE | USB_DEBUG_PORT_ENABLE))
|
||||
!= (USB_DEBUG_PORT_OWNER | USB_DEBUG_PORT_IN_USE | USB_DEBUG_PORT_ENABLE)) {
|
||||
return RETURN_DEVICE_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// Clearing DONE bit by writing 1
|
||||
//
|
||||
MmioOr32((UINTN)&DebugPortRegister->ControlStatus, BIT16);
|
||||
|
||||
//
|
||||
// Check if the request is executed successfully or not.
|
||||
|
|
@ -380,7 +399,17 @@ UsbDebugPortOut (
|
|||
//
|
||||
// Wait for completing the request
|
||||
//
|
||||
while ((MmioRead32((UINTN)&DebugPortRegister->ControlStatus) & BIT16) == 0);
|
||||
while ((MmioRead32((UINTN)&DebugPortRegister->ControlStatus) & BIT16) == 0) {
|
||||
if ((MmioRead32((UINTN)&DebugPortRegister->ControlStatus) & (USB_DEBUG_PORT_OWNER | USB_DEBUG_PORT_IN_USE | USB_DEBUG_PORT_ENABLE))
|
||||
!= (USB_DEBUG_PORT_OWNER | USB_DEBUG_PORT_IN_USE | USB_DEBUG_PORT_ENABLE)) {
|
||||
return RETURN_DEVICE_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// Clearing DONE bit by writing 1
|
||||
//
|
||||
MmioOr32((UINTN)&DebugPortRegister->ControlStatus, BIT16);
|
||||
|
||||
//
|
||||
// Check if the request is executed successfully or not.
|
||||
|
|
@ -498,8 +527,8 @@ NeedReinitializeHardware(
|
|||
)
|
||||
{
|
||||
UINT16 PciCmd;
|
||||
UINTN UsbDebugPortMemoryBase;
|
||||
UINTN EhciMemoryBase;
|
||||
UINT32 UsbDebugPortMemoryBase;
|
||||
UINT32 EhciMemoryBase;
|
||||
BOOLEAN Status;
|
||||
USB_DEBUG_PORT_REGISTER *UsbDebugPortRegister;
|
||||
|
||||
|
|
@ -522,15 +551,23 @@ NeedReinitializeHardware(
|
|||
//
|
||||
PciCmd = PciRead16 (PcdGet32(PcdUsbEhciPciAddress) + PCI_COMMAND_OFFSET);
|
||||
if (((PciCmd & EFI_PCI_COMMAND_MEMORY_SPACE) == 0) || ((PciCmd & EFI_PCI_COMMAND_BUS_MASTER) == 0)) {
|
||||
PciCmd |= EFI_PCI_COMMAND_MEMORY_SPACE | EFI_PCI_COMMAND_BUS_MASTER;
|
||||
PciWrite16(PcdGet32(PcdUsbEhciPciAddress) + PCI_COMMAND_OFFSET, PciCmd);
|
||||
Status = TRUE;
|
||||
}
|
||||
|
||||
//
|
||||
// Check if the debug port is enabled and owned by myself.
|
||||
// If the owner and in_use bit is not set, it means system is doing cold/warm boot or EHCI host controller is reset by system software.
|
||||
//
|
||||
UsbDebugPortRegister = (USB_DEBUG_PORT_REGISTER *)(Handle->UsbDebugPortMemoryBase + Handle->DebugPortOffset);
|
||||
if ((MmioRead32((UINTN)&UsbDebugPortRegister->ControlStatus) &
|
||||
(USB_DEBUG_PORT_OWNER | USB_DEBUG_PORT_ENABLE | USB_DEBUG_PORT_IN_USE)) == 0) {
|
||||
UsbDebugPortRegister = (USB_DEBUG_PORT_REGISTER *)(UINTN)(Handle->UsbDebugPortMemoryBase + Handle->DebugPortOffset);
|
||||
if ((MmioRead32((UINTN)&UsbDebugPortRegister->ControlStatus) & (USB_DEBUG_PORT_OWNER | USB_DEBUG_PORT_ENABLE | USB_DEBUG_PORT_IN_USE))
|
||||
!= (USB_DEBUG_PORT_OWNER | USB_DEBUG_PORT_ENABLE | USB_DEBUG_PORT_IN_USE)) {
|
||||
Status = TRUE;
|
||||
}
|
||||
|
||||
if (Handle->Initialized == USBDBG_RESET) {
|
||||
Status = TRUE;
|
||||
} else if (Handle->Initialized != USBDBG_INIT_DONE) {
|
||||
Status = TRUE;
|
||||
}
|
||||
return Status;
|
||||
|
|
@ -568,127 +605,145 @@ InitializeUsbDebugHardware (
|
|||
UINT8 DebugPortNumber;
|
||||
UINT8 Length;
|
||||
|
||||
UsbDebugPortRegister = (USB_DEBUG_PORT_REGISTER *)(Handle->UsbDebugPortMemoryBase + Handle->DebugPortOffset);
|
||||
UsbDebugPortRegister = (USB_DEBUG_PORT_REGISTER *)(UINTN)(Handle->UsbDebugPortMemoryBase + Handle->DebugPortOffset);
|
||||
PciCmd = PciRead16 (PcdGet32(PcdUsbEhciPciAddress) + PCI_COMMAND_OFFSET);
|
||||
UsbHCSParam = (UINT32 *)(Handle->EhciMemoryBase + 0x04);
|
||||
UsbCmd = (UINT32 *)(Handle->EhciMemoryBase + 0x20);
|
||||
UsbStatus = (UINT32 *)(Handle->EhciMemoryBase + 0x24);
|
||||
UsbHCSParam = (UINT32 *)(UINTN)(Handle->EhciMemoryBase + 0x04);
|
||||
UsbCmd = (UINT32 *)(UINTN)(Handle->EhciMemoryBase + 0x20);
|
||||
UsbStatus = (UINT32 *)(UINTN)(Handle->EhciMemoryBase + 0x24);
|
||||
|
||||
//
|
||||
// initialize the data toggle used by bulk in/out endpoint.
|
||||
// Check if the debug port is enabled and owned by myself.
|
||||
//
|
||||
Handle->BulkInToggle = 0;
|
||||
Handle->BulkOutToggle = 0;
|
||||
if (((MmioRead32((UINTN)&UsbDebugPortRegister->ControlStatus) & (USB_DEBUG_PORT_OWNER | USB_DEBUG_PORT_IN_USE))
|
||||
!= (USB_DEBUG_PORT_OWNER | USB_DEBUG_PORT_IN_USE)) || (Handle->Initialized == USBDBG_RESET)) {
|
||||
//
|
||||
// If the host controller is not halted, then halt it.
|
||||
//
|
||||
if ((MmioRead32((UINTN)UsbStatus) & BIT12) == 0) {
|
||||
MmioAnd32((UINTN)UsbCmd, (UINT32)~BIT0);
|
||||
while ((MmioRead32((UINTN)UsbStatus) & BIT12) == 0);
|
||||
}
|
||||
//
|
||||
// reset the host controller.
|
||||
//
|
||||
MmioOr32((UINTN)UsbCmd, BIT1);
|
||||
//
|
||||
// ensure that the host controller is reset.
|
||||
//
|
||||
while (MmioRead32((UINTN)UsbCmd) & BIT1);
|
||||
|
||||
//
|
||||
// Enable Ehci Memory Space Access
|
||||
//
|
||||
if (((PciCmd & EFI_PCI_COMMAND_MEMORY_SPACE) == 0) || ((PciCmd & EFI_PCI_COMMAND_BUS_MASTER) == 0)) {
|
||||
PciCmd |= EFI_PCI_COMMAND_MEMORY_SPACE | EFI_PCI_COMMAND_BUS_MASTER;
|
||||
PciWrite16(PcdGet32(PcdUsbEhciPciAddress) + PCI_COMMAND_OFFSET, PciCmd);
|
||||
//
|
||||
// Start the host controller if it's not running
|
||||
//
|
||||
if (MmioRead32((UINTN)UsbStatus) & BIT12) {
|
||||
MmioOr32((UINTN)UsbCmd, BIT0);
|
||||
// ensure that the host controller is started (HALTED bit must be cleared)
|
||||
while (MmioRead32((UINTN)UsbStatus) & BIT12);
|
||||
}
|
||||
|
||||
//
|
||||
// First get the ownership of port 0.
|
||||
//
|
||||
MmioOr32((UINTN)&UsbDebugPortRegister->ControlStatus, USB_DEBUG_PORT_OWNER | USB_DEBUG_PORT_IN_USE);
|
||||
|
||||
MicroSecondDelay (200000);
|
||||
}
|
||||
|
||||
//
|
||||
// If the host controller is not halted, then halt it.
|
||||
//
|
||||
if ((MmioRead32((UINTN)UsbStatus) & BIT12) == 0) {
|
||||
MmioAnd32((UINTN)UsbCmd, (UINT32)~BIT0);
|
||||
while ((MmioRead32((UINTN)UsbStatus) & BIT12) == 0);
|
||||
}
|
||||
//
|
||||
// reset the host controller.
|
||||
//
|
||||
MmioOr32((UINTN)UsbCmd, BIT1);
|
||||
//
|
||||
// ensure that the host controller is reset.
|
||||
//
|
||||
while (MmioRead32((UINTN)UsbCmd) & BIT1);
|
||||
|
||||
//
|
||||
// Start the host controller if it's not running
|
||||
//
|
||||
if (MmioRead32((UINTN)UsbStatus) & BIT12) {
|
||||
MmioOr32((UINTN)UsbCmd, BIT0);
|
||||
// ensure that the host controller is started (HALTED bit must be cleared)
|
||||
while (MmioRead32((UINTN)UsbStatus) & BIT12);
|
||||
}
|
||||
|
||||
//
|
||||
// First get the ownership of port 0.
|
||||
//
|
||||
MmioOr32((UINTN)&UsbDebugPortRegister->ControlStatus, USB_DEBUG_PORT_OWNER);
|
||||
|
||||
MicroSecondDelay (200000);
|
||||
|
||||
//
|
||||
// Find out which port is used as debug port.
|
||||
//
|
||||
DebugPortNumber = (UINT8)((MmioRead32((UINTN)UsbHCSParam) & 0x00F00000) >> 20);
|
||||
//
|
||||
// Should find a non low-speed device is connected
|
||||
// Should find a device is connected at debug port
|
||||
//
|
||||
PortStatus = (UINT32 *)(Handle->EhciMemoryBase + 0x64 + (DebugPortNumber - 1) * 4);
|
||||
if (!(MmioRead32((UINTN)PortStatus) & BIT0) || ((MmioRead32((UINTN)PortStatus) & USB_PORT_LINE_STATUS_MASK) == USB_PORT_LINE_STATUS_LS)) {
|
||||
PortStatus = (UINT32 *)(UINTN)(Handle->EhciMemoryBase + 0x64 + (DebugPortNumber - 1) * 4);
|
||||
if (!(MmioRead32((UINTN)PortStatus) & BIT0)) {
|
||||
Handle->Initialized = USBDBG_NO_DEV;
|
||||
return RETURN_NOT_FOUND;
|
||||
}
|
||||
|
||||
//
|
||||
// Reset the debug port
|
||||
//
|
||||
MmioOr32((UINTN)PortStatus, BIT8);
|
||||
MicroSecondDelay (200000);
|
||||
MmioAnd32((UINTN)PortStatus, (UINT32)~BIT8);
|
||||
while (MmioRead32((UINTN)PortStatus) & BIT8);
|
||||
if (Handle->Initialized != USBDBG_INIT_DONE) {
|
||||
//
|
||||
// Reset the debug port
|
||||
//
|
||||
MmioOr32((UINTN)PortStatus, BIT8);
|
||||
MicroSecondDelay (500000);
|
||||
MmioAnd32((UINTN)PortStatus, (UINT32)~BIT8);
|
||||
while (MmioRead32((UINTN)PortStatus) & BIT8);
|
||||
|
||||
//
|
||||
// The port enabled bit should be set by HW.
|
||||
//
|
||||
if ((MmioRead32((UINTN)PortStatus) & BIT2) == 0) {
|
||||
return RETURN_DEVICE_ERROR;
|
||||
//
|
||||
// The port enabled bit should be set by HW.
|
||||
//
|
||||
if ((MmioRead32((UINTN)PortStatus) & BIT2) == 0) {
|
||||
Handle->Initialized = USBDBG_NO_DBG_CAB;
|
||||
return RETURN_DEVICE_ERROR;
|
||||
}
|
||||
|
||||
//
|
||||
// Enable Usb Debug Port Capability
|
||||
//
|
||||
MmioOr32((UINTN)&UsbDebugPortRegister->ControlStatus, USB_DEBUG_PORT_ENABLE);
|
||||
|
||||
//
|
||||
// initialize the data toggle used by bulk in/out endpoint.
|
||||
//
|
||||
Handle->BulkInToggle = 0;
|
||||
Handle->BulkOutToggle = 0;
|
||||
|
||||
//
|
||||
// set usb debug device address as 0x7F.
|
||||
//
|
||||
Status = UsbDebugPortControlTransfer (UsbDebugPortRegister, &mSetDebugAddress, 0x0, 0x0, NULL, NULL);
|
||||
if (RETURN_ERROR(Status)) {
|
||||
//
|
||||
// The device can not work well.
|
||||
//
|
||||
Handle->Initialized = USBDBG_NO_DBG_CAB;
|
||||
return Status;
|
||||
}
|
||||
|
||||
//
|
||||
// Start to communicate with Usb Debug Device to see if the attached device is usb debug device or not.
|
||||
//
|
||||
Length = (UINT8)sizeof (USB_DEBUG_PORT_DESCRIPTOR);
|
||||
|
||||
//
|
||||
// Get debug descriptor.
|
||||
//
|
||||
Status = UsbDebugPortControlTransfer (UsbDebugPortRegister, &mGetDebugDescriptor, 0x7F, 0x0, (UINT8*)&UsbDebugPortDescriptor, &Length);
|
||||
if (RETURN_ERROR(Status)) {
|
||||
//
|
||||
// The device is not a usb debug device.
|
||||
//
|
||||
Handle->Initialized = USBDBG_NO_DBG_CAB;
|
||||
return Status;
|
||||
}
|
||||
|
||||
if (Length != sizeof(USB_DEBUG_PORT_DESCRIPTOR)) {
|
||||
Handle->Initialized = USBDBG_NO_DBG_CAB;
|
||||
return RETURN_DEVICE_ERROR;
|
||||
}
|
||||
|
||||
//
|
||||
// enable the usb debug feature.
|
||||
//
|
||||
Status = UsbDebugPortControlTransfer (UsbDebugPortRegister, &mSetDebugFeature, 0x7F, 0x0, NULL, NULL);
|
||||
if (RETURN_ERROR(Status)) {
|
||||
//
|
||||
// The device can not work well.
|
||||
//
|
||||
Handle->Initialized = USBDBG_NO_DBG_CAB;
|
||||
return Status;
|
||||
}
|
||||
|
||||
Handle->Initialized = USBDBG_DBG_CAB;
|
||||
}
|
||||
|
||||
//
|
||||
// Enable Usb Debug Port Capability
|
||||
// Set initialized flag
|
||||
//
|
||||
MmioOr32((UINTN)&UsbDebugPortRegister->ControlStatus, USB_DEBUG_PORT_ENABLE | USB_DEBUG_PORT_IN_USE);
|
||||
Handle->Initialized = USBDBG_INIT_DONE;
|
||||
|
||||
//
|
||||
// Start to communicate with Usb Debug Device to see if the attached device is usb debug device or not.
|
||||
//
|
||||
Length = (UINT8)sizeof (USB_DEBUG_PORT_DESCRIPTOR);
|
||||
|
||||
//
|
||||
// It's not a dedicated usb debug device, should use address 0 to get debug descriptor.
|
||||
//
|
||||
Status = UsbDebugPortControlTransfer (UsbDebugPortRegister, &mGetDebugDescriptor, 0x0, 0x0, (UINT8*)&UsbDebugPortDescriptor, &Length);
|
||||
if (RETURN_ERROR(Status)) {
|
||||
//
|
||||
// The device is not a usb debug device.
|
||||
//
|
||||
return Status;
|
||||
}
|
||||
|
||||
if (Length != sizeof(USB_DEBUG_PORT_DESCRIPTOR)) {
|
||||
return RETURN_DEVICE_ERROR;
|
||||
}
|
||||
|
||||
//
|
||||
// set usb debug device address as 0x7F.
|
||||
//
|
||||
Status = UsbDebugPortControlTransfer (UsbDebugPortRegister, &mSetDebugAddress, 0x0, 0x0, NULL, NULL);
|
||||
if (RETURN_ERROR(Status)) {
|
||||
//
|
||||
// The device can not work well.
|
||||
//
|
||||
return Status;
|
||||
}
|
||||
|
||||
//
|
||||
// enable the usb debug feature.
|
||||
//
|
||||
Status = UsbDebugPortControlTransfer (UsbDebugPortRegister, &mSetDebugFeature, 0x7F, 0x0, NULL, NULL);
|
||||
|
||||
return Status;
|
||||
return RETURN_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -744,13 +799,6 @@ DebugPortReadBuffer (
|
|||
UsbDebugPortHandle = (USB_DEBUG_PORT_HANDLE *)Handle;
|
||||
}
|
||||
|
||||
//
|
||||
// Check if debug port is ready
|
||||
//
|
||||
if (!UsbDebugPortHandle->Initialized) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (NeedReinitializeHardware(UsbDebugPortHandle)) {
|
||||
Status = InitializeUsbDebugHardware (UsbDebugPortHandle);
|
||||
if (RETURN_ERROR(Status)) {
|
||||
|
|
@ -758,7 +806,7 @@ DebugPortReadBuffer (
|
|||
}
|
||||
}
|
||||
|
||||
UsbDebugPortRegister = (USB_DEBUG_PORT_REGISTER *)(UsbDebugPortHandle->UsbDebugPortMemoryBase + UsbDebugPortHandle->DebugPortOffset);
|
||||
UsbDebugPortRegister = (USB_DEBUG_PORT_REGISTER *)(UINTN)(UsbDebugPortHandle->UsbDebugPortMemoryBase + UsbDebugPortHandle->DebugPortOffset);
|
||||
|
||||
//
|
||||
// First read data from buffer, then read debug port hw to get received data.
|
||||
|
|
@ -896,13 +944,6 @@ DebugPortWriteBuffer (
|
|||
UsbDebugPortHandle = (USB_DEBUG_PORT_HANDLE *)Handle;
|
||||
}
|
||||
|
||||
//
|
||||
// Check if debug port is ready
|
||||
//
|
||||
if (!UsbDebugPortHandle->Initialized) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (NeedReinitializeHardware(UsbDebugPortHandle)) {
|
||||
Status = InitializeUsbDebugHardware (UsbDebugPortHandle);
|
||||
if (RETURN_ERROR(Status)) {
|
||||
|
|
@ -910,7 +951,7 @@ DebugPortWriteBuffer (
|
|||
}
|
||||
}
|
||||
|
||||
UsbDebugPortRegister = (USB_DEBUG_PORT_REGISTER *)(UsbDebugPortHandle->UsbDebugPortMemoryBase + UsbDebugPortHandle->DebugPortOffset);
|
||||
UsbDebugPortRegister = (USB_DEBUG_PORT_REGISTER *)(UINTN)(UsbDebugPortHandle->UsbDebugPortMemoryBase + UsbDebugPortHandle->DebugPortOffset);
|
||||
|
||||
while ((Total < NumberOfBytes)) {
|
||||
if (NumberOfBytes - Total > USB_DEBUG_PORT_MAX_PACKET_SIZE) {
|
||||
|
|
@ -975,13 +1016,6 @@ DebugPortPollBuffer (
|
|||
UsbDebugPortHandle = (USB_DEBUG_PORT_HANDLE *)Handle;
|
||||
}
|
||||
|
||||
//
|
||||
// Check if debug port is ready
|
||||
//
|
||||
if (!UsbDebugPortHandle->Initialized) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (NeedReinitializeHardware(UsbDebugPortHandle)) {
|
||||
Status = InitializeUsbDebugHardware(UsbDebugPortHandle);
|
||||
if (RETURN_ERROR(Status)) {
|
||||
|
|
@ -997,7 +1031,7 @@ DebugPortPollBuffer (
|
|||
return TRUE;
|
||||
}
|
||||
|
||||
UsbDebugPortRegister = (USB_DEBUG_PORT_REGISTER *)(UsbDebugPortHandle->UsbDebugPortMemoryBase + UsbDebugPortHandle->DebugPortOffset);
|
||||
UsbDebugPortRegister = (USB_DEBUG_PORT_REGISTER *)(UINTN)(UsbDebugPortHandle->UsbDebugPortMemoryBase + UsbDebugPortHandle->DebugPortOffset);
|
||||
|
||||
UsbDebugPortRegister->TokenPid = INPUT_PID;
|
||||
if (UsbDebugPortHandle->BulkInToggle == 0) {
|
||||
|
|
@ -1020,7 +1054,12 @@ DebugPortPollBuffer (
|
|||
//
|
||||
// Wait for completing the request
|
||||
//
|
||||
while ((MmioRead32((UINTN)&UsbDebugPortRegister->ControlStatus) & (UINT32)BIT16) == 0);
|
||||
while ((MmioRead32((UINTN)&UsbDebugPortRegister->ControlStatus) & (UINT32)BIT16) == 0) {
|
||||
if ((MmioRead32((UINTN)&UsbDebugPortRegister->ControlStatus) & (USB_DEBUG_PORT_OWNER | USB_DEBUG_PORT_IN_USE | USB_DEBUG_PORT_ENABLE))
|
||||
!= (USB_DEBUG_PORT_OWNER | USB_DEBUG_PORT_IN_USE | USB_DEBUG_PORT_ENABLE)) {
|
||||
return FALSE;
|
||||
}
|
||||
}
|
||||
|
||||
if ((MmioRead32((UINTN)&UsbDebugPortRegister->ControlStatus)) & BIT6) {
|
||||
return FALSE;
|
||||
|
|
@ -1079,8 +1118,7 @@ DebugPortInitialize (
|
|||
{
|
||||
RETURN_STATUS Status;
|
||||
USB_DEBUG_PORT_HANDLE Handle;
|
||||
|
||||
if (Function == NULL && Context != NULL) {
|
||||
if (Function == NULL && Context != NULL) {
|
||||
return (DEBUG_PORT_HANDLE *) Context;
|
||||
}
|
||||
|
||||
|
|
@ -1088,7 +1126,7 @@ DebugPortInitialize (
|
|||
|
||||
Status = CalculateUsbDebugPortBar(&Handle.DebugPortOffset, &Handle.DebugPortBarNumber);
|
||||
if (RETURN_ERROR (Status)) {
|
||||
DEBUG ((EFI_D_ERROR, "USB Debug Port: the pci device pointed by PcdUsbEhciPciAddress is not EHCI host controller or does not support debug port capability!\n"));
|
||||
DEBUG ((EFI_D_ERROR, "UsbDbg: the pci device pointed by PcdUsbEhciPciAddress is not EHCI host controller or does not support debug port capability!\n"));
|
||||
goto Exit;
|
||||
}
|
||||
|
||||
|
|
@ -1112,16 +1150,16 @@ DebugPortInitialize (
|
|||
Handle.UsbDebugPortMemoryBase = 0xFFFFFC00 & PciRead32(PcdGet32(PcdUsbEhciPciAddress) + PCI_BASE_ADDRESSREG_OFFSET + Handle.DebugPortBarNumber * 4);
|
||||
}
|
||||
|
||||
Status = InitializeUsbDebugHardware (&Handle);
|
||||
if (RETURN_ERROR(Status)) {
|
||||
DEBUG ((EFI_D_ERROR, "USB Debug Port: Initialization failed, please check if USB debug cable is plugged into EHCI debug port correctly!\n"));
|
||||
goto Exit;
|
||||
}
|
||||
Handle.Initialized = USBDBG_RESET;
|
||||
|
||||
//
|
||||
// Set debug port initialized successfully flag
|
||||
//
|
||||
Handle.Initialized = TRUE;
|
||||
if (NeedReinitializeHardware(&Handle)) {
|
||||
DEBUG ((EFI_D_ERROR, "UsbDbg: Start EHCI debug port initialization!\n"));
|
||||
Status = InitializeUsbDebugHardware (&Handle);
|
||||
if (RETURN_ERROR(Status)) {
|
||||
DEBUG ((EFI_D_ERROR, "UsbDbg: Initialization failed, please check if USB debug cable is plugged into EHCI debug port correctly!\n"));
|
||||
goto Exit;
|
||||
}
|
||||
}
|
||||
|
||||
Exit:
|
||||
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/** @file
|
||||
PE/Coff Extra Action library instances.
|
||||
|
||||
Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
|
||||
Copyright (c) 2010 - 2012, Intel Corporation. All rights reserved.<BR>
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
|
|
@ -47,18 +47,19 @@ IsDrxEnabled (
|
|||
}
|
||||
|
||||
/**
|
||||
Performs additional actions after a PE/COFF image has been loaded and relocated.
|
||||
Common routine to report the PE/COFF image loading/relocating or unloading event.
|
||||
|
||||
If ImageContext is NULL, then ASSERT().
|
||||
|
||||
|
||||
@param ImageContext Pointer to the image context structure that describes the
|
||||
PE/COFF image that has already been loaded and relocated.
|
||||
PE/COFF image.
|
||||
@param Signature IMAGE_LOAD_SIGNATURE or IMAGE_UNLOAD_SIGNATURE.
|
||||
|
||||
**/
|
||||
VOID
|
||||
EFIAPI
|
||||
PeCoffLoaderRelocateImageExtraAction (
|
||||
IN OUT PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext
|
||||
PeCoffLoaderExtraActionCommon (
|
||||
IN OUT PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext,
|
||||
IN UINTN Signature
|
||||
)
|
||||
{
|
||||
BOOLEAN InterruptState;
|
||||
|
|
@ -94,7 +95,7 @@ PeCoffLoaderRelocateImageExtraAction (
|
|||
Cr4 = AsmReadCr4 ();
|
||||
|
||||
//
|
||||
// DR0 = IMAGE_LOAD_SIGNATURE
|
||||
// DR0 = Signature
|
||||
// DR1 = The address of the Null-terminated ASCII string for the PE/COFF image's PDB file name
|
||||
// DR2 = The pointer to the ImageContext structure
|
||||
// DR3 = IO_PORT_BREAKPOINT_ADDRESS
|
||||
|
|
@ -102,9 +103,9 @@ PeCoffLoaderRelocateImageExtraAction (
|
|||
// CR4 = Make sure DE(BIT3) is set
|
||||
//
|
||||
AsmWriteDr7 (0);
|
||||
AsmWriteDr0 (IMAGE_LOAD_SIGNATURE);
|
||||
AsmWriteDr1 ((UINTN)ImageContext->PdbPointer);
|
||||
AsmWriteDr2 ((UINTN)ImageContext);
|
||||
AsmWriteDr0 (Signature);
|
||||
AsmWriteDr1 ((UINTN) ImageContext->PdbPointer);
|
||||
AsmWriteDr2 ((UINTN) ImageContext);
|
||||
AsmWriteDr3 (IO_PORT_BREAKPOINT_ADDRESS);
|
||||
|
||||
LoadImageMethod = PcdGet8 (PcdDebugLoadImageMethod);
|
||||
|
|
@ -132,16 +133,20 @@ PeCoffLoaderRelocateImageExtraAction (
|
|||
// in the above exception handler
|
||||
//
|
||||
NewDr7 = AsmReadDr7 ();
|
||||
if (!IsDrxEnabled (0, NewDr7)) {
|
||||
if (!IsDrxEnabled (0, NewDr7) && (AsmReadDr0 () == 0 || AsmReadDr0 () == Signature)) {
|
||||
//
|
||||
// If user changed Dr3 (by setting HW bp in the above exception handler,
|
||||
// we will not set Dr0 to 0 in GO/STEP handler because the break cause is not IMAGE_LOAD/_UNLOAD.
|
||||
//
|
||||
AsmWriteDr0 (Dr0);
|
||||
}
|
||||
if (!IsDrxEnabled (1, NewDr7)) {
|
||||
if (!IsDrxEnabled (1, NewDr7) && (AsmReadDr1 () == (UINTN) ImageContext->PdbPointer)) {
|
||||
AsmWriteDr1 (Dr1);
|
||||
}
|
||||
if (!IsDrxEnabled (2, NewDr7)) {
|
||||
if (!IsDrxEnabled (2, NewDr7) && (AsmReadDr2 () == (UINTN) ImageContext)) {
|
||||
AsmWriteDr2 (Dr2);
|
||||
}
|
||||
if (!IsDrxEnabled (3, NewDr7)) {
|
||||
if (!IsDrxEnabled (3, NewDr7) && (AsmReadDr3 () == IO_PORT_BREAKPOINT_ADDRESS)) {
|
||||
AsmWriteDr3 (Dr3);
|
||||
}
|
||||
if (AsmReadCr4 () == (Cr4 | BIT3)) {
|
||||
|
|
@ -156,12 +161,26 @@ PeCoffLoaderRelocateImageExtraAction (
|
|||
SetInterruptState (InterruptState);
|
||||
}
|
||||
|
||||
/**
|
||||
Performs additional actions after a PE/COFF image has been loaded and relocated.
|
||||
|
||||
@param ImageContext Pointer to the image context structure that describes the
|
||||
PE/COFF image that has already been loaded and relocated.
|
||||
|
||||
**/
|
||||
VOID
|
||||
EFIAPI
|
||||
PeCoffLoaderRelocateImageExtraAction (
|
||||
IN OUT PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext
|
||||
)
|
||||
{
|
||||
PeCoffLoaderExtraActionCommon (ImageContext, IMAGE_LOAD_SIGNATURE);
|
||||
}
|
||||
|
||||
/**
|
||||
Performs additional actions just before a PE/COFF image is unloaded. Any resources
|
||||
that were allocated by PeCoffLoaderRelocateImageExtraAction() must be freed.
|
||||
|
||||
If ImageContext is NULL, then ASSERT().
|
||||
|
||||
@param ImageContext Pointer to the image context structure that describes the
|
||||
PE/COFF image that is being unloaded.
|
||||
|
||||
|
|
@ -172,98 +191,5 @@ PeCoffLoaderUnloadImageExtraAction (
|
|||
IN OUT PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext
|
||||
)
|
||||
{
|
||||
BOOLEAN InterruptState;
|
||||
UINTN Dr0;
|
||||
UINTN Dr1;
|
||||
UINTN Dr2;
|
||||
UINTN Dr3;
|
||||
UINTN Dr7;
|
||||
UINTN Cr4;
|
||||
UINTN NewDr7;
|
||||
UINT8 LoadImageMethod;
|
||||
UINT8 DebugAgentStatus;
|
||||
|
||||
ASSERT (ImageContext != NULL);
|
||||
|
||||
if (ImageContext->PdbPointer != NULL) {
|
||||
DEBUG((EFI_D_ERROR, " PDB = %a\n", ImageContext->PdbPointer));
|
||||
}
|
||||
|
||||
//
|
||||
// Disable interrupts and save the current interrupt state
|
||||
//
|
||||
InterruptState = SaveAndDisableInterrupts ();
|
||||
|
||||
//
|
||||
// Save Debug Register State
|
||||
//
|
||||
Dr0 = AsmReadDr0 ();
|
||||
Dr1 = AsmReadDr1 ();
|
||||
Dr2 = AsmReadDr2 ();
|
||||
Dr3 = AsmReadDr3 ();
|
||||
Dr7 = AsmReadDr7 ();
|
||||
Cr4 = AsmReadCr4 ();
|
||||
|
||||
//
|
||||
// DR0 = IMAGE_UNLOAD_SIGNATURE
|
||||
// DR1 = The address of the Null-terminated ASCII string for the PE/COFF image's PDB file name
|
||||
// DR2 = The pointer to the ImageContext structure
|
||||
// DR3 = IO_PORT_BREAKPOINT_ADDRESS
|
||||
// DR7 = Disables all HW breakpoints except for DR3 I/O port access of length 1 byte
|
||||
// CR4 = Make sure DE(BIT3) is set
|
||||
//
|
||||
AsmWriteDr7 (0);
|
||||
AsmWriteDr0 (IMAGE_UNLOAD_SIGNATURE);
|
||||
AsmWriteDr1 ((UINTN)ImageContext->PdbPointer);
|
||||
AsmWriteDr2 ((UINTN)ImageContext);
|
||||
AsmWriteDr3 (IO_PORT_BREAKPOINT_ADDRESS);
|
||||
|
||||
LoadImageMethod = PcdGet8 (PcdDebugLoadImageMethod);
|
||||
if (LoadImageMethod == DEBUG_LOAD_IMAGE_METHOD_IO_HW_BREAKPOINT) {
|
||||
AsmWriteDr7 (0x20000480);
|
||||
AsmWriteCr4 (Cr4 | BIT3);
|
||||
//
|
||||
// Do an IN from IO_PORT_BREAKPOINT_ADDRESS to generate a HW breakpoint until the port
|
||||
// returns a read value other than DEBUG_AGENT_IMAGE_WAIT
|
||||
//
|
||||
do {
|
||||
DebugAgentStatus = IoRead8 (IO_PORT_BREAKPOINT_ADDRESS);
|
||||
} while (DebugAgentStatus == DEBUG_AGENT_IMAGE_WAIT);
|
||||
|
||||
} else if (LoadImageMethod == DEBUG_LOAD_IMAGE_METHOD_SOFT_INT3) {
|
||||
//
|
||||
// Generate a software break point.
|
||||
//
|
||||
CpuBreakpoint ();
|
||||
}
|
||||
|
||||
//
|
||||
// Restore Debug Register State only when Host didn't change it inside exception handler.
|
||||
// E.g.: User halts the target and sets the HW breakpoint while target is
|
||||
// in the above exception handler
|
||||
//
|
||||
NewDr7 = AsmReadDr7 ();
|
||||
if (!IsDrxEnabled (0, NewDr7)) {
|
||||
AsmWriteDr0 (Dr0);
|
||||
}
|
||||
if (!IsDrxEnabled (1, NewDr7)) {
|
||||
AsmWriteDr1 (Dr1);
|
||||
}
|
||||
if (!IsDrxEnabled (2, NewDr7)) {
|
||||
AsmWriteDr2 (Dr2);
|
||||
}
|
||||
if (!IsDrxEnabled (3, NewDr7)) {
|
||||
AsmWriteDr3 (Dr3);
|
||||
}
|
||||
if (AsmReadCr4 () == (Cr4 | BIT3)) {
|
||||
AsmWriteCr4 (Cr4);
|
||||
}
|
||||
if (NewDr7 == 0x20000480) {
|
||||
AsmWriteDr7 (Dr7);
|
||||
}
|
||||
|
||||
//
|
||||
// Restore the interrupt state
|
||||
//
|
||||
SetInterruptState (InterruptState);
|
||||
PeCoffLoaderExtraActionCommon (ImageContext, IMAGE_UNLOAD_SIGNATURE);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -4,11 +4,3 @@ Tool (Intel (R) UDK Debugger Tool).
|
|||
|
||||
The Intel(R) UDK Debugger Tool and its detailed user manual can be obtained
|
||||
from: http://www.intel.com/technology/efi.
|
||||
|
||||
NOTE: In addition to the known issues listed in the user manual, the following
|
||||
anomalies have been observed:
|
||||
|
||||
1) When using a USB debug cable, after the TARGET completes a reset during
|
||||
memory initialization, the connection between the HOST and the TARGET may be
|
||||
lost. A work around for this issue is to unplug the USB debug cable and then
|
||||
plug the cable back in. A new debug session can then be started.
|
||||
|
|
|
|||
|
|
@ -22,7 +22,7 @@
|
|||
DEC_SPECIFICATION = 0x00010005
|
||||
PACKAGE_NAME = SourceLevelDebugPkg
|
||||
PACKAGE_GUID = DBF00C27-D8D7-443d-918B-4E85CDA1373B
|
||||
PACKAGE_VERSION = 0.71
|
||||
PACKAGE_VERSION = 0.80
|
||||
|
||||
[Includes]
|
||||
Include
|
||||
|
|
|
|||
|
|
@ -22,7 +22,7 @@
|
|||
[Defines]
|
||||
PLATFORM_NAME = SourceLevelDebugPkg
|
||||
PLATFORM_GUID = 38C85805-883F-4ee8-A854-95B966ED73AA
|
||||
PLATFORM_VERSION = 0.71
|
||||
PLATFORM_VERSION = 0.80
|
||||
DSC_SPECIFICATION = 0x00010005
|
||||
OUTPUT_DIRECTORY = Build/SourceLevelDebugPkg
|
||||
SUPPORTED_ARCHITECTURES = IA32|X64
|
||||
|
|
|
|||
Loading…
Reference in New Issue