mirror of https://github.com/acidanthera/audk.git
UefiCpuPkg/MpInitLib: Add MicrocodeDetect() and load microcode on BSP
v4: 1. ProcessorSignature is updated to CPU_MICROCODE_PROCESSOR_SIGNATURE instead of UINT32. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Michael Kinney <michael.d.kinney@intel.com>
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@ -39,6 +39,7 @@
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DxeMpLib.c
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MpLib.c
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MpLib.h
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Microcode.c
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[Packages]
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MdePkg/MdePkg.dec
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@ -0,0 +1,216 @@
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/** @file
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Implementation of loading microcode on processors.
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Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include "MpLib.h"
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/**
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Get microcode update signature of currently loaded microcode update.
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@return Microcode signature.
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**/
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UINT32
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GetCurrentMicrocodeSignature (
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VOID
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)
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{
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MSR_IA32_BIOS_SIGN_ID_REGISTER BiosSignIdMsr;
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AsmWriteMsr64 (MSR_IA32_BIOS_SIGN_ID, 0);
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AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, NULL);
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BiosSignIdMsr.Uint64 = AsmReadMsr64 (MSR_IA32_BIOS_SIGN_ID);
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return BiosSignIdMsr.Bits.MicrocodeUpdateSignature;
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}
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/**
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Detect whether specified processor can find matching microcode patch and load it.
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@param[in] PeiCpuMpData Pointer to PEI CPU MP Data
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**/
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VOID
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MicrocodeDetect (
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IN CPU_MP_DATA *CpuMpData
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)
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{
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UINT64 MicrocodePatchAddress;
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UINT64 MicrocodePatchRegionSize;
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UINT32 ExtendedTableLength;
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UINT32 ExtendedTableCount;
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CPU_MICROCODE_EXTENDED_TABLE *ExtendedTable;
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CPU_MICROCODE_EXTENDED_TABLE_HEADER *ExtendedTableHeader;
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CPU_MICROCODE_HEADER *MicrocodeEntryPoint;
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UINTN MicrocodeEnd;
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UINTN Index;
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UINT8 PlatformId;
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CPUID_VERSION_INFO_EAX Eax;
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UINT32 CurrentRevision;
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UINT32 LatestRevision;
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UINTN TotalSize;
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UINT32 CheckSum32;
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BOOLEAN CorrectMicrocode;
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VOID *MicrocodeData;
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MSR_IA32_PLATFORM_ID_REGISTER PlatformIdMsr;
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MicrocodePatchAddress = PcdGet64 (PcdCpuMicrocodePatchAddress);
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MicrocodePatchRegionSize = PcdGet64 (PcdCpuMicrocodePatchRegionSize);
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if (MicrocodePatchRegionSize == 0) {
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//
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// There is no microcode patches
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//
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return;
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}
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CurrentRevision = GetCurrentMicrocodeSignature ();
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if (CurrentRevision != 0) {
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//
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// Skip loading microcode if it has been loaded successfully
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//
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return;
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}
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ExtendedTableLength = 0;
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//
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// Here data of CPUID leafs have not been collected into context buffer, so
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// GetProcessorCpuid() cannot be used here to retrieve sCPUID data.
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//
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AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, NULL, NULL, NULL);
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//
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// The index of platform information resides in bits 50:52 of MSR IA32_PLATFORM_ID
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//
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PlatformIdMsr.Uint64 = AsmReadMsr64 (MSR_IA32_PLATFORM_ID);
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PlatformId = (UINT8) PlatformIdMsr.Bits.PlatformId;
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LatestRevision = 0;
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MicrocodeEnd = (UINTN) (MicrocodePatchAddress + MicrocodePatchRegionSize);
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MicrocodeEntryPoint = (CPU_MICROCODE_HEADER *) (UINTN) MicrocodePatchAddress;
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do {
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//
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// Check if the microcode is for the Cpu and the version is newer
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// and the update can be processed on the platform
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//
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CorrectMicrocode = FALSE;
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if (MicrocodeEntryPoint->HeaderVersion == 0x1) {
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//
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// It is the microcode header. It is not the padding data between microcode patches
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// because the padding data should not include 0x00000001 and it should be the repeated
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// byte format (like 0xXYXYXYXY....).
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//
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if (MicrocodeEntryPoint->ProcessorSignature.Uint32 == Eax.Uint32 &&
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MicrocodeEntryPoint->UpdateRevision > LatestRevision &&
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(MicrocodeEntryPoint->ProcessorFlags & (1 << PlatformId))
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) {
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if (MicrocodeEntryPoint->DataSize == 0) {
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CheckSum32 = CalculateSum32 ((UINT32 *) MicrocodeEntryPoint, 2048);
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} else {
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CheckSum32 = CalculateSum32 (
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(UINT32 *) MicrocodeEntryPoint,
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MicrocodeEntryPoint->DataSize + sizeof (CPU_MICROCODE_HEADER)
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);
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}
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if (CheckSum32 == 0) {
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CorrectMicrocode = TRUE;
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}
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} else if ((MicrocodeEntryPoint->DataSize != 0) &&
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(MicrocodeEntryPoint->UpdateRevision > LatestRevision)) {
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ExtendedTableLength = MicrocodeEntryPoint->TotalSize - (MicrocodeEntryPoint->DataSize +
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sizeof (CPU_MICROCODE_HEADER));
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if (ExtendedTableLength != 0) {
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//
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// Extended Table exist, check if the CPU in support list
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//
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ExtendedTableHeader = (CPU_MICROCODE_EXTENDED_TABLE_HEADER *) ((UINT8 *) (MicrocodeEntryPoint)
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+ MicrocodeEntryPoint->DataSize + sizeof (CPU_MICROCODE_HEADER));
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//
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// Calculate Extended Checksum
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//
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if ((ExtendedTableLength % 4) == 0) {
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CheckSum32 = CalculateSum32 ((UINT32 *) ExtendedTableHeader, ExtendedTableLength);
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if (CheckSum32 == 0) {
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//
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// Checksum correct
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//
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ExtendedTableCount = ExtendedTableHeader->ExtendedSignatureCount;
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ExtendedTable = (CPU_MICROCODE_EXTENDED_TABLE *) (ExtendedTableHeader + 1);
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for (Index = 0; Index < ExtendedTableCount; Index ++) {
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CheckSum32 = CalculateSum32 ((UINT32 *) ExtendedTable, sizeof(CPU_MICROCODE_EXTENDED_TABLE));
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if (CheckSum32 == 0) {
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//
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// Verify Header
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//
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if ((ExtendedTable->ProcessorSignature.Uint32 == Eax.Uint32) &&
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(ExtendedTable->ProcessorFlag & (1 << PlatformId)) ) {
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//
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// Find one
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//
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CorrectMicrocode = TRUE;
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break;
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}
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}
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ExtendedTable ++;
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}
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}
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}
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}
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}
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} else {
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//
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// It is the padding data between the microcode patches for microcode patches alignment.
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// Because the microcode patch is the multiple of 1-KByte, the padding data should not
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// exist if the microcode patch alignment value is not larger than 1-KByte. So, the microcode
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// alignment value should be larger than 1-KByte. We could skip SIZE_1KB padding data to
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// find the next possible microcode patch header.
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//
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MicrocodeEntryPoint = (CPU_MICROCODE_HEADER *) (((UINTN) MicrocodeEntryPoint) + SIZE_1KB);
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continue;
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}
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//
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// Get the next patch.
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//
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if (MicrocodeEntryPoint->DataSize == 0) {
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TotalSize = 2048;
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} else {
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TotalSize = MicrocodeEntryPoint->TotalSize;
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}
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if (CorrectMicrocode) {
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LatestRevision = MicrocodeEntryPoint->UpdateRevision;
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MicrocodeData = (VOID *) ((UINTN) MicrocodeEntryPoint + sizeof (CPU_MICROCODE_HEADER));
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}
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MicrocodeEntryPoint = (CPU_MICROCODE_HEADER *) (((UINTN) MicrocodeEntryPoint) + TotalSize);
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} while (((UINTN) MicrocodeEntryPoint < MicrocodeEnd));
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if (LatestRevision > CurrentRevision) {
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//
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// BIOS only authenticate updates that contain a numerically larger revision
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// than the currently loaded revision, where Current Signature < New Update
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// Revision. A processor with no loaded update is considered to have a
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// revision equal to zero.
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//
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AsmWriteMsr64 (
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MSR_IA32_BIOS_UPDT_TRIG,
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(UINT64) (UINTN) MicrocodeData
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);
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//
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// Get and check new microcode signature
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//
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CurrentRevision = GetCurrentMicrocodeSignature ();
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if (CurrentRevision != LatestRevision) {
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AcquireSpinLock(&CpuMpData->MpLock);
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DEBUG ((EFI_D_ERROR, "Updated microcode signature [0x%08x] does not match \
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loaded microcode signature [0x%08x]\n", CurrentRevision, LatestRevision));
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ReleaseSpinLock(&CpuMpData->MpLock);
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}
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}
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}
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@ -294,6 +294,11 @@ MpInitLibInitialize (
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CpuMpData->CpuData[Index].StartupApSignal =
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(UINT32 *)(MonitorBuffer + MonitorFilterSize * Index);
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}
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//
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// Load Microcode on BSP
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//
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MicrocodeDetect (CpuMpData);
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//
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// Store BSP's MTRR setting
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//
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MtrrGetAllMtrrs (&CpuMpData->MtrrTable);
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@ -232,5 +232,15 @@ AsmGetAddressMap (
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OUT MP_ASSEMBLY_ADDRESS_MAP *AddressMap
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);
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/**
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Detect whether specified processor can find matching microcode patch and load it.
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@param[in] PeiCpuMpData Pointer to PEI CPU MP Data
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**/
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VOID
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MicrocodeDetect (
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IN CPU_MP_DATA *CpuMpData
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);
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#endif
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@ -39,6 +39,7 @@
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PeiMpLib.c
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MpLib.c
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MpLib.h
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Microcode.c
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[Packages]
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MdePkg/MdePkg.dec
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