mirror of https://github.com/acidanthera/audk.git
Update BASE PCI Library that uses CF8/CFC access mechanism for PCI configuration cycles to be safe for use from interrupt context and from modules of type DXE_SMM_DRIVER.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10606 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
mdkinney
parent
76d428b107
commit
96dd57ee8d
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@ -114,9 +114,18 @@ PciCf8Read8 (
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IN UINTN Address
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IN UINTN Address
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)
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)
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{
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{
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BOOLEAN InterruptState;
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UINT32 AddressPort;
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UINT8 Result;
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ASSERT_INVALID_PCI_ADDRESS (Address, 0);
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ASSERT_INVALID_PCI_ADDRESS (Address, 0);
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InterruptState = SaveAndDisableInterrupts ();
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AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
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IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
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IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
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return IoRead8 (PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3));
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Result = IoRead8 (PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3));
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IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);
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SetInterruptState (InterruptState);
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return Result;
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}
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}
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/**
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/**
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@ -143,12 +152,21 @@ PciCf8Write8 (
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IN UINT8 Value
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IN UINT8 Value
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)
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)
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{
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{
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BOOLEAN InterruptState;
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UINT32 AddressPort;
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UINT8 Result;
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ASSERT_INVALID_PCI_ADDRESS (Address, 0);
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ASSERT_INVALID_PCI_ADDRESS (Address, 0);
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InterruptState = SaveAndDisableInterrupts ();
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AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
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IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
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IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
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return IoWrite8 (
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Result = IoWrite8 (
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PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),
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PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),
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Value
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Value
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);
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);
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IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);
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SetInterruptState (InterruptState);
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return Result;
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}
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}
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/**
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/**
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@ -179,12 +197,21 @@ PciCf8Or8 (
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IN UINT8 OrData
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IN UINT8 OrData
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)
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)
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{
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{
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BOOLEAN InterruptState;
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UINT32 AddressPort;
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UINT8 Result;
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ASSERT_INVALID_PCI_ADDRESS (Address, 0);
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ASSERT_INVALID_PCI_ADDRESS (Address, 0);
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InterruptState = SaveAndDisableInterrupts ();
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AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
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IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
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IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
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return IoOr8 (
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Result = IoOr8 (
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PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),
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PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),
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OrData
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OrData
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);
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);
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IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);
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SetInterruptState (InterruptState);
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return Result;
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}
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}
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/**
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/**
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@ -215,12 +242,21 @@ PciCf8And8 (
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IN UINT8 AndData
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IN UINT8 AndData
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)
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)
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{
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{
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BOOLEAN InterruptState;
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UINT32 AddressPort;
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UINT8 Result;
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ASSERT_INVALID_PCI_ADDRESS (Address, 0);
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ASSERT_INVALID_PCI_ADDRESS (Address, 0);
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InterruptState = SaveAndDisableInterrupts ();
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AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
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IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
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IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
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return IoAnd8 (
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Result = IoAnd8 (
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PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),
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PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),
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AndData
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AndData
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);
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);
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IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);
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SetInterruptState (InterruptState);
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return Result;
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}
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}
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/**
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/**
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@ -254,13 +290,22 @@ PciCf8AndThenOr8 (
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IN UINT8 OrData
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IN UINT8 OrData
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)
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)
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{
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{
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BOOLEAN InterruptState;
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UINT32 AddressPort;
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UINT8 Result;
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ASSERT_INVALID_PCI_ADDRESS (Address, 0);
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ASSERT_INVALID_PCI_ADDRESS (Address, 0);
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InterruptState = SaveAndDisableInterrupts ();
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AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
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IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
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IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
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return IoAndThenOr8 (
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Result = IoAndThenOr8 (
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PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),
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PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),
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AndData,
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AndData,
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OrData
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OrData
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);
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);
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IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);
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SetInterruptState (InterruptState);
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return Result;
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}
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}
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/**
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/**
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@ -293,13 +338,22 @@ PciCf8BitFieldRead8 (
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IN UINTN EndBit
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IN UINTN EndBit
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)
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)
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{
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{
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BOOLEAN InterruptState;
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UINT32 AddressPort;
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UINT8 Result;
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ASSERT_INVALID_PCI_ADDRESS (Address, 0);
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ASSERT_INVALID_PCI_ADDRESS (Address, 0);
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InterruptState = SaveAndDisableInterrupts ();
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AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
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IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
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IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
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return IoBitFieldRead8 (
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Result = IoBitFieldRead8 (
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PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),
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PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),
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StartBit,
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StartBit,
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EndBit
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EndBit
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);
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);
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IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);
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SetInterruptState (InterruptState);
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return Result;
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}
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}
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/**
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/**
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@ -335,14 +389,23 @@ PciCf8BitFieldWrite8 (
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IN UINT8 Value
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IN UINT8 Value
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)
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)
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{
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{
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BOOLEAN InterruptState;
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UINT32 AddressPort;
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UINT8 Result;
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ASSERT_INVALID_PCI_ADDRESS (Address, 0);
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ASSERT_INVALID_PCI_ADDRESS (Address, 0);
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InterruptState = SaveAndDisableInterrupts ();
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AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
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IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
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IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
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return IoBitFieldWrite8 (
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Result = IoBitFieldWrite8 (
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PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),
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PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),
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StartBit,
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StartBit,
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EndBit,
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EndBit,
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Value
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Value
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);
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);
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IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);
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SetInterruptState (InterruptState);
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return Result;
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}
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}
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/**
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/**
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@ -381,14 +444,23 @@ PciCf8BitFieldOr8 (
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IN UINT8 OrData
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IN UINT8 OrData
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)
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)
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{
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{
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BOOLEAN InterruptState;
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UINT32 AddressPort;
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UINT8 Result;
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ASSERT_INVALID_PCI_ADDRESS (Address, 0);
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ASSERT_INVALID_PCI_ADDRESS (Address, 0);
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InterruptState = SaveAndDisableInterrupts ();
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AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
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IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
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IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
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return IoBitFieldOr8 (
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Result = IoBitFieldOr8 (
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PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),
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PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),
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StartBit,
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StartBit,
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EndBit,
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EndBit,
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OrData
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OrData
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);
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);
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IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);
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SetInterruptState (InterruptState);
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return Result;
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}
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}
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/**
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/**
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@ -427,14 +499,23 @@ PciCf8BitFieldAnd8 (
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IN UINT8 AndData
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IN UINT8 AndData
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)
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)
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{
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{
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BOOLEAN InterruptState;
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UINT32 AddressPort;
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UINT8 Result;
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ASSERT_INVALID_PCI_ADDRESS (Address, 0);
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ASSERT_INVALID_PCI_ADDRESS (Address, 0);
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InterruptState = SaveAndDisableInterrupts ();
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AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
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IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
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IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
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return IoBitFieldAnd8 (
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Result = IoBitFieldAnd8 (
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PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),
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PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),
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StartBit,
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StartBit,
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EndBit,
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EndBit,
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AndData
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AndData
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);
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);
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IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);
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SetInterruptState (InterruptState);
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return Result;
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}
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}
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/**
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/**
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@ -477,15 +558,24 @@ PciCf8BitFieldAndThenOr8(
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IN UINT8 OrData
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IN UINT8 OrData
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)
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)
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{
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{
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BOOLEAN InterruptState;
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UINT32 AddressPort;
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UINT8 Result;
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ASSERT_INVALID_PCI_ADDRESS (Address, 0);
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ASSERT_INVALID_PCI_ADDRESS (Address, 0);
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InterruptState = SaveAndDisableInterrupts ();
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AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
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IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
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IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
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return IoBitFieldAndThenOr8 (
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Result = IoBitFieldAndThenOr8 (
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PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),
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PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),
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StartBit,
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StartBit,
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EndBit,
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EndBit,
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AndData,
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AndData,
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OrData
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OrData
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);
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);
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IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);
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SetInterruptState (InterruptState);
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return Result;
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}
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}
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/**
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/**
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@ -511,9 +601,18 @@ PciCf8Read16 (
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IN UINTN Address
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IN UINTN Address
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)
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)
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{
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{
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BOOLEAN InterruptState;
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UINT32 AddressPort;
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UINT16 Result;
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ASSERT_INVALID_PCI_ADDRESS (Address, 1);
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ASSERT_INVALID_PCI_ADDRESS (Address, 1);
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InterruptState = SaveAndDisableInterrupts ();
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AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
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IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
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IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
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return IoRead16 (PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2));
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Result = IoRead16 (PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2));
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IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);
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SetInterruptState (InterruptState);
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return Result;
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}
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}
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/**
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/**
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@ -541,12 +640,21 @@ PciCf8Write16 (
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IN UINT16 Value
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IN UINT16 Value
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)
|
)
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{
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{
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|
BOOLEAN InterruptState;
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UINT32 AddressPort;
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UINT16 Result;
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|
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ASSERT_INVALID_PCI_ADDRESS (Address, 1);
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ASSERT_INVALID_PCI_ADDRESS (Address, 1);
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InterruptState = SaveAndDisableInterrupts ();
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AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
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IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
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IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
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return IoWrite16 (
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Result = IoWrite16 (
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PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),
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PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),
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Value
|
Value
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);
|
);
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IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);
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SetInterruptState (InterruptState);
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return Result;
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}
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}
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|
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/**
|
/**
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|
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@ -578,12 +686,21 @@ PciCf8Or16 (
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IN UINT16 OrData
|
IN UINT16 OrData
|
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)
|
)
|
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{
|
{
|
||||||
|
BOOLEAN InterruptState;
|
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|
UINT32 AddressPort;
|
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|
UINT16 Result;
|
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|
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ASSERT_INVALID_PCI_ADDRESS (Address, 1);
|
ASSERT_INVALID_PCI_ADDRESS (Address, 1);
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|
InterruptState = SaveAndDisableInterrupts ();
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|
AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
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IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
|
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
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return IoOr16 (
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Result = IoOr16 (
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PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),
|
PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),
|
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OrData
|
OrData
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);
|
);
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|
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);
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|
SetInterruptState (InterruptState);
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|
return Result;
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}
|
}
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|
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/**
|
/**
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|
|
@ -615,12 +732,21 @@ PciCf8And16 (
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IN UINT16 AndData
|
IN UINT16 AndData
|
||||||
)
|
)
|
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{
|
{
|
||||||
|
BOOLEAN InterruptState;
|
||||||
|
UINT32 AddressPort;
|
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|
UINT16 Result;
|
||||||
|
|
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ASSERT_INVALID_PCI_ADDRESS (Address, 1);
|
ASSERT_INVALID_PCI_ADDRESS (Address, 1);
|
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|
InterruptState = SaveAndDisableInterrupts ();
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|
AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
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IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
|
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
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return IoAnd16 (
|
Result = IoAnd16 (
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PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),
|
PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),
|
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AndData
|
AndData
|
||||||
);
|
);
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|
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);
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|
SetInterruptState (InterruptState);
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|
return Result;
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}
|
}
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|
|
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/**
|
/**
|
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|
|
@ -655,13 +781,22 @@ PciCf8AndThenOr16 (
|
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IN UINT16 OrData
|
IN UINT16 OrData
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
BOOLEAN InterruptState;
|
||||||
|
UINT32 AddressPort;
|
||||||
|
UINT16 Result;
|
||||||
|
|
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ASSERT_INVALID_PCI_ADDRESS (Address, 1);
|
ASSERT_INVALID_PCI_ADDRESS (Address, 1);
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|
InterruptState = SaveAndDisableInterrupts ();
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|
AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
|
||||||
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
|
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
|
||||||
return IoAndThenOr16 (
|
Result = IoAndThenOr16 (
|
||||||
PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),
|
PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),
|
||||||
AndData,
|
AndData,
|
||||||
OrData
|
OrData
|
||||||
);
|
);
|
||||||
|
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);
|
||||||
|
SetInterruptState (InterruptState);
|
||||||
|
return Result;
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
@ -695,13 +830,22 @@ PciCf8BitFieldRead16 (
|
||||||
IN UINTN EndBit
|
IN UINTN EndBit
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
BOOLEAN InterruptState;
|
||||||
|
UINT32 AddressPort;
|
||||||
|
UINT16 Result;
|
||||||
|
|
||||||
ASSERT_INVALID_PCI_ADDRESS (Address, 1);
|
ASSERT_INVALID_PCI_ADDRESS (Address, 1);
|
||||||
|
InterruptState = SaveAndDisableInterrupts ();
|
||||||
|
AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
|
||||||
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
|
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
|
||||||
return IoBitFieldRead16 (
|
Result = IoBitFieldRead16 (
|
||||||
PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),
|
PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),
|
||||||
StartBit,
|
StartBit,
|
||||||
EndBit
|
EndBit
|
||||||
);
|
);
|
||||||
|
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);
|
||||||
|
SetInterruptState (InterruptState);
|
||||||
|
return Result;
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
@ -738,14 +882,23 @@ PciCf8BitFieldWrite16 (
|
||||||
IN UINT16 Value
|
IN UINT16 Value
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
BOOLEAN InterruptState;
|
||||||
|
UINT32 AddressPort;
|
||||||
|
UINT16 Result;
|
||||||
|
|
||||||
ASSERT_INVALID_PCI_ADDRESS (Address, 1);
|
ASSERT_INVALID_PCI_ADDRESS (Address, 1);
|
||||||
|
InterruptState = SaveAndDisableInterrupts ();
|
||||||
|
AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
|
||||||
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
|
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
|
||||||
return IoBitFieldWrite16 (
|
Result = IoBitFieldWrite16 (
|
||||||
PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),
|
PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),
|
||||||
StartBit,
|
StartBit,
|
||||||
EndBit,
|
EndBit,
|
||||||
Value
|
Value
|
||||||
);
|
);
|
||||||
|
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);
|
||||||
|
SetInterruptState (InterruptState);
|
||||||
|
return Result;
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
@ -785,14 +938,23 @@ PciCf8BitFieldOr16 (
|
||||||
IN UINT16 OrData
|
IN UINT16 OrData
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
BOOLEAN InterruptState;
|
||||||
|
UINT32 AddressPort;
|
||||||
|
UINT16 Result;
|
||||||
|
|
||||||
ASSERT_INVALID_PCI_ADDRESS (Address, 1);
|
ASSERT_INVALID_PCI_ADDRESS (Address, 1);
|
||||||
|
InterruptState = SaveAndDisableInterrupts ();
|
||||||
|
AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
|
||||||
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
|
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
|
||||||
return IoBitFieldOr16 (
|
Result = IoBitFieldOr16 (
|
||||||
PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),
|
PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),
|
||||||
StartBit,
|
StartBit,
|
||||||
EndBit,
|
EndBit,
|
||||||
OrData
|
OrData
|
||||||
);
|
);
|
||||||
|
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);
|
||||||
|
SetInterruptState (InterruptState);
|
||||||
|
return Result;
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
@ -832,14 +994,23 @@ PciCf8BitFieldAnd16 (
|
||||||
IN UINT16 AndData
|
IN UINT16 AndData
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
BOOLEAN InterruptState;
|
||||||
|
UINT32 AddressPort;
|
||||||
|
UINT16 Result;
|
||||||
|
|
||||||
ASSERT_INVALID_PCI_ADDRESS (Address, 1);
|
ASSERT_INVALID_PCI_ADDRESS (Address, 1);
|
||||||
|
InterruptState = SaveAndDisableInterrupts ();
|
||||||
|
AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
|
||||||
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
|
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
|
||||||
return IoBitFieldAnd16 (
|
Result = IoBitFieldAnd16 (
|
||||||
PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),
|
PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),
|
||||||
StartBit,
|
StartBit,
|
||||||
EndBit,
|
EndBit,
|
||||||
AndData
|
AndData
|
||||||
);
|
);
|
||||||
|
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);
|
||||||
|
SetInterruptState (InterruptState);
|
||||||
|
return Result;
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
@ -883,15 +1054,24 @@ PciCf8BitFieldAndThenOr16(
|
||||||
IN UINT16 OrData
|
IN UINT16 OrData
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
BOOLEAN InterruptState;
|
||||||
|
UINT32 AddressPort;
|
||||||
|
UINT16 Result;
|
||||||
|
|
||||||
ASSERT_INVALID_PCI_ADDRESS (Address, 1);
|
ASSERT_INVALID_PCI_ADDRESS (Address, 1);
|
||||||
|
InterruptState = SaveAndDisableInterrupts ();
|
||||||
|
AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
|
||||||
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
|
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
|
||||||
return IoBitFieldAndThenOr16 (
|
Result = IoBitFieldAndThenOr16 (
|
||||||
PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),
|
PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),
|
||||||
StartBit,
|
StartBit,
|
||||||
EndBit,
|
EndBit,
|
||||||
AndData,
|
AndData,
|
||||||
OrData
|
OrData
|
||||||
);
|
);
|
||||||
|
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);
|
||||||
|
SetInterruptState (InterruptState);
|
||||||
|
return Result;
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
@ -917,9 +1097,18 @@ PciCf8Read32 (
|
||||||
IN UINTN Address
|
IN UINTN Address
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
BOOLEAN InterruptState;
|
||||||
|
UINT32 AddressPort;
|
||||||
|
UINT32 Result;
|
||||||
|
|
||||||
ASSERT_INVALID_PCI_ADDRESS (Address, 3);
|
ASSERT_INVALID_PCI_ADDRESS (Address, 3);
|
||||||
|
InterruptState = SaveAndDisableInterrupts ();
|
||||||
|
AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
|
||||||
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
|
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
|
||||||
return IoRead32 (PCI_CONFIGURATION_DATA_PORT);
|
Result = IoRead32 (PCI_CONFIGURATION_DATA_PORT);
|
||||||
|
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);
|
||||||
|
SetInterruptState (InterruptState);
|
||||||
|
return Result;
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
@ -947,12 +1136,21 @@ PciCf8Write32 (
|
||||||
IN UINT32 Value
|
IN UINT32 Value
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
BOOLEAN InterruptState;
|
||||||
|
UINT32 AddressPort;
|
||||||
|
UINT32 Result;
|
||||||
|
|
||||||
ASSERT_INVALID_PCI_ADDRESS (Address, 3);
|
ASSERT_INVALID_PCI_ADDRESS (Address, 3);
|
||||||
|
InterruptState = SaveAndDisableInterrupts ();
|
||||||
|
AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
|
||||||
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
|
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
|
||||||
return IoWrite32 (
|
Result = IoWrite32 (
|
||||||
PCI_CONFIGURATION_DATA_PORT,
|
PCI_CONFIGURATION_DATA_PORT,
|
||||||
Value
|
Value
|
||||||
);
|
);
|
||||||
|
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);
|
||||||
|
SetInterruptState (InterruptState);
|
||||||
|
return Result;
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
@ -984,12 +1182,21 @@ PciCf8Or32 (
|
||||||
IN UINT32 OrData
|
IN UINT32 OrData
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
BOOLEAN InterruptState;
|
||||||
|
UINT32 AddressPort;
|
||||||
|
UINT32 Result;
|
||||||
|
|
||||||
ASSERT_INVALID_PCI_ADDRESS (Address, 3);
|
ASSERT_INVALID_PCI_ADDRESS (Address, 3);
|
||||||
|
InterruptState = SaveAndDisableInterrupts ();
|
||||||
|
AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
|
||||||
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
|
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
|
||||||
return IoOr32 (
|
Result = IoOr32 (
|
||||||
PCI_CONFIGURATION_DATA_PORT,
|
PCI_CONFIGURATION_DATA_PORT,
|
||||||
OrData
|
OrData
|
||||||
);
|
);
|
||||||
|
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);
|
||||||
|
SetInterruptState (InterruptState);
|
||||||
|
return Result;
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
@ -1021,12 +1228,21 @@ PciCf8And32 (
|
||||||
IN UINT32 AndData
|
IN UINT32 AndData
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
BOOLEAN InterruptState;
|
||||||
|
UINT32 AddressPort;
|
||||||
|
UINT32 Result;
|
||||||
|
|
||||||
ASSERT_INVALID_PCI_ADDRESS (Address, 3);
|
ASSERT_INVALID_PCI_ADDRESS (Address, 3);
|
||||||
|
InterruptState = SaveAndDisableInterrupts ();
|
||||||
|
AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
|
||||||
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
|
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
|
||||||
return IoAnd32 (
|
Result = IoAnd32 (
|
||||||
PCI_CONFIGURATION_DATA_PORT,
|
PCI_CONFIGURATION_DATA_PORT,
|
||||||
AndData
|
AndData
|
||||||
);
|
);
|
||||||
|
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);
|
||||||
|
SetInterruptState (InterruptState);
|
||||||
|
return Result;
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
@ -1061,13 +1277,22 @@ PciCf8AndThenOr32 (
|
||||||
IN UINT32 OrData
|
IN UINT32 OrData
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
BOOLEAN InterruptState;
|
||||||
|
UINT32 AddressPort;
|
||||||
|
UINT32 Result;
|
||||||
|
|
||||||
ASSERT_INVALID_PCI_ADDRESS (Address, 3);
|
ASSERT_INVALID_PCI_ADDRESS (Address, 3);
|
||||||
|
InterruptState = SaveAndDisableInterrupts ();
|
||||||
|
AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
|
||||||
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
|
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
|
||||||
return IoAndThenOr32 (
|
Result = IoAndThenOr32 (
|
||||||
PCI_CONFIGURATION_DATA_PORT,
|
PCI_CONFIGURATION_DATA_PORT,
|
||||||
AndData,
|
AndData,
|
||||||
OrData
|
OrData
|
||||||
);
|
);
|
||||||
|
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);
|
||||||
|
SetInterruptState (InterruptState);
|
||||||
|
return Result;
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
@ -1101,13 +1326,22 @@ PciCf8BitFieldRead32 (
|
||||||
IN UINTN EndBit
|
IN UINTN EndBit
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
BOOLEAN InterruptState;
|
||||||
|
UINT32 AddressPort;
|
||||||
|
UINT32 Result;
|
||||||
|
|
||||||
ASSERT_INVALID_PCI_ADDRESS (Address, 3);
|
ASSERT_INVALID_PCI_ADDRESS (Address, 3);
|
||||||
|
InterruptState = SaveAndDisableInterrupts ();
|
||||||
|
AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
|
||||||
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
|
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
|
||||||
return IoBitFieldRead32 (
|
Result = IoBitFieldRead32 (
|
||||||
PCI_CONFIGURATION_DATA_PORT,
|
PCI_CONFIGURATION_DATA_PORT,
|
||||||
StartBit,
|
StartBit,
|
||||||
EndBit
|
EndBit
|
||||||
);
|
);
|
||||||
|
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);
|
||||||
|
SetInterruptState (InterruptState);
|
||||||
|
return Result;
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
@ -1144,14 +1378,23 @@ PciCf8BitFieldWrite32 (
|
||||||
IN UINT32 Value
|
IN UINT32 Value
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
BOOLEAN InterruptState;
|
||||||
|
UINT32 AddressPort;
|
||||||
|
UINT32 Result;
|
||||||
|
|
||||||
ASSERT_INVALID_PCI_ADDRESS (Address, 3);
|
ASSERT_INVALID_PCI_ADDRESS (Address, 3);
|
||||||
|
InterruptState = SaveAndDisableInterrupts ();
|
||||||
|
AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
|
||||||
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
|
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
|
||||||
return IoBitFieldWrite32 (
|
Result = IoBitFieldWrite32 (
|
||||||
PCI_CONFIGURATION_DATA_PORT,
|
PCI_CONFIGURATION_DATA_PORT,
|
||||||
StartBit,
|
StartBit,
|
||||||
EndBit,
|
EndBit,
|
||||||
Value
|
Value
|
||||||
);
|
);
|
||||||
|
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);
|
||||||
|
SetInterruptState (InterruptState);
|
||||||
|
return Result;
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
@ -1191,14 +1434,23 @@ PciCf8BitFieldOr32 (
|
||||||
IN UINT32 OrData
|
IN UINT32 OrData
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
BOOLEAN InterruptState;
|
||||||
|
UINT32 AddressPort;
|
||||||
|
UINT32 Result;
|
||||||
|
|
||||||
ASSERT_INVALID_PCI_ADDRESS (Address, 3);
|
ASSERT_INVALID_PCI_ADDRESS (Address, 3);
|
||||||
|
InterruptState = SaveAndDisableInterrupts ();
|
||||||
|
AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
|
||||||
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
|
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
|
||||||
return IoBitFieldOr32 (
|
Result = IoBitFieldOr32 (
|
||||||
PCI_CONFIGURATION_DATA_PORT,
|
PCI_CONFIGURATION_DATA_PORT,
|
||||||
StartBit,
|
StartBit,
|
||||||
EndBit,
|
EndBit,
|
||||||
OrData
|
OrData
|
||||||
);
|
);
|
||||||
|
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);
|
||||||
|
SetInterruptState (InterruptState);
|
||||||
|
return Result;
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
@ -1238,14 +1490,23 @@ PciCf8BitFieldAnd32 (
|
||||||
IN UINT32 AndData
|
IN UINT32 AndData
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
BOOLEAN InterruptState;
|
||||||
|
UINT32 AddressPort;
|
||||||
|
UINT32 Result;
|
||||||
|
|
||||||
ASSERT_INVALID_PCI_ADDRESS (Address, 3);
|
ASSERT_INVALID_PCI_ADDRESS (Address, 3);
|
||||||
|
InterruptState = SaveAndDisableInterrupts ();
|
||||||
|
AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
|
||||||
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
|
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
|
||||||
return IoBitFieldAnd32 (
|
Result = IoBitFieldAnd32 (
|
||||||
PCI_CONFIGURATION_DATA_PORT,
|
PCI_CONFIGURATION_DATA_PORT,
|
||||||
StartBit,
|
StartBit,
|
||||||
EndBit,
|
EndBit,
|
||||||
AndData
|
AndData
|
||||||
);
|
);
|
||||||
|
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);
|
||||||
|
SetInterruptState (InterruptState);
|
||||||
|
return Result;
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
@ -1289,15 +1550,24 @@ PciCf8BitFieldAndThenOr32(
|
||||||
IN UINT32 OrData
|
IN UINT32 OrData
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
BOOLEAN InterruptState;
|
||||||
|
UINT32 AddressPort;
|
||||||
|
UINT32 Result;
|
||||||
|
|
||||||
ASSERT_INVALID_PCI_ADDRESS (Address, 3);
|
ASSERT_INVALID_PCI_ADDRESS (Address, 3);
|
||||||
|
InterruptState = SaveAndDisableInterrupts ();
|
||||||
|
AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
|
||||||
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
|
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
|
||||||
return IoBitFieldAndThenOr32 (
|
Result = IoBitFieldAndThenOr32 (
|
||||||
PCI_CONFIGURATION_DATA_PORT,
|
PCI_CONFIGURATION_DATA_PORT,
|
||||||
StartBit,
|
StartBit,
|
||||||
EndBit,
|
EndBit,
|
||||||
AndData,
|
AndData,
|
||||||
OrData
|
OrData
|
||||||
);
|
);
|
||||||
|
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);
|
||||||
|
SetInterruptState (InterruptState);
|
||||||
|
return Result;
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue