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1. Added EdkPciIncompatibleDeviceSupportLib in EdkModulePkg, this library is used for PciBus driver and includes 3 Incompatible device lists. 

2. Used EdkPciIncompatibleDeviceSupportLib in PciBus driver. 
3. Redirect all Pci Configuration access to new APIs added in PciLib.c for PciBus driver.
4. Added one PCD PcdIncompatibleDeviceSupportMask in EdkModulePkg.spd to provide mask of PCI devices incompatibility check.

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@2562 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
vanjeff 2007-04-12 09:07:01 +00:00
parent 0eaa1933bc
commit 98419ef4b9
18 changed files with 2226 additions and 412 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
EdkModulePkg/Bus/Pci/PciBus/Dxe/PciBus.msa
View File

@ -57,6 +57,9 @@
<LibraryClass Usage="ALWAYS_CONSUMED"> <LibraryClass Usage="ALWAYS_CONSUMED">
<Keyword>PcdLib</Keyword> <Keyword>PcdLib</Keyword>
</LibraryClass> </LibraryClass>
<LibraryClass Usage="ALWAYS_CONSUMED">
<Keyword>PciIncompatibleDeviceSupportLib</Keyword>
</LibraryClass>
</LibraryClassDefinitions> </LibraryClassDefinitions>
<SourceFiles> <SourceFiles>
<Filename>pcibus.h</Filename> <Filename>pcibus.h</Filename>
@ -174,5 +177,10 @@
<DefaultValue>TRUE</DefaultValue> <DefaultValue>TRUE</DefaultValue>
<HelpText>If TRUE, the PCI bus driver will support hot plug device. If not hot plug device is supported, this feature flag can be set to FALSE to save size.</HelpText> <HelpText>If TRUE, the PCI bus driver will support hot plug device. If not hot plug device is supported, this feature flag can be set to FALSE to save size.</HelpText>
</PcdEntry> </PcdEntry>
<PcdEntry PcdItemType="FIXED_AT_BUILD" Usage="ALWAYS_CONSUMED">
<C_Name>PcdPciIncompatibleDeviceSupportMask</C_Name>
<TokenSpaceGuidCName>gEfiEdkModulePkgTokenSpaceGuid</TokenSpaceGuidCName>
<HelpText>The PCD masks for PCI incompatible devices support</HelpText>
</PcdEntry>
</PcdCoded> </PcdCoded>
</ModuleSurfaceArea> </ModuleSurfaceArea>

82
EdkModulePkg/Bus/Pci/PciBus/Dxe/PciCommand.c
View File

@ -1,18 +1,18 @@
/*++ /*++
Copyright (c) 2006, Intel Corporation Copyright (c) 2006 - 2007, Intel Corporation
All rights reserved. This program and the accompanying materials All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name: Module Name:
PciCommand.c PciCommand.c
Abstract: Abstract:
PCI Bus Driver PCI Bus Driver
@ -56,13 +56,13 @@ Returns:
PciIo = &PciIoDevice->PciIo; PciIo = &PciIoDevice->PciIo;
if (Operation != EFI_SET_REGISTER) { if (Operation != EFI_SET_REGISTER) {
Status = PciIo->Pci.Read ( Status = PciIoRead (
PciIo, PciIo,
EfiPciIoWidthUint16, EfiPciIoWidthUint16,
Offset, Offset,
1, 1,
&OldCommand &OldCommand
); );
if (Operation == EFI_GET_REGISTER) { if (Operation == EFI_GET_REGISTER) {
*PtrCommand = OldCommand; *PtrCommand = OldCommand;
@ -78,13 +78,13 @@ Returns:
OldCommand = Command; OldCommand = Command;
} }
return PciIo->Pci.Write ( return PciIoWrite (
PciIo, PciIo,
EfiPciIoWidthUint16, EfiPciIoWidthUint16,
Offset, Offset,
1, 1,
&OldCommand &OldCommand
); );
} }
BOOLEAN BOOLEAN
@ -98,7 +98,7 @@ Routine Description:
Arguments: Arguments:
Returns: Returns:
None None
--*/ --*/
@ -131,7 +131,7 @@ Arguments:
NextRegBlock - A pointer to the next block. NextRegBlock - A pointer to the next block.
Returns: Returns:
None None
--*/ --*/
@ -157,22 +157,22 @@ Returns:
CapabilityPtr = 0; CapabilityPtr = 0;
if (IS_CARDBUS_BRIDGE (&PciIoDevice->Pci)) { if (IS_CARDBUS_BRIDGE (&PciIoDevice->Pci)) {
PciIoDevice->PciIo.Pci.Read ( PciIoRead (
&PciIoDevice->PciIo, &PciIoDevice->PciIo,
EfiPciIoWidthUint8, EfiPciIoWidthUint8,
EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR, EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR,
1, 1,
&CapabilityPtr &CapabilityPtr
); );
} else { } else {
PciIoDevice->PciIo.Pci.Read ( PciIoRead (
&PciIoDevice->PciIo, &PciIoDevice->PciIo,
EfiPciIoWidthUint8, EfiPciIoWidthUint8,
EFI_PCI_CAPABILITY_PTR, EFI_PCI_CAPABILITY_PTR,
1, 1,
&CapabilityPtr &CapabilityPtr
); );
} }
} }
@ -181,13 +181,13 @@ Returns:
// Mask it to DWORD alignment per PCI spec // Mask it to DWORD alignment per PCI spec
// //
CapabilityPtr &= 0xFC; CapabilityPtr &= 0xFC;
PciIoDevice->PciIo.Pci.Read ( PciIoRead (
&PciIoDevice->PciIo, &PciIoDevice->PciIo,
EfiPciIoWidthUint16, EfiPciIoWidthUint16,
CapabilityPtr, CapabilityPtr,
1, 1,
&CapabilityEntry &CapabilityEntry
); );
CapabilityID = (UINT8) CapabilityEntry; CapabilityID = (UINT8) CapabilityEntry;

7
EdkModulePkg/Bus/Pci/PciBus/Dxe/PciDeviceSupport.c
View File

@ -1,6 +1,6 @@
/*++ /*++
Copyright (c) 2006, Intel Corporation Copyright (c) 2006 - 2007, Intel Corporation
All rights reserved. This program and the accompanying materials All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at which accompanies this distribution. The full text of the license may be found at
@ -335,14 +335,13 @@ Returns:
if (!EFI_ERROR (Status)) { if (!EFI_ERROR (Status)) {
PciIoDevice->IsPciExp = TRUE; PciIoDevice->IsPciExp = TRUE;
} }
// //
// Force Interrupt line to "Unknown" or "No Connection" // Force Interrupt line to "Unknown" or "No Connection"
// //
PciIo = &(PciIoDevice->PciIo); PciIo = &(PciIoDevice->PciIo);
Data8 = PCI_INT_LINE_UNKNOWN; Data8 = PCI_INT_LINE_UNKNOWN;
PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &Data8);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &Data8);
// //
// Process Platform OpRom // Process Platform OpRom

94
EdkModulePkg/Bus/Pci/PciBus/Dxe/PciEnumerator.c
View File

@ -1,18 +1,18 @@
/*++ /*++
Copyright (c) 2006, Intel Corporation Copyright (c) 2006 - 2007, Intel Corporation
All rights reserved. This program and the accompanying materials All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name: Module Name:
PciEnumerator.c PciEnumerator.c
Abstract: Abstract:
PCI Bus Driver PCI Bus Driver
@ -34,7 +34,7 @@ PciEnumerator (
Routine Description: Routine Description:
This routine is used to enumerate entire pci bus system This routine is used to enumerate entire pci bus system
in a given platform in a given platform
Arguments: Arguments:
@ -118,7 +118,7 @@ Returns:
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
return Status; return Status;
} }
// //
// Submit the resource request // Submit the resource request
// //
@ -127,7 +127,7 @@ Returns:
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
return Status; return Status;
} }
// //
// Process P2C // Process P2C
// //
@ -136,7 +136,7 @@ Returns:
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
return Status; return Status;
} }
// //
// Process attributes for devices on this host bridge // Process attributes for devices on this host bridge
// //
@ -286,7 +286,7 @@ Returns:
while (CurrentLink && CurrentLink != &Bridge->ChildList) { while (CurrentLink && CurrentLink != &Bridge->ChildList) {
Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink); Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
if (!IsListEmpty (&Temp->ChildList)) { if (!IsListEmpty (&Temp->ChildList)) {
// //
// Go further to process the option rom under this bridge // Go further to process the option rom under this bridge
// //
@ -294,7 +294,7 @@ Returns:
} }
if (Temp->RomSize != 0 && Temp->RomSize <= MaxLength) { if (Temp->RomSize != 0 && Temp->RomSize <= MaxLength) {
// //
// Load and process the option rom // Load and process the option rom
// //
@ -382,8 +382,9 @@ Returns:
Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x18); Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x18);
Status = PciRootBridgeIo->Pci.Write ( Status = PciRootBridgeIoWrite (
PciRootBridgeIo, PciRootBridgeIo,
&Pci,
EfiPciWidthUint16, EfiPciWidthUint16,
Address, Address,
1, 1,
@ -394,8 +395,9 @@ Returns:
// Initialize SubBusNumber to SecondBus // Initialize SubBusNumber to SecondBus
// //
Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A); Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A);
Status = PciRootBridgeIo->Pci.Write ( Status = PciRootBridgeIoWrite (
PciRootBridgeIo, PciRootBridgeIo,
&Pci,
EfiPciWidthUint8, EfiPciWidthUint8,
Address, Address,
1, 1,
@ -407,8 +409,9 @@ Returns:
if (IS_PCI_BRIDGE (&Pci)) { if (IS_PCI_BRIDGE (&Pci)) {
Register8 = 0xFF; Register8 = 0xFF;
Status = PciRootBridgeIo->Pci.Write ( Status = PciRootBridgeIoWrite (
PciRootBridgeIo, PciRootBridgeIo,
&Pci,
EfiPciWidthUint8, EfiPciWidthUint8,
Address, Address,
1, 1,
@ -432,8 +435,9 @@ Returns:
Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A); Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A);
Status = PciRootBridgeIo->Pci.Write ( Status = PciRootBridgeIoWrite (
PciRootBridgeIo, PciRootBridgeIo,
&Pci,
EfiPciWidthUint8, EfiPciWidthUint8,
Address, Address,
1, 1,
@ -503,7 +507,7 @@ Returns:
// Here is the point where PCI bus driver calls HOST bridge allocation protocol // Here is the point where PCI bus driver calls HOST bridge allocation protocol
// Currently we hardcoded for ea815 // Currently we hardcoded for ea815
// //
if (Attributes & EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM) { if (Attributes & EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM) {
RootBridgeDev->Decodes |= EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED; RootBridgeDev->Decodes |= EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED;
} }
@ -526,7 +530,7 @@ GetMaxOptionRomSize (
/*++ /*++
Routine Description: Routine Description:
Get Max Option Rom size on this bridge Get Max Option Rom size on this bridge
Arguments: Arguments:
@ -552,7 +556,7 @@ Returns:
while (CurrentLink && CurrentLink != &Bridge->ChildList) { while (CurrentLink && CurrentLink != &Bridge->ChildList) {
Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink); Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
if (!IsListEmpty (&Temp->ChildList)) { if (!IsListEmpty (&Temp->ChildList)) {
// //
// Get max option rom size under this bridge // Get max option rom size under this bridge
// //
@ -567,13 +571,13 @@ Returns:
} }
} else { } else {
// //
// For devices get the rom size directly // For devices get the rom size directly
// //
TempOptionRomSize = Temp->RomSize; TempOptionRomSize = Temp->RomSize;
} }
// //
// Get the largest rom size on this bridge // Get the largest rom size on this bridge
// //
@ -594,7 +598,7 @@ PciHostBridgeDeviceAttribute (
/*++ /*++
Routine Description: Routine Description:
Process attributes of devices on this host bridge Process attributes of devices on this host bridge
Arguments: Arguments:
@ -650,7 +654,7 @@ GetResourceAllocationStatus (
/*++ /*++
Routine Description: Routine Description:
Get resource allocation status from the ACPI pointer Get resource allocation status from the ACPI pointer
Arguments: Arguments:
@ -736,7 +740,7 @@ RejectPciDevice (
/*++ /*++
Routine Description: Routine Description:
Remove a PCI device from device pool and mark its bar Remove a PCI device from device pool and mark its bar
Arguments: Arguments:
@ -789,7 +793,7 @@ Returns:
// //
InitializeP2C (PciDevice); InitializeP2C (PciDevice);
} }
// //
// Remove the device // Remove the device
// //
@ -817,7 +821,7 @@ IsRejectiveDevice (
/*++ /*++
Routine Description: Routine Description:
Determine whethter a PCI device can be rejected Determine whethter a PCI device can be rejected
Arguments: Arguments:
@ -839,7 +843,7 @@ Returns:
if (!Temp) { if (!Temp) {
return FALSE; return FALSE;
} }
// //
// PPB and RB should go ahead // PPB and RB should go ahead
// //
@ -853,7 +857,7 @@ Returns:
if ((Temp->Parent) && (Temp->BusNumber == 0)) { if ((Temp->Parent) && (Temp->BusNumber == 0)) {
return FALSE; return FALSE;
} }
// //
// Skip VGA // Skip VGA
// //
@ -872,7 +876,7 @@ GetLargerConsumerDevice (
/*++ /*++
Routine Description: Routine Description:
Get the larger resource consumer Get the larger resource consumer
Arguments: Arguments:
@ -914,8 +918,8 @@ GetMaxResourceConsumerDevice (
/*++ /*++
Routine Description: Routine Description:
Get the max resource consumer in the host resource pool Get the max resource consumer in the host resource pool
Arguments: Arguments:
@ -974,7 +978,7 @@ PciHostBridgeAdjustAllocation (
/*++ /*++
Routine Description: Routine Description:
Adjust host bridge allocation so as to reduce resource requirement Adjust host bridge allocation so as to reduce resource requirement
Arguments: Arguments:
@ -1039,7 +1043,7 @@ Returns:
// //
return EFI_ABORTED; return EFI_ABORTED;
} }
// //
// Hostbridge hasn't enough resource // Hostbridge hasn't enough resource
// //
@ -1047,7 +1051,7 @@ Returns:
if (!PciResNode) { if (!PciResNode) {
continue; continue;
} }
// //
// Check if the device has been removed before // Check if the device has been removed before
// //
@ -1056,13 +1060,13 @@ Returns:
continue; continue;
} }
} }
// //
// Remove the device if it isn't in the array // Remove the device if it isn't in the array
// //
Status = RejectPciDevice (PciResNode->PciDev); Status = RejectPciDevice (PciResNode->PciDev);
if (Status == EFI_SUCCESS) { if (Status == EFI_SUCCESS) {
// //
// Raise the EFI_IOB_EC_RESOURCE_CONFLICT status code // Raise the EFI_IOB_EC_RESOURCE_CONFLICT status code
// //
@ -1399,7 +1403,7 @@ Returns:
// Memory type aperture // Memory type aperture
// //
case 0: case 0:
// //
// Check to see the granularity // Check to see the granularity
// //
@ -1471,7 +1475,7 @@ Returns:
SubBusNumber = 0; SubBusNumber = 0;
StartBusNumber = 0; StartBusNumber = 0;
PciIo = &(BridgeDev->PciIo); PciIo = &(BridgeDev->PciIo);
Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x19, 1, &StartBusNumber); Status = PciIoRead (PciIo, EfiPciIoWidthUint8, 0x19, 1, &StartBusNumber);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
return Status; return Status;
@ -1896,7 +1900,7 @@ Returns:
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
// //
// Get Root Brige Handle // Get Root Brige Handle
// //
@ -1965,7 +1969,7 @@ PciHotPlugRequestNotify (
Routine Description: Routine Description:
Hot plug request notify. Hot plug request notify.
Arguments: Arguments:
This - A pointer to the hot plug request protocol. This - A pointer to the hot plug request protocol.
@ -2082,7 +2086,7 @@ SearchHostBridgeHandle (
/*++ /*++
Routine Description: Routine Description:
Arguments: Arguments:
Returns: Returns:
@ -2130,7 +2134,7 @@ AddHostBridgeEnumerator (
/*++ /*++
Routine Description: Routine Description:
Arguments: Arguments:
Returns: Returns:

259
EdkModulePkg/Bus/Pci/PciBus/Dxe/PciEnumeratorSupport.c
View File

@ -1,18 +1,18 @@
/*++ /*++
Copyright (c) 2006 - 2007, Intel Corporation Copyright (c) 2006 - 2007, Intel Corporation
All rights reserved. This program and the accompanying materials All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name: Module Name:
PciEnumeratorSupport.c PciEnumeratorSupport.c
Abstract: Abstract:
PCI Bus Driver PCI Bus Driver
@ -66,8 +66,9 @@ Returns:
// //
// Read the Vendor Id register // Read the Vendor Id register
// //
Status = PciRootBridgeIo->Pci.Read ( Status = PciRootBridgeIoRead (
PciRootBridgeIo, PciRootBridgeIo,
NULL,
EfiPciWidthUint32, EfiPciWidthUint32,
Address, Address,
1, 1,
@ -80,8 +81,9 @@ Returns:
// Read the entire config header for the device // Read the entire config header for the device
// //
Status = PciRootBridgeIo->Pci.Read ( Status = PciRootBridgeIoRead (
PciRootBridgeIo, PciRootBridgeIo,
NULL,
EfiPciWidthUint32, EfiPciWidthUint32,
Address, Address,
sizeof (PCI_TYPE00) / sizeof (UINT32), sizeof (PCI_TYPE00) / sizeof (UINT32),
@ -172,12 +174,12 @@ Returns:
// //
PciIo = &(PciIoDevice->PciIo); PciIo = &(PciIoDevice->PciIo);
Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x19, 1, &SecBus); Status = PciIoRead (PciIo, EfiPciIoWidthUint8, 0x19, 1, &SecBus);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
return Status; return Status;
} }
// //
// Get resource padding for PPB // Get resource padding for PPB
// //
@ -256,7 +258,7 @@ Returns:
Func Func
); );
if ((PciIoDevice != NULL) && gFullEnumeration) { if ((PciIoDevice != NULL) && gFullEnumeration) {
InitializeP2C (PciIoDevice); InitializeP2C (PciIoDevice);
} }
} else { } else {
@ -297,16 +299,18 @@ Returns:
if (!PciIoDevice) { if (!PciIoDevice) {
return EFI_OUT_OF_RESOURCES; return EFI_OUT_OF_RESOURCES;
} }
// //
// Update the bar information for this PCI device so as to support some specific device // Update the bar information for this PCI device so as to support some specific device
// //
UpdatePciInfo (PciIoDevice); if (PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_ACPI_RESOURCE_SUPPORT) {
UpdatePciInfo (PciIoDevice);
}
if (PciIoDevice->DevicePath == NULL) { if (PciIoDevice->DevicePath == NULL) {
return EFI_OUT_OF_RESOURCES; return EFI_OUT_OF_RESOURCES;
} }
// //
// Detect this function has option rom // Detect this function has option rom
// //
@ -321,7 +325,7 @@ Returns:
ResetPowerManagementFeature (PciIoDevice); ResetPowerManagementFeature (PciIoDevice);
} }
// //
// Insert it into a global tree for future reference // Insert it into a global tree for future reference
// //
@ -452,7 +456,7 @@ Returns:
if (!PciIoDevice) { if (!PciIoDevice) {
return NULL; return NULL;
} }
// //
// Create a device path for this PCI device and store it into its private data // Create a device path for this PCI device and store it into its private data
// //
@ -486,10 +490,10 @@ Returns:
// //
// Test whether it support 32 decode or not // Test whether it support 32 decode or not
// //
PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Temp); PciIoRead (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Temp);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &gAllOne); PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &gAllOne);
PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Value); PciIoRead (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Value);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Temp); PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Temp);
if (Value) { if (Value) {
if (Value & 0x01) { if (Value & 0x01) {
@ -684,20 +688,20 @@ Returns:
// Preserve the original value // Preserve the original value
// //
PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &OriginalValue); PciIoRead (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &OriginalValue);
// //
// Raise TPL to high level to disable timer interrupt while the BAR is probed // Raise TPL to high level to disable timer interrupt while the BAR is probed
// //
OldTpl = gBS->RaiseTPL (EFI_TPL_HIGH_LEVEL); OldTpl = gBS->RaiseTPL (EFI_TPL_HIGH_LEVEL);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &gAllOne); PciIoWrite (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &gAllOne);
PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &Value); PciIoRead (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &Value);
// //
// Write back the original value // Write back the original value
// //
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &OriginalValue); PciIoWrite (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &OriginalValue);
// //
// Restore TPL to its original level // Restore TPL to its original level
@ -771,7 +775,7 @@ Returns:
gBS->RestoreTPL (OldTpl); gBS->RestoreTPL (OldTpl);
if (IS_PCI_BRIDGE (&PciIoDevice->Pci) || IS_CARDBUS_BRIDGE (&PciIoDevice->Pci)) { if (IS_PCI_BRIDGE (&PciIoDevice->Pci) || IS_CARDBUS_BRIDGE (&PciIoDevice->Pci)) {
// //
// Preserve the original value // Preserve the original value
// //
@ -813,7 +817,7 @@ PciSetDeviceAttribute (
/*++ /*++
Routine Description: Routine Description:
Set the supported or current attributes of a PCI device Set the supported or current attributes of a PCI device
Arguments: Arguments:
PciIoDevice - Structure pointer for PCI device. PciIoDevice - Structure pointer for PCI device.
@ -821,7 +825,7 @@ PciSetDeviceAttribute (
BridgeControl - Bridge control value for PPB or P2C. BridgeControl - Bridge control value for PPB or P2C.
Option - Make a choice of EFI_SET_SUPPORTS or EFI_SET_ATTRIBUTES. Option - Make a choice of EFI_SET_SUPPORTS or EFI_SET_ATTRIBUTES.
Returns: Returns:
--*/ --*/
@ -829,15 +833,15 @@ PciSetDeviceAttribute (
Routine Description: Routine Description:
Arguments: Arguments:
Returns: Returns:
EFI_SUCCESS Always success EFI_SUCCESS Always success
--*/ --*/
{ {
@ -878,7 +882,7 @@ Returns:
if (Option == EFI_SET_SUPPORTS) { if (Option == EFI_SET_SUPPORTS) {
Attributes |= EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE | Attributes |= EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE |
EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED | EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED |
EFI_PCI_IO_ATTRIBUTE_MEMORY_DISABLE | EFI_PCI_IO_ATTRIBUTE_MEMORY_DISABLE |
EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE | EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE |
@ -929,7 +933,7 @@ GetFastBackToBackSupport (
/*++ /*++
Routine Description: Routine Description:
Determine if the device can support Fast Back to Back attribute Determine if the device can support Fast Back to Back attribute
Arguments: Arguments:
@ -953,11 +957,11 @@ Returns:
// Read the status register // Read the status register
// //
PciIo = &PciIoDevice->PciIo; PciIo = &PciIoDevice->PciIo;
Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, StatusIndex, 1, &StatusRegister); Status = PciIoRead (PciIo, EfiPciIoWidthUint16, StatusIndex, 1, &StatusRegister);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
// //
// Check the Fast B2B bit // Check the Fast B2B bit
// //
@ -977,7 +981,7 @@ ProcessOptionRomLight (
/*++ /*++
Routine Description: Routine Description:
Process the option ROM for all the children of the specified parent PCI device. Process the option ROM for all the children of the specified parent PCI device.
It can only be used after the first full Option ROM process. It can only be used after the first full Option ROM process.
@ -1020,7 +1024,7 @@ DetermineDeviceAttribute (
/*++ /*++
Routine Description: Routine Description:
Determine the related attributes of all devices under a Root Bridge Determine the related attributes of all devices under a Root Bridge
Arguments: Arguments:
@ -1061,7 +1065,7 @@ Returns:
return Status; return Status;
} }
} else { } else {
// //
// Set the attributes to be checked for common PCI devices and PPB or P2C // Set the attributes to be checked for common PCI devices and PPB or P2C
// Since some devices only support part of them, it is better to set the // Since some devices only support part of them, it is better to set the
@ -1100,30 +1104,30 @@ Returns:
/* /*
if (IS_PCI_IDE(&PciIoDevice->Pci)) { if (IS_PCI_IDE(&PciIoDevice->Pci)) {
PciIo = &PciIoDevice->PciIo; PciIo = &PciIoDevice->PciIo;
PciIo->Pci.Read ( PciIoRead (
PciIo, PciIo,
EfiPciIoWidthUint8, EfiPciIoWidthUint8,
0x09, 0x09,
1, 1,
&IdePI &IdePI
); );
// //
// Set native mode if it can be supported // Set native mode if it can be supported
// //
IdePI |= (((IdePI & 0x0F) >> 1) & 0x05); IdePI |= (((IdePI & 0x0F) >> 1) & 0x05);
PciIo->Pci.Write ( PciIoWrite (
PciIo, PciIo,
EfiPciIoWidthUint8, EfiPciIoWidthUint8,
0x09, 0x09,
1, 1,
&IdePI &IdePI
); );
} }
*/ */
} }
@ -1135,7 +1139,7 @@ Returns:
if (IS_CARDBUS_BRIDGE (&PciIoDevice->Pci)) { if (IS_CARDBUS_BRIDGE (&PciIoDevice->Pci)) {
FastB2BSupport = FALSE; FastB2BSupport = FALSE;
} }
// //
// For RootBridge, PPB , P2C, go recursively to traverse all its children // For RootBridge, PPB , P2C, go recursively to traverse all its children
// //
@ -1216,45 +1220,28 @@ Returns:
UINTN BarIndex; UINTN BarIndex;
UINTN BarEndIndex; UINTN BarEndIndex;
BOOLEAN SetFlag; BOOLEAN SetFlag;
EFI_PCI_DEVICE_INFO PciDeviceInfo;
VOID *Configuration; VOID *Configuration;
EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr; EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;
Configuration = NULL; Configuration = NULL;
//
// It can only be supported after the Incompatible PCI Device
// Support Protocol has been installed
//
if (gEfiIncompatiblePciDeviceSupport == NULL) {
Status = gBS->LocateProtocol (
&gEfiIncompatiblePciDeviceSupportProtocolGuid,
NULL,
(VOID **) &gEfiIncompatiblePciDeviceSupport
);
if (EFI_ERROR (Status)) {
return EFI_UNSUPPORTED;
}
}
// //
// Check whether the device belongs to incompatible devices or not // Check whether the device belongs to incompatible devices or not
// If it is , then get its special requirement in the ACPI table // If it is , then get its special requirement in the ACPI table
// //
Status = gEfiIncompatiblePciDeviceSupport->CheckDevice ( PciDeviceInfo.VendorID = PciIoDevice->Pci.Hdr.VendorId;
gEfiIncompatiblePciDeviceSupport, PciDeviceInfo.DeviceID = PciIoDevice->Pci.Hdr.DeviceId;
PciIoDevice->Pci.Hdr.VendorId, PciDeviceInfo.RevisionID = PciIoDevice->Pci.Hdr.RevisionID;
PciIoDevice->Pci.Hdr.DeviceId, PciDeviceInfo.SubsystemVendorID = PciIoDevice->Pci.Device.SubsystemVendorID;
PciIoDevice->Pci.Hdr.RevisionID, PciDeviceInfo.SubsystemID = PciIoDevice->Pci.Device.SubsystemID;
PciIoDevice->Pci.Device.SubsystemVendorID,
PciIoDevice->Pci.Device.SubsystemID, Status = PciResourceUpdateCheck (&PciDeviceInfo, &Configuration);
&Configuration
);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
return Status; return Status;
} }
// //
// Update PCI device information from the ACPI table // Update PCI device information from the ACPI table
// //
@ -1289,7 +1276,7 @@ Returns:
SetFlag = FALSE; SetFlag = FALSE;
switch (Ptr->ResType) { switch (Ptr->ResType) {
case ACPI_ADDRESS_SPACE_TYPE_MEM: case ACPI_ADDRESS_SPACE_TYPE_MEM:
// //
// Make sure the bar is memory type // Make sure the bar is memory type
// //
@ -1299,7 +1286,7 @@ Returns:
break; break;
case ACPI_ADDRESS_SPACE_TYPE_IO: case ACPI_ADDRESS_SPACE_TYPE_IO:
// //
// Make sure the bar is IO type // Make sure the bar is IO type
// //
@ -1310,7 +1297,7 @@ Returns:
} }
if (SetFlag) { if (SetFlag) {
// //
// Update the new alignment for the device // Update the new alignment for the device
// //
@ -1367,9 +1354,9 @@ Returns:
// //
// Check the validity of the parameter // Check the validity of the parameter
// //
if (NewAlignment != PCI_BAR_EVEN_ALIGN && if (NewAlignment != PCI_BAR_EVEN_ALIGN &&
NewAlignment != PCI_BAR_SQUAD_ALIGN && NewAlignment != PCI_BAR_SQUAD_ALIGN &&
NewAlignment != PCI_BAR_DQUAD_ALIGN ) { NewAlignment != PCI_BAR_DQUAD_ALIGN ) {
*Alignment = NewAlignment; *Alignment = NewAlignment;
return ; return ;
} }
@ -1384,7 +1371,7 @@ Returns:
OldAlignment = RShiftU64 (OldAlignment, 4); OldAlignment = RShiftU64 (OldAlignment, 4);
ShiftBit += 4; ShiftBit += 4;
} }
// //
// Adjust the alignment to even, quad or double quad boundary // Adjust the alignment to even, quad or double quad boundary
// //
@ -1401,7 +1388,7 @@ Returns:
OldAlignment = OldAlignment + 8 - (OldAlignment & 0x07); OldAlignment = OldAlignment + 8 - (OldAlignment & 0x07);
} }
} }
// //
// Update the old value // Update the old value
// //
@ -1563,7 +1550,7 @@ Returns:
for (Data = Value; Data != 0; Data >>= 1) { for (Data = Value; Data != 0; Data >>= 1) {
Index ++; Index ++;
} }
Value |= ((UINT32)(-1) << Index); Value |= ((UINT32)(-1) << Index);
// //
// Calculate the size of 64bit bar // Calculate the size of 64bit bar
@ -1587,7 +1574,7 @@ Returns:
break; break;
} }
} }
// //
// Check the length again so as to keep compatible with some special bars // Check the length again so as to keep compatible with some special bars
// //
@ -1596,7 +1583,7 @@ Returns:
PciIoDevice->PciBar[BarIndex].BaseAddress = 0; PciIoDevice->PciBar[BarIndex].BaseAddress = 0;
PciIoDevice->PciBar[BarIndex].Alignment = 0; PciIoDevice->PciBar[BarIndex].Alignment = 0;
} }
// //
// Increment number of bar // Increment number of bar
// //
@ -1610,7 +1597,7 @@ InitializePciDevice (
/*++ /*++
Routine Description: Routine Description:
This routine is used to initialize the bar of a PCI device This routine is used to initialize the bar of a PCI device
It can be called typically when a device is going to be rejected It can be called typically when a device is going to be rejected
@ -1635,7 +1622,7 @@ Returns:
// has not been alloacted // has not been alloacted
// //
for (Offset = 0x10; Offset <= 0x24; Offset += sizeof (UINT32)) { for (Offset = 0x10; Offset <= 0x24; Offset += sizeof (UINT32)) {
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, Offset, 1, &gAllOne); PciIoWrite (PciIo, EfiPciIoWidthUint32, Offset, 1, &gAllOne);
} }
return EFI_SUCCESS; return EFI_SUCCESS;
@ -1668,28 +1655,28 @@ Returns:
// Io32, pMem32, pMem64 to quiescent state // Io32, pMem32, pMem64 to quiescent state
// Resource base all ones, Resource limit all zeros // Resource base all ones, Resource limit all zeros
// //
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &gAllOne); PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &gAllOne);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1D, 1, &gAllZero); PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x1D, 1, &gAllZero);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x20, 1, &gAllOne); PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x20, 1, &gAllOne);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x22, 1, &gAllZero); PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x22, 1, &gAllZero);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x24, 1, &gAllOne); PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x24, 1, &gAllOne);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x26, 1, &gAllZero); PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x26, 1, &gAllZero);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x28, 1, &gAllOne); PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x28, 1, &gAllOne);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x2C, 1, &gAllZero); PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x2C, 1, &gAllZero);
// //
// don't support use io32 as for now // don't support use io32 as for now
// //
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x30, 1, &gAllOne); PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x30, 1, &gAllOne);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x32, 1, &gAllZero); PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x32, 1, &gAllZero);
// //
// Force Interrupt line to zero for cards that come up randomly // Force Interrupt line to zero for cards that come up randomly
// //
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &gAllZero); PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &gAllZero);
return EFI_SUCCESS; return EFI_SUCCESS;
} }
@ -1721,22 +1708,22 @@ Returns:
// Io32, pMem32, pMem64 to quiescent state( // Io32, pMem32, pMem64 to quiescent state(
// Resource base all ones, Resource limit all zeros // Resource base all ones, Resource limit all zeros
// //
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x1c, 1, &gAllOne); PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x1c, 1, &gAllOne);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x20, 1, &gAllZero); PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x20, 1, &gAllZero);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x24, 1, &gAllOne); PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x24, 1, &gAllOne);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x28, 1, &gAllZero); PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x28, 1, &gAllZero);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x2c, 1, &gAllOne); PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x2c, 1, &gAllOne);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x30, 1, &gAllZero); PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x30, 1, &gAllZero);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x34, 1, &gAllOne); PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x34, 1, &gAllOne);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x38, 1, &gAllZero); PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x38, 1, &gAllZero);
// //
// Force Interrupt line to zero for cards that come up randomly // Force Interrupt line to zero for cards that come up randomly
// //
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &gAllZero); PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &gAllZero);
return EFI_SUCCESS; return EFI_SUCCESS;
} }
@ -1845,7 +1832,7 @@ PciEnumeratorLight (
Routine Description: Routine Description:
This routine is used to enumerate entire pci bus system This routine is used to enumerate entire pci bus system
in a given platform in a given platform
Arguments: Arguments:
@ -1910,7 +1897,7 @@ Returns:
Descriptors++; Descriptors++;
continue; continue;
} }
// //
// Record the root bridge io protocol // Record the root bridge io protocol
// //
@ -1922,7 +1909,7 @@ Returns:
); );
if (!EFI_ERROR (Status)) { if (!EFI_ERROR (Status)) {
// //
// Remove those PCI devices which are rejected when full enumeration // Remove those PCI devices which are rejected when full enumeration
// //
@ -1975,9 +1962,9 @@ Arguments:
MinBus - The min bus. MinBus - The min bus.
MaxBus - The max bus. MaxBus - The max bus.
BusRange - The bus range. BusRange - The bus range.
Returns: Returns:
Status Code. Status Code.
--*/ --*/
@ -2129,11 +2116,11 @@ Returns:
} }
if (TestValue & 0x01) { if (TestValue & 0x01) {
// //
// IO Bar // IO Bar
// //
Mask = 0xFFFFFFFC; Mask = 0xFFFFFFFC;
TestValue = TestValue & Mask; TestValue = TestValue & Mask;
if ((TestValue != 0) && (TestValue == (OldValue & Mask))) { if ((TestValue != 0) && (TestValue == (OldValue & Mask))) {
@ -2141,26 +2128,26 @@ Returns:
} }
} else { } else {
// //
// Mem Bar // Mem Bar
// //
Mask = 0xFFFFFFF0; Mask = 0xFFFFFFF0;
TestValue = TestValue & Mask; TestValue = TestValue & Mask;
if ((TestValue & 0x07) == 0x04) { if ((TestValue & 0x07) == 0x04) {
// //
// Mem64 or PMem64 // Mem64 or PMem64
// //
BarOffset += sizeof (UINT32); BarOffset += sizeof (UINT32);
if ((TestValue != 0) && (TestValue == (OldValue & Mask))) { if ((TestValue != 0) && (TestValue == (OldValue & Mask))) {
// //
// Test its high 32-Bit BAR // Test its high 32-Bit BAR
// //
Status = BarExisted (PciIoDevice, BarOffset, &TestValue, &OldValue); Status = BarExisted (PciIoDevice, BarOffset, &TestValue, &OldValue);
if (TestValue == OldValue) { if (TestValue == OldValue) {
return TRUE; return TRUE;
@ -2168,7 +2155,7 @@ Returns:
} }
} else { } else {
// //
// Mem32 or PMem32 // Mem32 or PMem32
// //
@ -2207,7 +2194,7 @@ Returns:
EFI_STATUS Status; EFI_STATUS Status;
PCI_TYPE00 Pci; PCI_TYPE00 Pci;
UINT8 Device; UINT8 Device;
UINT32 Register; UINT32 Register;
UINT8 Func; UINT8 Func;
UINT64 Address; UINT64 Address;
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo; EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
@ -2231,9 +2218,10 @@ Returns:
if (!EFI_ERROR (Status) && (IS_PCI_BRIDGE (&Pci))) { if (!EFI_ERROR (Status) && (IS_PCI_BRIDGE (&Pci))) {
Register = 0; Register = 0;
Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x18); Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x18);
Status = PciRootBridgeIo->Pci.Read ( Status = PciRootBridgeIoRead (
PciRootBridgeIo, PciRootBridgeIo,
EfiPciWidthUint32, &Pci,
EfiPciWidthUint32,
Address, Address,
1, 1,
&Register &Register
@ -2242,9 +2230,10 @@ Returns:
// Reset register 18h, 19h, 1Ah on PCI Bridge // Reset register 18h, 19h, 1Ah on PCI Bridge
// //
Register &= 0xFF000000; Register &= 0xFF000000;
Status = PciRootBridgeIo->Pci.Write ( Status = PciRootBridgeIoWrite (
PciRootBridgeIo, PciRootBridgeIo,
EfiPciWidthUint32, &Pci,
EfiPciWidthUint32,
Address, Address,
1, 1,
&Register &Register

1009
EdkModulePkg/Bus/Pci/PciBus/Dxe/PciLib.c
View File

File diff suppressed because it is too large Load Diff

126
EdkModulePkg/Bus/Pci/PciBus/Dxe/PciLib.h
View File

@ -1,18 +1,18 @@
/*++ /*++
Copyright (c) 2006, Intel Corporation Copyright (c) 2006 - 2007, Intel Corporation
All rights reserved. This program and the accompanying materials All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name: Module Name:
PciLib.h PciLib.h
Abstract: Abstract:
PCI Bus Driver Lib header file. PCI Bus Driver Lib header file.
@ -26,6 +26,15 @@ Revision History
#ifndef _EFI_PCI_LIB_H #ifndef _EFI_PCI_LIB_H
#define _EFI_PCI_LIB_H #define _EFI_PCI_LIB_H
//
// Mask definistions for PCD PcdPciIncompatibleDeviceSupportMask
//
#define PCI_INCOMPATIBLE_ACPI_RESOURCE_SUPPORT 0x01
#define PCI_INCOMPATIBLE_READ_SUPPORT 0x02
#define PCI_INCOMPATIBLE_WRITE_SUPPORT 0x04
#define PCI_INCOMPATIBLE_REGISTER_UPDATE_SUPPORT 0x08
#define PCI_INCOMPATIBLE_ACCESS_WIDTH_SUPPORT 0x0a
VOID VOID
InstallHotPlugRequestProtocol ( InstallHotPlugRequestProtocol (
IN EFI_STATUS *Status IN EFI_STATUS *Status
@ -274,4 +283,103 @@ Returns:
--*/ --*/
; ;
/**
Read PCI configuration space through EFI_PCI_IO_PROTOCOL.
@param PciIo A pointer to the EFI_PCI_O_PROTOCOL.
@param Width Signifies the width of the memory operations.
@Param Address The address within the PCI configuration space for the PCI controller.
@param Buffer For read operations, the destination buffer to store the results. For
write operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
@retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
@retval EFI_INVALID_PARAMETER Buffer is NULL.
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
**/
EFI_STATUS
PciIoRead (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
IN UINT32 Address,
IN UINTN Count,
IN OUT VOID *Buffer
);
/**
Write PCI configuration space through EFI_PCI_IO_PROTOCOL.
@param PciIo A pointer to the EFI_PCI_O_PROTOCOL.
@param Width Signifies the width of the memory operations.
@Param Address The address within the PCI configuration space for the PCI controller.
@param Buffer For read operations, the destination buffer to store the results. For
write operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
@retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
@retval EFI_INVALID_PARAMETER Buffer is NULL.
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
**/
EFI_STATUS
PciIoWrite (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
IN UINT32 Address,
IN UINTN Count,
IN OUT VOID *Buffer
);
/**
Write PCI configuration space through EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
@param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
@param Pci A pointer to PCI_TYPE00.
@param Width Signifies the width of the memory operations.
@Param Address The address within the PCI configuration space for the PCI controller.
@param Buffer For read operations, the destination buffer to store the results. For
write operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
@retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
@retval EFI_INVALID_PARAMETER Buffer is NULL.
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
**/
EFI_STATUS
PciRootBridgeIoWrite (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,
IN PCI_TYPE00 *Pci,
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 Address,
IN UINTN Count,
IN OUT VOID *Buffer
);
/**
Read PCI configuration space through EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
@param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
@param Pci A pointer to PCI_TYPE00.
@param Width Signifies the width of the memory operations.
@Param Address The address within the PCI configuration space for the PCI controller.
@param Buffer For read operations, the destination buffer to store the results. For
write operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
@retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
@retval EFI_INVALID_PARAMETER Buffer is NULL.
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
**/
EFI_STATUS
PciRootBridgeIoRead (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,
IN PCI_TYPE00 *Pci,
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 Address,
IN UINTN Count,
IN OUT VOID *Buffer
);
#endif #endif

32
EdkModulePkg/Bus/Pci/PciBus/Dxe/PciOptionRomSupport.c
View File

@ -1,18 +1,18 @@
/*++ /*++
Copyright (c) 2006, Intel Corporation Copyright (c) 2006 - 2007, Intel Corporation
All rights reserved. This program and the accompanying materials All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name: Module Name:
PciOptionRomSupport.c PciOptionRomSupport.c
Abstract: Abstract:
PCI Bus Driver PCI Bus Driver
@ -88,8 +88,9 @@ Returns:
AllOnes = 0xfffffffe; AllOnes = 0xfffffffe;
Address = EFI_PCI_ADDRESS (Bus, Device, Function, RomBarIndex); Address = EFI_PCI_ADDRESS (Bus, Device, Function, RomBarIndex);
Status = PciRootBridgeIo->Pci.Write ( Status = PciRootBridgeIoWrite (
PciRootBridgeIo, PciRootBridgeIo,
&PciIoDevice->Pci,
EfiPciWidthUint32, EfiPciWidthUint32,
Address, Address,
1, 1,
@ -98,12 +99,13 @@ Returns:
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
return Status; return Status;
} }
// //
// read back // read back
// //
Status = PciRootBridgeIo->Pci.Read ( Status = PciRootBridgeIoRead (
PciRootBridgeIo, PciRootBridgeIo,
&PciIoDevice->Pci,
EfiPciWidthUint32, EfiPciWidthUint32,
Address, Address,
1, 1,
@ -334,7 +336,7 @@ Returns:
// Clear all bars // Clear all bars
// //
for (Offset = 0x10; Offset <= 0x24; Offset += sizeof (UINT32)) { for (Offset = 0x10; Offset <= 0x24; Offset += sizeof (UINT32)) {
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, Offset, 1, &gAllZero); PciIoWrite (PciIo, EfiPciIoWidthUint32, Offset, 1, &gAllZero);
} }
// //
@ -342,7 +344,7 @@ Returns:
// enable its decoder // enable its decoder
// //
Value32 = RomBar | 0x1; Value32 = RomBar | 0x1;
PciIo->Pci.Write ( PciIoWrite (
PciIo, PciIo,
(EFI_PCI_IO_PROTOCOL_WIDTH) EfiPciWidthUint32, (EFI_PCI_IO_PROTOCOL_WIDTH) EfiPciWidthUint32,
RomBarIndex, RomBarIndex,
@ -376,7 +378,7 @@ Returns:
// disable rom decode // disable rom decode
// //
Value32 = 0xFFFFFFFE; Value32 = 0xFFFFFFFE;
PciIo->Pci.Write ( PciIoWrite (
PciIo, PciIo,
(EFI_PCI_IO_PROTOCOL_WIDTH) EfiPciWidthUint32, (EFI_PCI_IO_PROTOCOL_WIDTH) EfiPciWidthUint32,
RomBarIndex, RomBarIndex,

32
EdkModulePkg/Bus/Pci/PciBus/Dxe/PciPowerManagement.c
View File

@ -1,18 +1,18 @@
/*++ /*++
Copyright (c) 2006, Intel Corporation Copyright (c) 2006 - 2007, Intel Corporation
All rights reserved. This program and the accompanying materials All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name: Module Name:
PciPowerManagement.c PciPowerManagement.c
Abstract: Abstract:
PCI Bus Driver PCI Bus Driver
@ -71,13 +71,13 @@ Returns:
// //
// Write PMCSR // Write PMCSR
// //
PciIoDevice->PciIo.Pci.Write ( PciIoWrite (
&PciIoDevice->PciIo, &PciIoDevice->PciIo,
EfiPciIoWidthUint16, EfiPciIoWidthUint16,
PowerManagementRegBlock + 4, PowerManagementRegBlock + 4,
1, 1,
&PMCSR &PMCSR
); );
return EFI_SUCCESS; return EFI_SUCCESS;
} }

80
EdkModulePkg/Bus/Pci/PciBus/Dxe/PciResourceSupport.c
View File

@ -1,18 +1,18 @@
/*++ /*++
Copyright (c) 2006, Intel Corporation Copyright (c) 2006 - 2007, Intel Corporation
All rights reserved. This program and the accompanying materials All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name: Module Name:
PciResourceSupport.c PciResourceSupport.c
Abstract: Abstract:
PCI Bus Driver PCI Bus Driver
@ -1222,7 +1222,7 @@ Returns:
case PciBarTypeMem32: case PciBarTypeMem32:
case PciBarTypePMem32: case PciBarTypePMem32:
PciIo->Pci.Write ( PciIoWrite (
PciIo, PciIo,
EfiPciIoWidthUint32, EfiPciIoWidthUint32,
(Node->PciDev->PciBar[Node->Bar]).Offset, (Node->PciDev->PciBar[Node->Bar]).Offset,
@ -1239,7 +1239,7 @@ Returns:
Address32 = (UINT32) (Address & 0x00000000FFFFFFFF); Address32 = (UINT32) (Address & 0x00000000FFFFFFFF);
PciIo->Pci.Write ( PciIoWrite (
PciIo, PciIo,
EfiPciIoWidthUint32, EfiPciIoWidthUint32,
(Node->PciDev->PciBar[Node->Bar]).Offset, (Node->PciDev->PciBar[Node->Bar]).Offset,
@ -1249,7 +1249,7 @@ Returns:
Address32 = (UINT32) RShiftU64 (Address, 32); Address32 = (UINT32) RShiftU64 (Address, 32);
PciIo->Pci.Write ( PciIoWrite (
PciIo, PciIo,
EfiPciIoWidthUint32, EfiPciIoWidthUint32,
(UINT8) ((Node->PciDev->PciBar[Node->Bar]).Offset + 4), (UINT8) ((Node->PciDev->PciBar[Node->Bar]).Offset + 4),
@ -1317,7 +1317,7 @@ Returns:
case PPB_BAR_0: case PPB_BAR_0:
case PPB_BAR_1: case PPB_BAR_1:
PciIo->Pci.Write ( PciIoWrite (
PciIo, PciIo,
EfiPciIoWidthUint32, EfiPciIoWidthUint32,
(Node->PciDev->PciBar[Node->Bar]).Offset, (Node->PciDev->PciBar[Node->Bar]).Offset,
@ -1333,7 +1333,7 @@ Returns:
case PPB_IO_RANGE: case PPB_IO_RANGE:
Address32 = ((UINT32) (Address)) >> 8; Address32 = ((UINT32) (Address)) >> 8;
PciIo->Pci.Write ( PciIoWrite (
PciIo, PciIo,
EfiPciIoWidthUint8, EfiPciIoWidthUint8,
0x1C, 0x1C,
@ -1342,7 +1342,7 @@ Returns:
); );
Address32 >>= 8; Address32 >>= 8;
PciIo->Pci.Write ( PciIoWrite (
PciIo, PciIo,
EfiPciIoWidthUint16, EfiPciIoWidthUint16,
0x30, 0x30,
@ -1352,7 +1352,7 @@ Returns:
Address32 = (UINT32) (Address + Node->Length - 1); Address32 = (UINT32) (Address + Node->Length - 1);
Address32 = ((UINT32) (Address32)) >> 8; Address32 = ((UINT32) (Address32)) >> 8;
PciIo->Pci.Write ( PciIoWrite (
PciIo, PciIo,
EfiPciIoWidthUint8, EfiPciIoWidthUint8,
0x1D, 0x1D,
@ -1361,7 +1361,7 @@ Returns:
); );
Address32 >>= 8; Address32 >>= 8;
PciIo->Pci.Write ( PciIoWrite (
PciIo, PciIo,
EfiPciIoWidthUint16, EfiPciIoWidthUint16,
0x32, 0x32,
@ -1376,7 +1376,7 @@ Returns:
case PPB_MEM32_RANGE: case PPB_MEM32_RANGE:
Address32 = ((UINT32) (Address)) >> 16; Address32 = ((UINT32) (Address)) >> 16;
PciIo->Pci.Write ( PciIoWrite (
PciIo, PciIo,
EfiPciIoWidthUint16, EfiPciIoWidthUint16,
0x20, 0x20,
@ -1386,7 +1386,7 @@ Returns:
Address32 = (UINT32) (Address + Node->Length - 1); Address32 = (UINT32) (Address + Node->Length - 1);
Address32 = ((UINT32) (Address32)) >> 16; Address32 = ((UINT32) (Address32)) >> 16;
PciIo->Pci.Write ( PciIoWrite (
PciIo, PciIo,
EfiPciIoWidthUint16, EfiPciIoWidthUint16,
0x22, 0x22,
@ -1402,7 +1402,7 @@ Returns:
case PPB_PMEM64_RANGE: case PPB_PMEM64_RANGE:
Address32 = ((UINT32) (Address)) >> 16; Address32 = ((UINT32) (Address)) >> 16;
PciIo->Pci.Write ( PciIoWrite (
PciIo, PciIo,
EfiPciIoWidthUint16, EfiPciIoWidthUint16,
0x24, 0x24,
@ -1412,7 +1412,7 @@ Returns:
Address32 = (UINT32) (Address + Node->Length - 1); Address32 = (UINT32) (Address + Node->Length - 1);
Address32 = ((UINT32) (Address32)) >> 16; Address32 = ((UINT32) (Address32)) >> 16;
PciIo->Pci.Write ( PciIoWrite (
PciIo, PciIo,
EfiPciIoWidthUint16, EfiPciIoWidthUint16,
0x26, 0x26,
@ -1421,7 +1421,7 @@ Returns:
); );
Address32 = (UINT32) RShiftU64 (Address, 32); Address32 = (UINT32) RShiftU64 (Address, 32);
PciIo->Pci.Write ( PciIoWrite (
PciIo, PciIo,
EfiPciIoWidthUint32, EfiPciIoWidthUint32,
0x28, 0x28,
@ -1430,7 +1430,7 @@ Returns:
); );
Address32 = (UINT32) RShiftU64 ((Address + Node->Length - 1), 32); Address32 = (UINT32) RShiftU64 ((Address + Node->Length - 1), 32);
PciIo->Pci.Write ( PciIoWrite (
PciIo, PciIo,
EfiPciIoWidthUint32, EfiPciIoWidthUint32,
0x2C, 0x2C,
@ -1915,7 +1915,7 @@ Returns:
switch (Node->Bar) { switch (Node->Bar) {
case P2C_BAR_0: case P2C_BAR_0:
PciIo->Pci.Write ( PciIoWrite (
PciIo, PciIo,
EfiPciIoWidthUint32, EfiPciIoWidthUint32,
(Node->PciDev->PciBar[Node->Bar]).Offset, (Node->PciDev->PciBar[Node->Bar]).Offset,
@ -1928,7 +1928,7 @@ Returns:
break; break;
case P2C_MEM_1: case P2C_MEM_1:
PciIo->Pci.Write ( PciIoWrite (
PciIo, PciIo,
EfiPciIoWidthUint32, EfiPciIoWidthUint32,
0x1c, 0x1c,
@ -1937,7 +1937,7 @@ Returns:
); );
TempAddress = Address + Node->Length - 1; TempAddress = Address + Node->Length - 1;
PciIo->Pci.Write ( PciIoWrite (
PciIo, PciIo,
EfiPciIoWidthUint32, EfiPciIoWidthUint32,
0x20, 0x20,
@ -1950,7 +1950,7 @@ Returns:
// //
// Set non-prefetchable bit // Set non-prefetchable bit
// //
PciIo->Pci.Read ( PciIoRead (
PciIo, PciIo,
EfiPciIoWidthUint16, EfiPciIoWidthUint16,
0x3e, 0x3e,
@ -1959,7 +1959,7 @@ Returns:
); );
BridgeControl &= 0xfeff; BridgeControl &= 0xfeff;
PciIo->Pci.Write ( PciIoWrite (
PciIo, PciIo,
EfiPciIoWidthUint16, EfiPciIoWidthUint16,
0x3e, 0x3e,
@ -1972,7 +1972,7 @@ Returns:
// //
// Set pre-fetchable bit // Set pre-fetchable bit
// //
PciIo->Pci.Read ( PciIoRead (
PciIo, PciIo,
EfiPciIoWidthUint16, EfiPciIoWidthUint16,
0x3e, 0x3e,
@ -1981,7 +1981,7 @@ Returns:
); );
BridgeControl |= 0x0100; BridgeControl |= 0x0100;
PciIo->Pci.Write ( PciIoWrite (
PciIo, PciIo,
EfiPciIoWidthUint16, EfiPciIoWidthUint16,
0x3e, 0x3e,
@ -1997,7 +1997,7 @@ Returns:
break; break;
case P2C_MEM_2: case P2C_MEM_2:
PciIo->Pci.Write ( PciIoWrite (
PciIo, PciIo,
EfiPciIoWidthUint32, EfiPciIoWidthUint32,
0x24, 0x24,
@ -2007,7 +2007,7 @@ Returns:
TempAddress = Address + Node->Length - 1; TempAddress = Address + Node->Length - 1;
PciIo->Pci.Write ( PciIoWrite (
PciIo, PciIo,
EfiPciIoWidthUint32, EfiPciIoWidthUint32,
0x28, 0x28,
@ -2020,7 +2020,7 @@ Returns:
// //
// Set non-prefetchable bit // Set non-prefetchable bit
// //
PciIo->Pci.Read ( PciIoRead (
PciIo, PciIo,
EfiPciIoWidthUint16, EfiPciIoWidthUint16,
0x3e, 0x3e,
@ -2029,7 +2029,7 @@ Returns:
); );
BridgeControl &= 0xfdff; BridgeControl &= 0xfdff;
PciIo->Pci.Write ( PciIoWrite (
PciIo, PciIo,
EfiPciIoWidthUint16, EfiPciIoWidthUint16,
0x3e, 0x3e,
@ -2041,7 +2041,7 @@ Returns:
// //
// Set pre-fetchable bit // Set pre-fetchable bit
// //
PciIo->Pci.Read ( PciIoRead (
PciIo, PciIo,
EfiPciIoWidthUint16, EfiPciIoWidthUint16,
0x3e, 0x3e,
@ -2050,7 +2050,7 @@ Returns:
); );
BridgeControl |= 0x0200; BridgeControl |= 0x0200;
PciIo->Pci.Write ( PciIoWrite (
PciIo, PciIo,
EfiPciIoWidthUint16, EfiPciIoWidthUint16,
0x3e, 0x3e,
@ -2065,7 +2065,7 @@ Returns:
break; break;
case P2C_IO_1: case P2C_IO_1:
PciIo->Pci.Write ( PciIoWrite (
PciIo, PciIo,
EfiPciIoWidthUint32, EfiPciIoWidthUint32,
0x2c, 0x2c,
@ -2073,7 +2073,7 @@ Returns:
&Address &Address
); );
TempAddress = Address + Node->Length - 1; TempAddress = Address + Node->Length - 1;
PciIo->Pci.Write ( PciIoWrite (
PciIo, PciIo,
EfiPciIoWidthUint32, EfiPciIoWidthUint32,
0x30, 0x30,
@ -2088,7 +2088,7 @@ Returns:
break; break;
case P2C_IO_2: case P2C_IO_2:
PciIo->Pci.Write ( PciIoWrite (
PciIo, PciIo,
EfiPciIoWidthUint32, EfiPciIoWidthUint32,
0x34, 0x34,
@ -2097,7 +2097,7 @@ Returns:
); );
TempAddress = Address + Node->Length - 1; TempAddress = Address + Node->Length - 1;
PciIo->Pci.Write ( PciIoWrite (
PciIo, PciIo,
EfiPciIoWidthUint32, EfiPciIoWidthUint32,
0x38, 0x38,

45
EdkModulePkg/Bus/Pci/PciBus/Dxe/pcibus.c
View File

@ -1,24 +1,24 @@
/*++ /*++
Copyright (c) 2006, Intel Corporation Copyright (c) 2006 - 2007, Intel Corporation
All rights reserved. This program and the accompanying materials All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name: Module Name:
PciBus.c PciBus.c
Abstract: Abstract:
PCI Bus Driver PCI Bus Driver
Revision History Revision History
--*/ --*/
#include "pcibus.h" #include "pcibus.h"
@ -36,7 +36,6 @@ EFI_DRIVER_BINDING_PROTOCOL gPciBusDriverBinding = {
NULL NULL
}; };
EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *gEfiIncompatiblePciDeviceSupport = NULL;
EFI_HANDLE gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM]; EFI_HANDLE gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];
UINTN gPciHostBridgeNumber; UINTN gPciHostBridgeNumber;
BOOLEAN gFullEnumeration; BOOLEAN gFullEnumeration;
@ -68,8 +67,8 @@ Arguments:
Returns: Returns:
EFI_SUCCESS EFI_SUCCESS
EFI_DEVICE_ERROR EFI_DEVICE_ERROR
--*/ --*/
// TODO: ImageHandle - add argument and description to function comment // TODO: ImageHandle - add argument and description to function comment
@ -101,7 +100,7 @@ Routine Description:
Check to see if pci bus driver supports the given controller Check to see if pci bus driver supports the given controller
Arguments: Arguments:
IN EFI_DRIVER_BINDING_PROTOCOL *This, IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller, IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
@ -195,13 +194,13 @@ Routine Description:
Start to management the controller passed in Start to management the controller passed in
Arguments: Arguments:
IN EFI_DRIVER_BINDING_PROTOCOL *This, IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller, IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
Returns: Returns:
--*/ --*/
// TODO: This - add argument and description to function comment // TODO: This - add argument and description to function comment
@ -211,12 +210,6 @@ Returns:
{ {
EFI_STATUS Status; EFI_STATUS Status;
Status = gBS->LocateProtocol (
&gEfiIncompatiblePciDeviceSupportProtocolGuid,
NULL,
(VOID **) &gEfiIncompatiblePciDeviceSupport
);
// //
// If PCI Platform protocol is available, get it now. // If PCI Platform protocol is available, get it now.
// If the platform implements this, it must be installed before BDS phase // If the platform implements this, it must be installed before BDS phase
@ -240,12 +233,12 @@ Returns:
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
return Status; return Status;
} }
// //
// Enable PCI device specified by remaining device path. BDS or other driver can call the // Enable PCI device specified by remaining device path. BDS or other driver can call the
// start more than once. // start more than once.
// //
StartPciDevices (Controller, RemainingDevicePath); StartPciDevices (Controller, RemainingDevicePath);
return EFI_SUCCESS; return EFI_SUCCESS;
@ -267,7 +260,7 @@ Routine Description:
if all the the children get closed, close the protocol if all the the children get closed, close the protocol
Arguments: Arguments:
IN EFI_DRIVER_BINDING_PROTOCOL *This, IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller, IN EFI_HANDLE Controller,
IN UINTN NumberOfChildren, IN UINTN NumberOfChildren,
@ -275,7 +268,7 @@ Arguments:
Returns: Returns:
--*/ --*/
// TODO: This - add argument and description to function comment // TODO: This - add argument and description to function comment
// TODO: Controller - add argument and description to function comment // TODO: Controller - add argument and description to function comment

19
EdkModulePkg/Bus/Pci/PciBus/Dxe/pcibus.h
View File

@ -1,18 +1,18 @@
/*++ /*++
Copyright (c) 2006, Intel Corporation Copyright (c) 2006 - 2007, Intel Corporation
All rights reserved. This program and the accompanying materials All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name: Module Name:
pcibus.h pcibus.h
Abstract: Abstract:
PCI Bus Driver PCI Bus Driver
@ -216,7 +216,6 @@ typedef struct _PCI_IO_DEVICE {
// //
// Global Variables // Global Variables
// //
extern EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *gEfiIncompatiblePciDeviceSupport;
extern EFI_DRIVER_BINDING_PROTOCOL gPciBusDriverBinding; extern EFI_DRIVER_BINDING_PROTOCOL gPciBusDriverBinding;
extern EFI_COMPONENT_NAME_PROTOCOL gPciBusComponentName; extern EFI_COMPONENT_NAME_PROTOCOL gPciBusComponentName;
extern LIST_ENTRY gPciDevicePool; extern LIST_ENTRY gPciDevicePool;

40
EdkModulePkg/EdkModulePkg.fpd
View File

@ -3575,6 +3575,8 @@
<Instance ModuleGuid="4674739d-3195-4fb2-8094-ac1d22d00194" PackageGuid="5e0e9358-46b6-4ae2-8218-4ab8b9bbdcec"/> <Instance ModuleGuid="4674739d-3195-4fb2-8094-ac1d22d00194" PackageGuid="5e0e9358-46b6-4ae2-8218-4ab8b9bbdcec"/>
<Instance ModuleGuid="91c1677a-e57f-4191-8b8e-eb7711a716e0" PackageGuid="5e0e9358-46b6-4ae2-8218-4ab8b9bbdcec"/> <Instance ModuleGuid="91c1677a-e57f-4191-8b8e-eb7711a716e0" PackageGuid="5e0e9358-46b6-4ae2-8218-4ab8b9bbdcec"/>
<Instance ModuleGuid="be490364-73d2-420d-950e-f6450ca75dfb" PackageGuid="5e0e9358-46b6-4ae2-8218-4ab8b9bbdcec"/> <Instance ModuleGuid="be490364-73d2-420d-950e-f6450ca75dfb" PackageGuid="5e0e9358-46b6-4ae2-8218-4ab8b9bbdcec"/>
<!--Pkg: EdkModulePkg Mod: EdkDxePciIncompatibleDeviceSuppportLib Path: EdkModulePkg\Library\EdkDxePciIncompatibleDeviceSupportLib\EdkDxePciIncompatibleDeviceSupportLib.msa-->
<Instance ModuleGuid="1ca1c1f9-5baf-4204-b6e5-5e24109a4e4e" ModuleVersion="1.0" PackageGuid="68169ab0-d41b-4009-9060-292c253ac43d" PackageVersion="0.3"/>
</Libraries> </Libraries>
<PcdBuildDefinition> <PcdBuildDefinition>
<PcdData ItemType="FIXED_AT_BUILD"> <PcdData ItemType="FIXED_AT_BUILD">
@ -3689,6 +3691,14 @@
<MaxDatumSize>4</MaxDatumSize> <MaxDatumSize>4</MaxDatumSize>
<Value>320</Value> <Value>320</Value>
</PcdData> </PcdData>
<PcdData ItemType="FIXED_AT_BUILD">
<C_Name>PcdPciIncompatibleDeviceSupportMask</C_Name>
<Token>0x0001003f</Token>
<TokenSpaceGuidCName>gEfiEdkModulePkgTokenSpaceGuid</TokenSpaceGuidCName>
<DatumType>UINT8</DatumType>
<MaxDatumSize>1</MaxDatumSize>
<Value>0x0</Value>
</PcdData>
</PcdBuildDefinition> </PcdBuildDefinition>
<ModuleSaBuildOptions> <ModuleSaBuildOptions>
<FvBinding>NULL</FvBinding> <FvBinding>NULL</FvBinding>
@ -9019,6 +9029,8 @@
<Instance ModuleGuid="4674739d-3195-4fb2-8094-ac1d22d00194" PackageGuid="5e0e9358-46b6-4ae2-8218-4ab8b9bbdcec"/> <Instance ModuleGuid="4674739d-3195-4fb2-8094-ac1d22d00194" PackageGuid="5e0e9358-46b6-4ae2-8218-4ab8b9bbdcec"/>
<Instance ModuleGuid="91c1677a-e57f-4191-8b8e-eb7711a716e0" PackageGuid="5e0e9358-46b6-4ae2-8218-4ab8b9bbdcec"/> <Instance ModuleGuid="91c1677a-e57f-4191-8b8e-eb7711a716e0" PackageGuid="5e0e9358-46b6-4ae2-8218-4ab8b9bbdcec"/>
<Instance ModuleGuid="be490364-73d2-420d-950e-f6450ca75dfb" PackageGuid="5e0e9358-46b6-4ae2-8218-4ab8b9bbdcec"/> <Instance ModuleGuid="be490364-73d2-420d-950e-f6450ca75dfb" PackageGuid="5e0e9358-46b6-4ae2-8218-4ab8b9bbdcec"/>
<!--Pkg: EdkModulePkg Mod: EdkDxePciIncompatibleDeviceSuppportLib Path: EdkModulePkg\Library\EdkDxePciIncompatibleDeviceSupportLib\EdkDxePciIncompatibleDeviceSupportLib.msa-->
<Instance ModuleGuid="1ca1c1f9-5baf-4204-b6e5-5e24109a4e4e" ModuleVersion="1.0" PackageGuid="68169ab0-d41b-4009-9060-292c253ac43d" PackageVersion="0.3"/>
</Libraries> </Libraries>
<PcdBuildDefinition> <PcdBuildDefinition>
<PcdData ItemType="FIXED_AT_BUILD"> <PcdData ItemType="FIXED_AT_BUILD">
@ -9133,6 +9145,14 @@
<MaxDatumSize>4</MaxDatumSize> <MaxDatumSize>4</MaxDatumSize>
<Value>320</Value> <Value>320</Value>
</PcdData> </PcdData>
<PcdData ItemType="FIXED_AT_BUILD">
<C_Name>PcdPciIncompatibleDeviceSupportMask</C_Name>
<Token>0x0001003f</Token>
<TokenSpaceGuidCName>gEfiEdkModulePkgTokenSpaceGuid</TokenSpaceGuidCName>
<DatumType>UINT8</DatumType>
<MaxDatumSize>1</MaxDatumSize>
<Value>0x0</Value>
</PcdData>
</PcdBuildDefinition> </PcdBuildDefinition>
<ModuleSaBuildOptions> <ModuleSaBuildOptions>
<FvBinding>NULL</FvBinding> <FvBinding>NULL</FvBinding>
@ -13569,6 +13589,8 @@
<Instance ModuleGuid="4674739d-3195-4fb2-8094-ac1d22d00194" PackageGuid="5e0e9358-46b6-4ae2-8218-4ab8b9bbdcec"/> <Instance ModuleGuid="4674739d-3195-4fb2-8094-ac1d22d00194" PackageGuid="5e0e9358-46b6-4ae2-8218-4ab8b9bbdcec"/>
<Instance ModuleGuid="91c1677a-e57f-4191-8b8e-eb7711a716e0" PackageGuid="5e0e9358-46b6-4ae2-8218-4ab8b9bbdcec"/> <Instance ModuleGuid="91c1677a-e57f-4191-8b8e-eb7711a716e0" PackageGuid="5e0e9358-46b6-4ae2-8218-4ab8b9bbdcec"/>
<Instance ModuleGuid="be490364-73d2-420d-950e-f6450ca75dfb" PackageGuid="5e0e9358-46b6-4ae2-8218-4ab8b9bbdcec"/> <Instance ModuleGuid="be490364-73d2-420d-950e-f6450ca75dfb" PackageGuid="5e0e9358-46b6-4ae2-8218-4ab8b9bbdcec"/>
<!--Pkg: EdkModulePkg Mod: EdkDxePciIncompatibleDeviceSuppportLib Path: EdkModulePkg\Library\EdkDxePciIncompatibleDeviceSupportLib\EdkDxePciIncompatibleDeviceSupportLib.msa-->
<Instance ModuleGuid="1ca1c1f9-5baf-4204-b6e5-5e24109a4e4e" ModuleVersion="1.0" PackageGuid="68169ab0-d41b-4009-9060-292c253ac43d" PackageVersion="0.3"/>
</Libraries> </Libraries>
<PcdBuildDefinition> <PcdBuildDefinition>
<PcdData ItemType="FIXED_AT_BUILD"> <PcdData ItemType="FIXED_AT_BUILD">
@ -13683,6 +13705,14 @@
<MaxDatumSize>4</MaxDatumSize> <MaxDatumSize>4</MaxDatumSize>
<Value>320</Value> <Value>320</Value>
</PcdData> </PcdData>
<PcdData ItemType="FIXED_AT_BUILD">
<C_Name>PcdPciIncompatibleDeviceSupportMask</C_Name>
<Token>0x0001003f</Token>
<TokenSpaceGuidCName>gEfiEdkModulePkgTokenSpaceGuid</TokenSpaceGuidCName>
<DatumType>UINT8</DatumType>
<MaxDatumSize>1</MaxDatumSize>
<Value>0x0</Value>
</PcdData>
</PcdBuildDefinition> </PcdBuildDefinition>
<ModuleSaBuildOptions> <ModuleSaBuildOptions>
<FvBinding>NULL</FvBinding> <FvBinding>NULL</FvBinding>
@ -17741,6 +17771,8 @@
<Instance ModuleGuid="4674739d-3195-4fb2-8094-ac1d22d00194" PackageGuid="5e0e9358-46b6-4ae2-8218-4ab8b9bbdcec"/> <Instance ModuleGuid="4674739d-3195-4fb2-8094-ac1d22d00194" PackageGuid="5e0e9358-46b6-4ae2-8218-4ab8b9bbdcec"/>
<Instance ModuleGuid="91c1677a-e57f-4191-8b8e-eb7711a716e0" PackageGuid="5e0e9358-46b6-4ae2-8218-4ab8b9bbdcec"/> <Instance ModuleGuid="91c1677a-e57f-4191-8b8e-eb7711a716e0" PackageGuid="5e0e9358-46b6-4ae2-8218-4ab8b9bbdcec"/>
<Instance ModuleGuid="be490364-73d2-420d-950e-f6450ca75dfb" PackageGuid="5e0e9358-46b6-4ae2-8218-4ab8b9bbdcec"/> <Instance ModuleGuid="be490364-73d2-420d-950e-f6450ca75dfb" PackageGuid="5e0e9358-46b6-4ae2-8218-4ab8b9bbdcec"/>
<!--Pkg: EdkModulePkg Mod: EdkDxePciIncompatibleDeviceSuppportLib Path: EdkModulePkg\Library\EdkDxePciIncompatibleDeviceSupportLib\EdkDxePciIncompatibleDeviceSupportLib.msa-->
<Instance ModuleGuid="1ca1c1f9-5baf-4204-b6e5-5e24109a4e4e" ModuleVersion="1.0" PackageGuid="68169ab0-d41b-4009-9060-292c253ac43d" PackageVersion="0.3"/>
</Libraries> </Libraries>
<PcdBuildDefinition> <PcdBuildDefinition>
<PcdData ItemType="FIXED_AT_BUILD"> <PcdData ItemType="FIXED_AT_BUILD">
@ -17855,6 +17887,14 @@
<MaxDatumSize>4</MaxDatumSize> <MaxDatumSize>4</MaxDatumSize>
<Value>320</Value> <Value>320</Value>
</PcdData> </PcdData>
<PcdData ItemType="FIXED_AT_BUILD">
<C_Name>PcdPciIncompatibleDeviceSupportMask</C_Name>
<Token>0x0001003f</Token>
<TokenSpaceGuidCName>gEfiEdkModulePkgTokenSpaceGuid</TokenSpaceGuidCName>
<DatumType>UINT8</DatumType>
<MaxDatumSize>1</MaxDatumSize>
<Value>0x0</Value>
</PcdData>
</PcdBuildDefinition> </PcdBuildDefinition>
<ModuleSaBuildOptions> <ModuleSaBuildOptions>
<FvBinding>NULL</FvBinding> <FvBinding>NULL</FvBinding>

30
EdkModulePkg/EdkModulePkg.spd
View File

@ -8,7 +8,7 @@
<Description>This Module provides standard reference information for EFI/Tiano implementations.</Description> <Description>This Module provides standard reference information for EFI/Tiano implementations.</Description>
<Copyright>Copyright (c) 2006 - 2007, Intel Corporation.</Copyright> <Copyright>Copyright (c) 2006 - 2007, Intel Corporation.</Copyright>
<License>All rights reserved. <License>All rights reserved.
This program and the accompanying materials are licensed and made available This program and the accompanying materials are licensed and made available
under the terms and conditions of the BSD License which accompanies this distribution. under the terms and conditions of the BSD License which accompanies this distribution.
The full text of the license may be found at http://opensource.org/licenses/bsd-license.php The full text of the license may be found at http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES
@ -72,6 +72,10 @@
<IncludeHeader>Include/Library/EdkGenericPlatformBdsLib.h</IncludeHeader> <IncludeHeader>Include/Library/EdkGenericPlatformBdsLib.h</IncludeHeader>
<HelpText>Generic Platform Bds library</HelpText> <HelpText>Generic Platform Bds library</HelpText>
</LibraryClass> </LibraryClass>
<LibraryClass Name="PciIncompatibleDeviceSupportLib">
<IncludeHeader>Include/Library/PciIncompatibleDeviceSupportLib.h</IncludeHeader>
<HelpText>This library includes the PCI incompatible devices list.</HelpText>
</LibraryClass>
</LibraryClassDeclarations> </LibraryClassDeclarations>
<IndustryStdIncludes> <IndustryStdIncludes>
<IndustryStdHeader Name="CapsuleName"> <IndustryStdHeader Name="CapsuleName">
@ -404,6 +408,7 @@
<Filename>Library/EdkOemHookStatusCodeLibNull/EdkOemHookStatusCodeLibNull.msa</Filename> <Filename>Library/EdkOemHookStatusCodeLibNull/EdkOemHookStatusCodeLibNull.msa</Filename>
<Filename>Library/EdkGenericBdsLib/EdkGenericBdsLib.msa</Filename> <Filename>Library/EdkGenericBdsLib/EdkGenericBdsLib.msa</Filename>
<Filename>Library/EdkGenericPlatformBdsLib/EdkGenericPlatformBdsLib.msa</Filename> <Filename>Library/EdkGenericPlatformBdsLib/EdkGenericPlatformBdsLib.msa</Filename>
<Filename>Library/EdkPciIncompatibleDeviceSupportLib/EdkPciIncompatibleDeviceSupportLib.msa</Filename>
<Filename>Universal/Console/ConSplitter/Dxe/ConSplitter.msa</Filename> <Filename>Universal/Console/ConSplitter/Dxe/ConSplitter.msa</Filename>
<Filename>Universal/Console/GraphicsConsole/Dxe/GraphicsConsole.msa</Filename> <Filename>Universal/Console/GraphicsConsole/Dxe/GraphicsConsole.msa</Filename>
<Filename>Universal/Console/Terminal/Dxe/Terminal.msa</Filename> <Filename>Universal/Console/Terminal/Dxe/Terminal.msa</Filename>
@ -919,7 +924,7 @@
<DatumType>UINT32</DatumType> <DatumType>UINT32</DatumType>
<ValidUsage>FIXED_AT_BUILD</ValidUsage> <ValidUsage>FIXED_AT_BUILD</ValidUsage>
<DefaultValue>0x08</DefaultValue> <DefaultValue>0x08</DefaultValue>
<HelpText>The maximum number of callback function, which will be triggered when <HelpText>The maximum number of callback function, which will be triggered when
a PCD entry is been set, can be registered for a single PCD entry in PEI phase.</HelpText> a PCD entry is been set, can be registered for a single PCD entry in PEI phase.</HelpText>
</PcdEntry> </PcdEntry>
<PcdEntry> <PcdEntry>
@ -929,7 +934,7 @@
<DatumType>UINT32</DatumType> <DatumType>UINT32</DatumType>
<ValidUsage>FIXED_AT_BUILD</ValidUsage> <ValidUsage>FIXED_AT_BUILD</ValidUsage>
<DefaultValue>0x0</DefaultValue> <DefaultValue>0x0</DefaultValue>
<HelpText>The base address of the VPD (Vital Product Data) region. It is <HelpText>The base address of the VPD (Vital Product Data) region. It is
normally a region reserved on flash.</HelpText> normally a region reserved on flash.</HelpText>
</PcdEntry> </PcdEntry>
<PcdEntry> <PcdEntry>
@ -966,7 +971,7 @@
<DatumType>BOOLEAN</DatumType> <DatumType>BOOLEAN</DatumType>
<ValidUsage>FEATURE_FLAG</ValidUsage> <ValidUsage>FEATURE_FLAG</ValidUsage>
<DefaultValue>TRUE</DefaultValue> <DefaultValue>TRUE</DefaultValue>
<HelpText>This feature flag can be used to enable or disable the Pcd PEIM database <HelpText>This feature flag can be used to enable or disable the Pcd PEIM database
traverse capability. Disable it can reduce the size of final image generated.</HelpText> traverse capability. Disable it can reduce the size of final image generated.</HelpText>
</PcdEntry> </PcdEntry>
<PcdEntry> <PcdEntry>
@ -976,7 +981,7 @@
<DatumType>BOOLEAN</DatumType> <DatumType>BOOLEAN</DatumType>
<ValidUsage>FEATURE_FLAG</ValidUsage> <ValidUsage>FEATURE_FLAG</ValidUsage>
<DefaultValue>TRUE</DefaultValue> <DefaultValue>TRUE</DefaultValue>
<HelpText>This feature flag can be used to enable or disable the Pcd DXE database <HelpText>This feature flag can be used to enable or disable the Pcd DXE database
traverse capability. Disable it can reduce the size of final image generated.</HelpText> traverse capability. Disable it can reduce the size of final image generated.</HelpText>
</PcdEntry> </PcdEntry>
<PcdEntry> <PcdEntry>
@ -1294,5 +1299,20 @@
<DefaultValue>FALSE</DefaultValue> <DefaultValue>FALSE</DefaultValue>
<HelpText>If this PCD is set as TRUE, NT emulator will be endabled.</HelpText> <HelpText>If this PCD is set as TRUE, NT emulator will be endabled.</HelpText>
</PcdEntry> </PcdEntry>
<PcdEntry>
<C_Name>PcdPciIncompatibleDeviceSupportMask</C_Name>
<Token>0x0001003f</Token>
<TokenSpaceGuidCName>gEfiEdkModulePkgTokenSpaceGuid</TokenSpaceGuidCName>
<DatumType>UINT8</DatumType>
<ValidUsage>FIXED_AT_BUILD</ValidUsage>
<DefaultValue>0x0</DefaultValue>
<HelpText>The PCD masks for PCI incompatible devices support.
Acpi_Resource_Update_Support :1;
Register_Read_Support :1;
Register_Write_Support :1;
Register_Update_Support :1;
Register_Access_Width_Support :1;
Reserved :3;</HelpText>
</PcdEntry>
</PcdDeclarations> </PcdDeclarations>
</PackageSurfaceArea> </PackageSurfaceArea>

134
EdkModulePkg/Include/Library/PciIncompatibleDeviceSupportLib.h Normal file
View File

@ -0,0 +1,134 @@
/** @file
PCI Incompatible device support Libary.
Copyright (c) 2007 Intel Corporation. All rights reserved. <BR>
This software and associated documentation (if any) is furnished
under a license and may only be used or copied in accordance
with the terms of the license. Except as permitted by such
license, no part of this software or documentation may be
reproduced, stored in a retrieval system, or transmitted in any
form or by any means without the express written consent of
Intel Corporation.
**/
#define PCI_REGISTER_READ 0xfffffffffffffff1ULL
#define PCI_REGISTER_WRITE 0xfffffffffffffff2ULL
#define VALUE_NOCARE 0xffffffffffffffffULL
//
// PCI device device information
//
typedef struct {
UINT64 VendorID;
UINT64 DeviceID;
UINT64 RevisionID;
UINT64 SubsystemVendorID;
UINT64 SubsystemID;
} EFI_PCI_DEVICE_INFO;
//
// store hardcode value of resgister
//
typedef struct {
UINT64 AndValue;
UINT64 OrValue;
} EFI_PCI_REGISTER_VALUE_DATA;
//
// store access width information
//
typedef struct {
UINT64 StartOffset;
UINT64 EndOffset;
UINT64 Width;
} EFI_PCI_REGISTER_ACCESS_DATA;
//
// ACPI resource descriptor
//
typedef struct {
UINT64 ResType;
UINT64 GenFlag;
UINT64 SpecificFlag;
UINT64 AddrSpaceGranularity;
UINT64 AddrRangeMin;
UINT64 AddrRangeMax;
UINT64 AddrTranslationOffset;
UINT64 AddrLen;
} EFI_PCI_RESOUCE_DESCRIPTOR;
/**
Checks the incompatible device list for ACPI resource update and return
the configuration.
This function searches the incompatible device list according to request
information. If the PCI device belongs to the devices list, corresponding
configuration informtion will be returned, in the meantime return EFI_SUCCESS.
@param PciDeviceInfo A pointer to PCI device information.
@param Configuration Returned information.
@retval returns EFI_SUCCESS if check incompatible device ok.
Otherwise return EFI_UNSUPPORTED.
**/
RETURN_STATUS
EFIAPI
PciResourceUpdateCheck (
IN EFI_PCI_DEVICE_INFO *PciDeviceInfo,
OUT VOID *Configuration
);
/**
Checks the incompatible device list and return configuration register mask values.
This function searches the incompatible device list according to request
information. If the PCI device belongs to the devices list, corresponding
configuration informtion will be returned, in the meantime return EFI_SUCCESS.
@param PciDeviceInfo A pointer to EFI_PCI_DEVICE_INFO.
@param AccessType Access Type, READ or WRITE.
@param Offset The address within the PCI configuration space.
@param Configuration Returned information.
@retval returns EFI_SUCCESS if check incompatible device ok.
Otherwise return EFI_UNSUPPORTED.
**/
RETURN_STATUS
EFIAPI
PciRegisterUpdateCheck (
IN EFI_PCI_DEVICE_INFO *PciDeviceInfo,
IN UINT64 AccessType,
IN UINT64 Offset,
OUT VOID *Configuration
);
/**
Checks the incompatible device list for access width incompatibility and
return the configuration
This function searches the incompatible device list for access width
incompatibility according to request information. If the PCI device
belongs to the devices list, corresponding configuration informtion
will be returned, in the meantime return EFI_SUCCESS.
@param PciDeviceInfo A pointer to PCI device information.
@param AccessType Access type, READ or WRITE.
@param Offset The address within the PCI configuration space.
@param AccessWidth Access width needs to check incompatibility.
@param Configuration Returned information.
@retval returns EFI_SUCCESS if check incompatible device ok.
Otherwise return EFI_UNSUPPORTED.
**/
RETURN_STATUS
EFIAPI
PciRegisterAccessCheck (
IN EFI_PCI_DEVICE_INFO *PciDeviceInfo,
IN UINT64 AccessType,
IN UINT64 Offset,
IN UINT64 AccessWidth,
OUT VOID *Configuration
);

388
EdkModulePkg/Library/EdkPciIncompatibleDeviceSupportLib/EdkPciIncompatibleDeviceSupportLib.c Normal file
View File

@ -0,0 +1,388 @@
/** @file
The implementation of PCI incompatible device support libary.
Copyright (c) 2007 Intel Corporation. All rights reserved. <BR>
This software and associated documentation (if any) is furnished
under a license and may only be used or copied in accordance
with the terms of the license. Except as permitted by such
license, no part of this software or documentation may be
reproduced, stored in a retrieval system, or transmitted in any
form or by any means without the express written consent of
Intel Corporation.
**/
#include "IncompatiblePciDeviceList.h"
/**
Check whether two PCI devices matched
@param PciDeviceInfo A pointer to EFI_PCI_DEVICE_INFO.
@param Header A pointer to EFI_PCI_DEVICE_INFO.
@retval returns EFI_SUCCESS if two PCI device matched.
**/
STATIC
EFI_STATUS
DeviceCheck (
IN EFI_PCI_DEVICE_INFO *PciDeviceInfo,
IN EFI_PCI_DEVICE_INFO *Header
)
{
//
// See if the Header matches the parameters passed in
//
if (Header->VendorID != DEVICE_ID_NOCARE) {
if (PciDeviceInfo->VendorID != Header->VendorID) {
return EFI_UNSUPPORTED;
}
}
if (Header->DeviceID != DEVICE_ID_NOCARE) {
if (PciDeviceInfo->DeviceID != Header->DeviceID) {
return EFI_UNSUPPORTED;
}
}
if (Header->RevisionID != DEVICE_ID_NOCARE) {
if (PciDeviceInfo->RevisionID != Header->RevisionID) {
return EFI_UNSUPPORTED;
}
}
if (Header->SubsystemVendorID != DEVICE_ID_NOCARE) {
if (PciDeviceInfo->SubsystemVendorID != Header->SubsystemVendorID) {
return EFI_UNSUPPORTED;
}
}
if (Header->SubsystemID != DEVICE_ID_NOCARE) {
if (PciDeviceInfo->SubsystemID != Header->SubsystemID) {
return EFI_UNSUPPORTED;
}
}
return EFI_SUCCESS;
}
/**
Check the incompatible device list for ACPI resource update and return
the configuration
This function searches the incompatible device list according to request
information. If the PCI device belongs to the devices list, corresponding
configuration informtion will be returned, in the meantime return EFI_SUCCESS.
@param PciDeviceInfo A pointer to PCI device information.
@param Configuration Returned information.
@retval returns EFI_SUCCESS if check incompatible device ok.
Otherwise return EFI_UNSUPPORTED.
**/
RETURN_STATUS
EFIAPI
PciResourceUpdateCheck (
IN EFI_PCI_DEVICE_INFO *PciDeviceInfo,
OUT VOID *Configuration
)
{
UINT64 Tag;
UINT64 *ListPtr;
UINT64 *TempListPtr;
EFI_PCI_DEVICE_INFO *Header;
EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *AcpiPtr;
EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *OldAcpiPtr;
EFI_PCI_RESOUCE_DESCRIPTOR *Dsc;
EFI_ACPI_END_TAG_DESCRIPTOR *PtrEnd;
UINTN Index;
ASSERT (PciDeviceInfo != NULL);
//
// Initialize the return value to NULL
//
* (VOID **) Configuration = NULL;
ListPtr = IncompatiblePciDeviceListForResource;
while (*ListPtr != LIST_END_TAG) {
Tag = *ListPtr;
switch (Tag) {
case DEVICE_INF_TAG:
Header = (EFI_PCI_DEVICE_INFO *) (ListPtr + 1);
ListPtr = ListPtr + 1 + sizeof (EFI_PCI_DEVICE_INFO) / sizeof (UINT64);
if (DeviceCheck (PciDeviceInfo, Header) != EFI_SUCCESS) {
continue;
}
//
// Matched an item, so construct the ACPI descriptor for the resource.
//
//
// Count the resource items so that to allocate space
//
for (Index = 0, TempListPtr = ListPtr; *TempListPtr == DEVICE_RES_TAG; Index++) {
TempListPtr = TempListPtr + 1 + ((sizeof (EFI_PCI_RESOUCE_DESCRIPTOR)) / sizeof (UINT64));
}
//
// If there is at least one type of resource request,
// allocate a acpi resource node
//
if (Index == 0) {
return EFI_ABORTED;
}
AcpiPtr = AllocateZeroPool (
sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * Index + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)
);
OldAcpiPtr = AcpiPtr;
//
// Fill the EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR structure
// according to the EFI_PCI_RESOUCE_DESCRIPTOR structure
//
for (; *ListPtr == DEVICE_RES_TAG;) {
Dsc = (EFI_PCI_RESOUCE_DESCRIPTOR *) (ListPtr + 1);
AcpiPtr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
AcpiPtr->Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);
AcpiPtr->ResType = (UINT8) Dsc->ResType;
AcpiPtr->GenFlag = (UINT8) Dsc->GenFlag;
AcpiPtr->SpecificFlag = (UINT8) Dsc->SpecificFlag;
AcpiPtr->AddrSpaceGranularity = Dsc->AddrSpaceGranularity;;
AcpiPtr->AddrRangeMin = Dsc->AddrRangeMin;
AcpiPtr->AddrRangeMax = Dsc->AddrRangeMax;
AcpiPtr->AddrTranslationOffset = Dsc->AddrTranslationOffset;
AcpiPtr->AddrLen = Dsc->AddrLen;
ListPtr = ListPtr + 1 + ((sizeof (EFI_PCI_RESOUCE_DESCRIPTOR)) / sizeof (UINT64));
AcpiPtr++;
}
//
// put the checksum
//
PtrEnd = (EFI_ACPI_END_TAG_DESCRIPTOR *) (AcpiPtr);
PtrEnd->Desc = ACPI_END_TAG_DESCRIPTOR;
PtrEnd->Checksum = 0;
*(VOID **) Configuration = OldAcpiPtr;
return EFI_SUCCESS;
case DEVICE_RES_TAG:
//
// Adjust the pointer to the next PCI resource descriptor item
//
ListPtr = ListPtr + 1 + ((sizeof (EFI_PCI_RESOUCE_DESCRIPTOR)) / sizeof (UINT64));
break;
default:
return EFI_UNSUPPORTED;
}
}
return EFI_UNSUPPORTED;
}
/**
Check the incompatible device list and return configuraton register mask values.
This function searches the incompatible device list according to request
information. If the PCI device belongs to the devices list, corresponding
configuration informtion will be returned, in the meantime return EFI_SUCCESS.
@param PciDeviceInfo A pointer to EFI_PCI_DEVICE_INFO.
@param AccessType Access Type, READ or WRITE.
@param Offset The address within the PCI configuration space.
@param Configuration Returned information.
@retval returns EFI_SUCCESS if check incompatible device ok.
Otherwise return EFI_UNSUPPORTED.
**/
RETURN_STATUS
EFIAPI
PciRegisterUpdateCheck (
IN EFI_PCI_DEVICE_INFO *PciDeviceInfo,
IN UINT64 AccessType,
IN UINT64 Offset,
OUT VOID *Configuration
)
{
EFI_PCI_DEVICE_INFO *Header;
UINT64 Tag;
UINT64 *ListPtr;
EFI_PCI_REGISTER_VALUE_DATA *RegisterPtr;
EFI_PCI_REGISTER_VALUE_DATA *Dsc;
ASSERT (PciDeviceInfo != NULL);
ListPtr = IncompatiblePciDeviceListForRegister;
//
// Initialize the return value to NULL
//
* (VOID **) Configuration = NULL;
while (*ListPtr != LIST_END_TAG) {
Tag = *ListPtr;
switch (Tag) {
case DEVICE_INF_TAG:
Header = (EFI_PCI_DEVICE_INFO *) (ListPtr + 1);
ListPtr = ListPtr + 1 + sizeof (EFI_PCI_DEVICE_INFO) / sizeof (UINT64);
//
// Check whether the PCI device matches the device in the incompatible devices list?
// If not, ship next
//
if (DeviceCheck (PciDeviceInfo, Header) != EFI_SUCCESS) {
continue;
}
//
// Matched an item, check whether access matches?
//
for (; *ListPtr == DEVICE_RES_TAG;) {
ListPtr ++;
if (((EFI_PCI_REGISTER_VALUE_DESCRIPTOR *)ListPtr)->Offset == (Offset & 0xfc)) {
if (((EFI_PCI_REGISTER_VALUE_DESCRIPTOR *)ListPtr)->AccessType == AccessType) {
Dsc = (EFI_PCI_REGISTER_VALUE_DATA *) (ListPtr + 2);
RegisterPtr = AllocateZeroPool (sizeof (EFI_PCI_REGISTER_VALUE_DATA));
RegisterPtr->AndValue = Dsc->AndValue;
RegisterPtr->OrValue = Dsc->OrValue;
*(VOID **) Configuration = RegisterPtr;
return EFI_SUCCESS;
}
}
ListPtr += sizeof (EFI_PCI_REGISTER_VALUE_DESCRIPTOR) / (sizeof (UINT64));
}
return EFI_UNSUPPORTED;
case DEVICE_RES_TAG:
//
// Adjust the pointer to the next item
//
ListPtr = ListPtr + 1 + ((sizeof (EFI_PCI_REGISTER_VALUE_DESCRIPTOR)) / sizeof (UINT64));
break;
default:
return EFI_UNSUPPORTED;
}
}
return EFI_UNSUPPORTED;
}
/**
Check the incompatible device list for access width incompatibility and
return the configuration
This function searches the incompatible device list for access width
incompatibility according to request information. If the PCI device
belongs to the devices list, corresponding configuration informtion
will be returned, in the meantime return EFI_SUCCESS.
@param PciDeviceInfo A pointer to PCI device information.
@param AccessType Access type, READ or WRITE.
@param Offset The address within the PCI configuration space.
@param AccessWidth Access width needs to check incompatibility.
@param Configuration Returned information.
@retval returns EFI_SUCCESS if check incompatible device ok.
Otherwise return EFI_UNSUPPORTED.
**/
RETURN_STATUS
EFIAPI
PciRegisterAccessCheck (
IN EFI_PCI_DEVICE_INFO *PciDeviceInfo,
IN UINT64 AccessType,
IN UINT64 Offset,
IN UINT64 AccessWidth,
OUT VOID *Configuration
)
{
EFI_PCI_DEVICE_INFO *Header;
UINT64 Tag;
UINT64 *ListPtr;
EFI_PCI_REGISTER_ACCESS_DATA *RegisterPtr;
EFI_PCI_REGISTER_ACCESS_DATA *Dsc;
ASSERT (PciDeviceInfo != NULL);
ListPtr = DeviceListForAccessWidth;
//
// Initialize the return value to NULL
//
* (VOID **) Configuration = NULL;
while (*ListPtr != LIST_END_TAG) {
Tag = *ListPtr;
switch (Tag) {
case DEVICE_INF_TAG:
Header = (EFI_PCI_DEVICE_INFO *) (ListPtr + 1);
ListPtr = ListPtr + 1 + sizeof (EFI_PCI_DEVICE_INFO) / sizeof (UINT64);
//
// Check whether the PCI device matches the device in the incompatible devices list?
// If not, ship next
//
if (DeviceCheck (PciDeviceInfo, Header) != EFI_SUCCESS) {
continue;
}
//
// Matched an item, check whether access matches?
//
for (; *ListPtr == DEVICE_RES_TAG;) {
ListPtr ++;
if (((EFI_PCI_REGISTER_ACCESS_DESCRIPTOR *) ListPtr)->AccessType == AccessType &&
((EFI_PCI_REGISTER_ACCESS_DESCRIPTOR *) ListPtr)->AccessWidth == AccessWidth ) {
Dsc = (EFI_PCI_REGISTER_ACCESS_DATA *) (ListPtr + 2);
if((Dsc->StartOffset <= Offset) && (Dsc->EndOffset > Offset)) {
RegisterPtr = AllocateZeroPool (sizeof (EFI_PCI_REGISTER_ACCESS_DATA));
RegisterPtr->StartOffset = Dsc->StartOffset;
RegisterPtr->EndOffset = Dsc->EndOffset;
RegisterPtr->Width = Dsc->Width;
*(VOID **) Configuration = RegisterPtr;
return EFI_SUCCESS;
}
}
ListPtr += sizeof (EFI_PCI_REGISTER_ACCESS_DESCRIPTOR) / (sizeof (UINT64));
}
return EFI_UNSUPPORTED;
case DEVICE_RES_TAG:
//
// Adjust the pointer to the next item
//
ListPtr = ListPtr + 1 + ((sizeof (EFI_PCI_REGISTER_ACCESS_DESCRIPTOR)) / sizeof (UINT64));
break;
default:
return EFI_UNSUPPORTED;
}
}
return EFI_UNSUPPORTED;
}

44
EdkModulePkg/Library/EdkPciIncompatibleDeviceSupportLib/EdkPciIncompatibleDeviceSupportLib.msa Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<ModuleSurfaceArea xmlns="http://www.TianoCore.org/2006/Edk2.0" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<MsaHeader>
<ModuleName>EdkPciIncompatibleDeviceSuppportLib</ModuleName>
<ModuleType>DXE_DRIVER</ModuleType>
<GuidValue>1ca1c1f9-5baf-4204-b6e5-5e24109a4e4e</GuidValue>
<Version>1.0</Version>
<Abstract>PCI Incompatible device support Library</Abstract>
<Description>Check PCI incompatible devices and set necessary configuration</Description>
<Copyright>Copyright (c) 2007, Intel Corporation.</Copyright>
<License>All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.</License>
<Specification>FRAMEWORK_BUILD_PACKAGING_SPECIFICATION 0x00000052</Specification>
</MsaHeader>
<ModuleDefinitions>
<SupportedArchitectures>IA32 X64 IPF EBC</SupportedArchitectures>
<BinaryModule>false</BinaryModule>
<OutputFileBasename>EdkPciIncompatibleDeviceSupportLib</OutputFileBasename>
</ModuleDefinitions>
<LibraryClassDefinitions>
<LibraryClass Usage="ALWAYS_PRODUCED">
<Keyword>PciIncompatibleDeviceSupportLib</Keyword>
</LibraryClass>
<LibraryClass Usage="ALWAYS_CONSUMED">
<Keyword>MemoryAllocationLib</Keyword>
</LibraryClass>
</LibraryClassDefinitions>
<SourceFiles>
<Filename>EdkPciIncompatibleDeviceSupportLib.c</Filename>
<Filename>IncompatiblePciDeviceList.h</Filename>
</SourceFiles>
<PackageDependencies>
<Package PackageGuid="5e0e9358-46b6-4ae2-8218-4ab8b9bbdcec"/>
<Package PackageGuid="68169ab0-d41b-4009-9060-292c253ac43d"/>
</PackageDependencies>
<Externs>
<Specification>EFI_SPECIFICATION_VERSION 0x00020000</Specification>
<Specification>EDK_RELEASE_VERSION 0x00020000</Specification>
</Externs>
</ModuleSurfaceArea>

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EdkModulePkg/Library/EdkPciIncompatibleDeviceSupportLib/IncompatiblePciDeviceList.h Normal file
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/** @file
The incompatible PCI device list
Copyright (c) 2007 Intel Corporation. All rights reserved. <BR>
This software and associated documentation (if any) is furnished
under a license and may only be used or copied in accordance
with the terms of the license. Except as permitted by such
license, no part of this software or documentation may be
reproduced, stored in a retrieval system, or transmitted in any
form or by any means without the express written consent of
Intel Corporation.
**/
#ifndef _EFI_INCOMPATIBLE_PCI_DEVICE_LIST_H
#define _EFI_INCOMPATIBLE_PCI_DEVICE_LIST_H
#include <IndustryStandard/pci22.h>
#include <IndustryStandard/Acpi.h>
#define PCI_DEVICE_ID(VendorId, DeviceId, Revision, SubVendorId, SubDeviceId) \
VendorId, DeviceId, Revision, SubVendorId, SubDeviceId
#define PCI_BAR_TYPE_IO ACPI_ADDRESS_SPACE_TYPE_IO
#define PCI_BAR_TYPE_MEM ACPI_ADDRESS_SPACE_TYPE_MEM
#define DEVICE_INF_TAG 0xFFF2
#define DEVICE_RES_TAG 0xFFF1
#define LIST_END_TAG 0x0000
//
// descriptor for access width of incompatible PCI device
//
typedef struct {
UINT64 AccessType;
UINT64 AccessWidth;
EFI_PCI_REGISTER_ACCESS_DATA PciRegisterAccessData;
} EFI_PCI_REGISTER_ACCESS_DESCRIPTOR;
//
// descriptor for register value of incompatible PCI device
//
typedef struct {
UINT64 AccessType;
UINT64 Offset;
EFI_PCI_REGISTER_VALUE_DATA PciRegisterValueData;
} EFI_PCI_REGISTER_VALUE_DESCRIPTOR;
//
// the incompatible PCI devices list for ACPI resource
//
GLOBAL_REMOVE_IF_UNREFERENCED UINT64 IncompatiblePciDeviceListForResource[] = {
//
// DEVICE_INF_TAG,
// PCI_DEVICE_ID (VendorID, DeviceID, Revision, SubVendorId, SubDeviceId),
// DEVICE_RES_TAG,
// ResType, GFlag , SFlag, Granularity, RangeMin,
// RangeMax, Offset, AddrLen
//
//
// Device Adaptec 9004
//
DEVICE_INF_TAG,
PCI_DEVICE_ID(0x9004, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),
DEVICE_RES_TAG,
PCI_BAR_TYPE_IO,
PCI_ACPI_UNUSED,
PCI_ACPI_UNUSED,
PCI_ACPI_UNUSED,
PCI_ACPI_UNUSED,
PCI_BAR_EVEN_ALIGN,
PCI_BAR_ALL,
PCI_BAR_NOCHANGE,
//
// Device Adaptec 9005
//
DEVICE_INF_TAG,
PCI_DEVICE_ID(0x9005, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),
DEVICE_RES_TAG,
PCI_BAR_TYPE_IO,
PCI_ACPI_UNUSED,
PCI_ACPI_UNUSED,
PCI_ACPI_UNUSED,
PCI_ACPI_UNUSED,
PCI_BAR_EVEN_ALIGN,
PCI_BAR_ALL,
PCI_BAR_NOCHANGE,
//
// Device QLogic 1007
//
DEVICE_INF_TAG,
PCI_DEVICE_ID(0x1077, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),
DEVICE_RES_TAG,
PCI_BAR_TYPE_IO,
PCI_ACPI_UNUSED,
PCI_ACPI_UNUSED,
PCI_ACPI_UNUSED,
PCI_ACPI_UNUSED,
PCI_BAR_EVEN_ALIGN,
PCI_BAR_ALL,
PCI_BAR_NOCHANGE,
//
// Device Agilent 103C
//
DEVICE_INF_TAG,
PCI_DEVICE_ID(0x103C, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),
DEVICE_RES_TAG,
PCI_BAR_TYPE_IO,
PCI_ACPI_UNUSED,
PCI_ACPI_UNUSED,
PCI_ACPI_UNUSED,
PCI_ACPI_UNUSED,
PCI_BAR_EVEN_ALIGN,
PCI_BAR_ALL,
PCI_BAR_NOCHANGE,
//
// Device Agilent 15BC
//
DEVICE_INF_TAG,
PCI_DEVICE_ID(0x15BC, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),
DEVICE_RES_TAG,
PCI_BAR_TYPE_IO,
PCI_ACPI_UNUSED,
PCI_ACPI_UNUSED,
PCI_ACPI_UNUSED,
PCI_ACPI_UNUSED,
PCI_BAR_EVEN_ALIGN,
PCI_BAR_ALL,
PCI_BAR_NOCHANGE,
//
// The end of the list
//
LIST_END_TAG
};
//
// the incompatible PCI devices list for the values of configuration registers
//
GLOBAL_REMOVE_IF_UNREFERENCED UINT64 IncompatiblePciDeviceListForRegister[] = {
//
// DEVICE_INF_TAG,
// PCI_DEVICE_ID (VendorID, DeviceID, Revision, SubVendorId, SubDeviceId),
// PCI_RES_TAG,
// PCI_ACCESS_TYPE, PCI_CONFIG_ADDRESS,
// AND_VALUE, OR_VALUE
//
// Device Lava 0x1407, DeviceId 0x0110
//
DEVICE_INF_TAG,
PCI_DEVICE_ID(0x1407, 0x0110, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),
DEVICE_RES_TAG,
PCI_REGISTER_READ,
PCI_CAPBILITY_POINTER_OFFSET,
0xffffff00,
VALUE_NOCARE,
//
// Device Lava 0x1407, DeviceId 0x0111
//
DEVICE_INF_TAG,
PCI_DEVICE_ID(0x1407, 0x0111, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),
DEVICE_RES_TAG,
PCI_REGISTER_READ,
PCI_CAPBILITY_POINTER_OFFSET,
0xffffff00,
VALUE_NOCARE,
//
// The end of the list
//
LIST_END_TAG
};
//
// the incompatible PCI devices list for the access width of configuration registers
//
GLOBAL_REMOVE_IF_UNREFERENCED UINT64 DeviceListForAccessWidth[] = {
//
// DEVICE_INF_TAG,
// PCI_DEVICE_ID (VendorID, DeviceID, Revision, SubVendorId, SubDeviceId),
// DEVICE_RES_TAG,
// PCI_ACCESS_TYPE, PCI_ACCESS_WIDTH,
// START_ADDRESS, END_ADDRESS,
// ACTUAL_PCI_ACCESS_WIDTH,
//
//
// Sample Device
//
//DEVICE_INF_TAG,
//PCI_DEVICE_ID(0xXXXX, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),
//DEVICE_RES_TAG,
//PCI_REGISTER_READ,
//EfiPciWidthUint8,
//0,
//0xFF,
//EfiPciWidthUint32,
//
//
// The end of the list
//
LIST_END_TAG
};
#endif