tyler.durden
/
audk
mirror of https://github.com/acidanthera/audk.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

1. Added EdkPciIncompatibleDeviceSupportLib in EdkModulePkg, this library is used for PciBus driver and includes 3 Incompatible device lists. 

2. Used EdkPciIncompatibleDeviceSupportLib in PciBus driver. 
3. Redirect all Pci Configuration access to new APIs added in PciLib.c for PciBus driver.
4. Added one PCD PcdIncompatibleDeviceSupportMask in EdkModulePkg.spd to provide mask of PCI devices incompatibility check.

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@2562 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
vanjeff 2007-04-12 09:07:01 +00:00
parent 0eaa1933bc
commit 98419ef4b9
18 changed files with 2226 additions and 412 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
EdkModulePkg/Bus/Pci/PciBus/Dxe/PciBus.msa
View File

@ -57,6 +57,9 @@
<LibraryClass Usage="ALWAYS_CONSUMED">
<Keyword>PcdLib</Keyword>
</LibraryClass>
<LibraryClass Usage="ALWAYS_CONSUMED">
<Keyword>PciIncompatibleDeviceSupportLib</Keyword>
</LibraryClass>
</LibraryClassDefinitions>
<SourceFiles>
<Filename>pcibus.h</Filename>
@ -174,5 +177,10 @@
<DefaultValue>TRUE</DefaultValue>
<HelpText>If TRUE, the PCI bus driver will support hot plug device. If not hot plug device is supported, this feature flag can be set to FALSE to save size.</HelpText>
</PcdEntry>
<PcdEntry PcdItemType="FIXED_AT_BUILD" Usage="ALWAYS_CONSUMED">
<C_Name>PcdPciIncompatibleDeviceSupportMask</C_Name>
<TokenSpaceGuidCName>gEfiEdkModulePkgTokenSpaceGuid</TokenSpaceGuidCName>
<HelpText>The PCD masks for PCI incompatible devices support</HelpText>
</PcdEntry>
</PcdCoded>
</ModuleSurfaceArea>

62
EdkModulePkg/Bus/Pci/PciBus/Dxe/PciCommand.c
View File

@ -1,6 +1,6 @@
/*++
Copyright (c) 2006, Intel Corporation
Copyright (c) 2006 - 2007, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -56,13 +56,13 @@ Returns:
PciIo = &PciIoDevice->PciIo;
if (Operation != EFI_SET_REGISTER) {
Status = PciIo->Pci.Read (
PciIo,
EfiPciIoWidthUint16,
Offset,
1,
&OldCommand
);
Status = PciIoRead (
PciIo,
EfiPciIoWidthUint16,
Offset,
1,
&OldCommand
);
if (Operation == EFI_GET_REGISTER) {
*PtrCommand = OldCommand;
@ -78,13 +78,13 @@ Returns:
OldCommand = Command;
}
return PciIo->Pci.Write (
return PciIoWrite (
PciIo,
EfiPciIoWidthUint16,
Offset,
1,
&OldCommand
);
);
}
BOOLEAN
@ -157,22 +157,22 @@ Returns:
CapabilityPtr = 0;
if (IS_CARDBUS_BRIDGE (&PciIoDevice->Pci)) {
PciIoDevice->PciIo.Pci.Read (
&PciIoDevice->PciIo,
EfiPciIoWidthUint8,
EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR,
1,
&CapabilityPtr
);
PciIoRead (
&PciIoDevice->PciIo,
EfiPciIoWidthUint8,
EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR,
1,
&CapabilityPtr
);
} else {
PciIoDevice->PciIo.Pci.Read (
&PciIoDevice->PciIo,
EfiPciIoWidthUint8,
EFI_PCI_CAPABILITY_PTR,
1,
&CapabilityPtr
);
PciIoRead (
&PciIoDevice->PciIo,
EfiPciIoWidthUint8,
EFI_PCI_CAPABILITY_PTR,
1,
&CapabilityPtr
);
}
}
@ -181,13 +181,13 @@ Returns:
// Mask it to DWORD alignment per PCI spec
//
CapabilityPtr &= 0xFC;
PciIoDevice->PciIo.Pci.Read (
&PciIoDevice->PciIo,
EfiPciIoWidthUint16,
CapabilityPtr,
1,
&CapabilityEntry
);
PciIoRead (
&PciIoDevice->PciIo,
EfiPciIoWidthUint16,
CapabilityPtr,
1,
&CapabilityEntry
);
CapabilityID = (UINT8) CapabilityEntry;

5
EdkModulePkg/Bus/Pci/PciBus/Dxe/PciDeviceSupport.c
View File

@ -1,6 +1,6 @@
/*++
Copyright (c) 2006, Intel Corporation
Copyright (c) 2006 - 2007, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -341,8 +341,7 @@ Returns:
//
PciIo = &(PciIoDevice->PciIo);
Data8 = PCI_INT_LINE_UNKNOWN;
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &Data8);
PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &Data8);
//
// Process Platform OpRom

16
EdkModulePkg/Bus/Pci/PciBus/Dxe/PciEnumerator.c
View File

@ -1,6 +1,6 @@
/*++
Copyright (c) 2006, Intel Corporation
Copyright (c) 2006 - 2007, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -382,8 +382,9 @@ Returns:
Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x18);
Status = PciRootBridgeIo->Pci.Write (
Status = PciRootBridgeIoWrite (
PciRootBridgeIo,
&Pci,
EfiPciWidthUint16,
Address,
1,
@ -394,8 +395,9 @@ Returns:
// Initialize SubBusNumber to SecondBus
//
Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A);
Status = PciRootBridgeIo->Pci.Write (
Status = PciRootBridgeIoWrite (
PciRootBridgeIo,
&Pci,
EfiPciWidthUint8,
Address,
1,
@ -407,8 +409,9 @@ Returns:
if (IS_PCI_BRIDGE (&Pci)) {
Register8 = 0xFF;
Status = PciRootBridgeIo->Pci.Write (
Status = PciRootBridgeIoWrite (
PciRootBridgeIo,
&Pci,
EfiPciWidthUint8,
Address,
1,
@ -432,8 +435,9 @@ Returns:
Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A);
Status = PciRootBridgeIo->Pci.Write (
Status = PciRootBridgeIoWrite (
PciRootBridgeIo,
&Pci,
EfiPciWidthUint8,
Address,
1,
@ -1471,7 +1475,7 @@ Returns:
SubBusNumber = 0;
StartBusNumber = 0;
PciIo = &(BridgeDev->PciIo);
Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x19, 1, &StartBusNumber);
Status = PciIoRead (PciIo, EfiPciIoWidthUint8, 0x19, 1, &StartBusNumber);
if (EFI_ERROR (Status)) {
return Status;

115
EdkModulePkg/Bus/Pci/PciBus/Dxe/PciEnumeratorSupport.c
View File

@ -66,8 +66,9 @@ Returns:
//
// Read the Vendor Id register
//
Status = PciRootBridgeIo->Pci.Read (
Status = PciRootBridgeIoRead (
PciRootBridgeIo,
NULL,
EfiPciWidthUint32,
Address,
1,
@ -80,8 +81,9 @@ Returns:
// Read the entire config header for the device
//
Status = PciRootBridgeIo->Pci.Read (
Status = PciRootBridgeIoRead (
PciRootBridgeIo,
NULL,
EfiPciWidthUint32,
Address,
sizeof (PCI_TYPE00) / sizeof (UINT32),
@ -172,7 +174,7 @@ Returns:
//
PciIo = &(PciIoDevice->PciIo);
Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x19, 1, &SecBus);
Status = PciIoRead (PciIo, EfiPciIoWidthUint8, 0x19, 1, &SecBus);
if (EFI_ERROR (Status)) {
return Status;
@ -301,7 +303,9 @@ Returns:
//
// Update the bar information for this PCI device so as to support some specific device
//
UpdatePciInfo (PciIoDevice);
if (PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_ACPI_RESOURCE_SUPPORT) {
UpdatePciInfo (PciIoDevice);
}
if (PciIoDevice->DevicePath == NULL) {
return EFI_OUT_OF_RESOURCES;
@ -486,10 +490,10 @@ Returns:
//
// Test whether it support 32 decode or not
//
PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Temp);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &gAllOne);
PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Value);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Temp);
PciIoRead (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Temp);
PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &gAllOne);
PciIoRead (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Value);
PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Temp);
if (Value) {
if (Value & 0x01) {
@ -684,20 +688,20 @@ Returns:
// Preserve the original value
//
PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &OriginalValue);
PciIoRead (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &OriginalValue);
//
// Raise TPL to high level to disable timer interrupt while the BAR is probed
//
OldTpl = gBS->RaiseTPL (EFI_TPL_HIGH_LEVEL);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &gAllOne);
PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &Value);
PciIoWrite (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &gAllOne);
PciIoRead (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &Value);
//
// Write back the original value
//
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &OriginalValue);
PciIoWrite (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &OriginalValue);
//
// Restore TPL to its original level
@ -953,7 +957,7 @@ Returns:
// Read the status register
//
PciIo = &PciIoDevice->PciIo;
Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, StatusIndex, 1, &StatusRegister);
Status = PciIoRead (PciIo, EfiPciIoWidthUint16, StatusIndex, 1, &StatusRegister);
if (EFI_ERROR (Status)) {
return EFI_UNSUPPORTED;
}
@ -1102,7 +1106,7 @@ Returns:
PciIo = &PciIoDevice->PciIo;
PciIo->Pci.Read (
PciIoRead (
PciIo,
EfiPciIoWidthUint8,
0x09,
@ -1115,7 +1119,7 @@ Returns:
//
IdePI |= (((IdePI & 0x0F) >> 1) & 0x05);
PciIo->Pci.Write (
PciIoWrite (
PciIo,
EfiPciIoWidthUint8,
0x09,
@ -1216,40 +1220,23 @@ Returns:
UINTN BarIndex;
UINTN BarEndIndex;
BOOLEAN SetFlag;
EFI_PCI_DEVICE_INFO PciDeviceInfo;
VOID *Configuration;
EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;
Configuration = NULL;
//
// It can only be supported after the Incompatible PCI Device
// Support Protocol has been installed
//
if (gEfiIncompatiblePciDeviceSupport == NULL) {
Status = gBS->LocateProtocol (
&gEfiIncompatiblePciDeviceSupportProtocolGuid,
NULL,
(VOID **) &gEfiIncompatiblePciDeviceSupport
);
if (EFI_ERROR (Status)) {
return EFI_UNSUPPORTED;
}
}
//
// Check whether the device belongs to incompatible devices or not
// If it is , then get its special requirement in the ACPI table
//
Status = gEfiIncompatiblePciDeviceSupport->CheckDevice (
gEfiIncompatiblePciDeviceSupport,
PciIoDevice->Pci.Hdr.VendorId,
PciIoDevice->Pci.Hdr.DeviceId,
PciIoDevice->Pci.Hdr.RevisionID,
PciIoDevice->Pci.Device.SubsystemVendorID,
PciIoDevice->Pci.Device.SubsystemID,
&Configuration
);
PciDeviceInfo.VendorID = PciIoDevice->Pci.Hdr.VendorId;
PciDeviceInfo.DeviceID = PciIoDevice->Pci.Hdr.DeviceId;
PciDeviceInfo.RevisionID = PciIoDevice->Pci.Hdr.RevisionID;
PciDeviceInfo.SubsystemVendorID = PciIoDevice->Pci.Device.SubsystemVendorID;
PciDeviceInfo.SubsystemID = PciIoDevice->Pci.Device.SubsystemID;
Status = PciResourceUpdateCheck (&PciDeviceInfo, &Configuration);
if (EFI_ERROR (Status)) {
return Status;
@ -1635,7 +1622,7 @@ Returns:
// has not been alloacted
//
for (Offset = 0x10; Offset <= 0x24; Offset += sizeof (UINT32)) {
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, Offset, 1, &gAllOne);
PciIoWrite (PciIo, EfiPciIoWidthUint32, Offset, 1, &gAllOne);
}
return EFI_SUCCESS;
@ -1668,28 +1655,28 @@ Returns:
// Io32, pMem32, pMem64 to quiescent state
// Resource base all ones, Resource limit all zeros
//
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &gAllOne);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1D, 1, &gAllZero);
PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &gAllOne);
PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x1D, 1, &gAllZero);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x20, 1, &gAllOne);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x22, 1, &gAllZero);
PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x20, 1, &gAllOne);
PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x22, 1, &gAllZero);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x24, 1, &gAllOne);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x26, 1, &gAllZero);
PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x24, 1, &gAllOne);
PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x26, 1, &gAllZero);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x28, 1, &gAllOne);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x2C, 1, &gAllZero);
PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x28, 1, &gAllOne);
PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x2C, 1, &gAllZero);
//
// don't support use io32 as for now
//
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x30, 1, &gAllOne);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x32, 1, &gAllZero);
PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x30, 1, &gAllOne);
PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x32, 1, &gAllZero);
//
// Force Interrupt line to zero for cards that come up randomly
//
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &gAllZero);
PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &gAllZero);
return EFI_SUCCESS;
}
@ -1721,22 +1708,22 @@ Returns:
// Io32, pMem32, pMem64 to quiescent state(
// Resource base all ones, Resource limit all zeros
//
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x1c, 1, &gAllOne);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x20, 1, &gAllZero);
PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x1c, 1, &gAllOne);
PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x20, 1, &gAllZero);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x24, 1, &gAllOne);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x28, 1, &gAllZero);
PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x24, 1, &gAllOne);
PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x28, 1, &gAllZero);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x2c, 1, &gAllOne);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x30, 1, &gAllZero);
PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x2c, 1, &gAllOne);
PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x30, 1, &gAllZero);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x34, 1, &gAllOne);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x38, 1, &gAllZero);
PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x34, 1, &gAllOne);
PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x38, 1, &gAllZero);
//
// Force Interrupt line to zero for cards that come up randomly
//
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &gAllZero);
PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &gAllZero);
return EFI_SUCCESS;
}
@ -2231,8 +2218,9 @@ Returns:
if (!EFI_ERROR (Status) && (IS_PCI_BRIDGE (&Pci))) {
Register = 0;
Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x18);
Status = PciRootBridgeIo->Pci.Read (
Status = PciRootBridgeIoRead (
PciRootBridgeIo,
&Pci,
EfiPciWidthUint32,
Address,
1,
@ -2242,8 +2230,9 @@ Returns:
// Reset register 18h, 19h, 1Ah on PCI Bridge
//
Register &= 0xFF000000;
Status = PciRootBridgeIo->Pci.Write (
Status = PciRootBridgeIoWrite (
PciRootBridgeIo,
&Pci,
EfiPciWidthUint32,
Address,
1,

911
EdkModulePkg/Bus/Pci/PciBus/Dxe/PciLib.c
View File

File diff suppressed because it is too large Load Diff

110
EdkModulePkg/Bus/Pci/PciBus/Dxe/PciLib.h
View File

@ -1,6 +1,6 @@
/*++
Copyright (c) 2006, Intel Corporation
Copyright (c) 2006 - 2007, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -26,6 +26,15 @@ Revision History
#ifndef _EFI_PCI_LIB_H
#define _EFI_PCI_LIB_H
//
// Mask definistions for PCD PcdPciIncompatibleDeviceSupportMask
//
#define PCI_INCOMPATIBLE_ACPI_RESOURCE_SUPPORT 0x01
#define PCI_INCOMPATIBLE_READ_SUPPORT 0x02
#define PCI_INCOMPATIBLE_WRITE_SUPPORT 0x04
#define PCI_INCOMPATIBLE_REGISTER_UPDATE_SUPPORT 0x08
#define PCI_INCOMPATIBLE_ACCESS_WIDTH_SUPPORT 0x0a
VOID
InstallHotPlugRequestProtocol (
IN EFI_STATUS *Status
@ -274,4 +283,103 @@ Returns:
--*/
;
/**
Read PCI configuration space through EFI_PCI_IO_PROTOCOL.
@param PciIo A pointer to the EFI_PCI_O_PROTOCOL.
@param Width Signifies the width of the memory operations.
@Param Address The address within the PCI configuration space for the PCI controller.
@param Buffer For read operations, the destination buffer to store the results. For
write operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
@retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
@retval EFI_INVALID_PARAMETER Buffer is NULL.
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
**/
EFI_STATUS
PciIoRead (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
IN UINT32 Address,
IN UINTN Count,
IN OUT VOID *Buffer
);
/**
Write PCI configuration space through EFI_PCI_IO_PROTOCOL.
@param PciIo A pointer to the EFI_PCI_O_PROTOCOL.
@param Width Signifies the width of the memory operations.
@Param Address The address within the PCI configuration space for the PCI controller.
@param Buffer For read operations, the destination buffer to store the results. For
write operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
@retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
@retval EFI_INVALID_PARAMETER Buffer is NULL.
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
**/
EFI_STATUS
PciIoWrite (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
IN UINT32 Address,
IN UINTN Count,
IN OUT VOID *Buffer
);
/**
Write PCI configuration space through EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
@param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
@param Pci A pointer to PCI_TYPE00.
@param Width Signifies the width of the memory operations.
@Param Address The address within the PCI configuration space for the PCI controller.
@param Buffer For read operations, the destination buffer to store the results. For
write operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
@retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
@retval EFI_INVALID_PARAMETER Buffer is NULL.
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
**/
EFI_STATUS
PciRootBridgeIoWrite (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,
IN PCI_TYPE00 *Pci,
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 Address,
IN UINTN Count,
IN OUT VOID *Buffer
);
/**
Read PCI configuration space through EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
@param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
@param Pci A pointer to PCI_TYPE00.
@param Width Signifies the width of the memory operations.
@Param Address The address within the PCI configuration space for the PCI controller.
@param Buffer For read operations, the destination buffer to store the results. For
write operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
@retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
@retval EFI_INVALID_PARAMETER Buffer is NULL.
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
**/
EFI_STATUS
PciRootBridgeIoRead (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,
IN PCI_TYPE00 *Pci,
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 Address,
IN UINTN Count,
IN OUT VOID *Buffer
);
#endif

14
EdkModulePkg/Bus/Pci/PciBus/Dxe/PciOptionRomSupport.c
View File

@ -1,6 +1,6 @@
/*++
Copyright (c) 2006, Intel Corporation
Copyright (c) 2006 - 2007, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -88,8 +88,9 @@ Returns:
AllOnes = 0xfffffffe;
Address = EFI_PCI_ADDRESS (Bus, Device, Function, RomBarIndex);
Status = PciRootBridgeIo->Pci.Write (
Status = PciRootBridgeIoWrite (
PciRootBridgeIo,
&PciIoDevice->Pci,
EfiPciWidthUint32,
Address,
1,
@ -102,8 +103,9 @@ Returns:
//
// read back
//
Status = PciRootBridgeIo->Pci.Read (
Status = PciRootBridgeIoRead (
PciRootBridgeIo,
&PciIoDevice->Pci,
EfiPciWidthUint32,
Address,
1,
@ -334,7 +336,7 @@ Returns:
// Clear all bars
//
for (Offset = 0x10; Offset <= 0x24; Offset += sizeof (UINT32)) {
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, Offset, 1, &gAllZero);
PciIoWrite (PciIo, EfiPciIoWidthUint32, Offset, 1, &gAllZero);
}
//
@ -342,7 +344,7 @@ Returns:
// enable its decoder
//
Value32 = RomBar | 0x1;
PciIo->Pci.Write (
PciIoWrite (
PciIo,
(EFI_PCI_IO_PROTOCOL_WIDTH) EfiPciWidthUint32,
RomBarIndex,
@ -376,7 +378,7 @@ Returns:
// disable rom decode
//
Value32 = 0xFFFFFFFE;
PciIo->Pci.Write (
PciIoWrite (
PciIo,
(EFI_PCI_IO_PROTOCOL_WIDTH) EfiPciWidthUint32,
RomBarIndex,

16
EdkModulePkg/Bus/Pci/PciBus/Dxe/PciPowerManagement.c
View File

@ -1,6 +1,6 @@
/*++
Copyright (c) 2006, Intel Corporation
Copyright (c) 2006 - 2007, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -71,13 +71,13 @@ Returns:
//
// Write PMCSR
//
PciIoDevice->PciIo.Pci.Write (
&PciIoDevice->PciIo,
EfiPciIoWidthUint16,
PowerManagementRegBlock + 4,
1,
&PMCSR
);
PciIoWrite (
&PciIoDevice->PciIo,
EfiPciIoWidthUint16,
PowerManagementRegBlock + 4,
1,
&PMCSR
);
return EFI_SUCCESS;
}

64
EdkModulePkg/Bus/Pci/PciBus/Dxe/PciResourceSupport.c
View File

@ -1,6 +1,6 @@
/*++
Copyright (c) 2006, Intel Corporation
Copyright (c) 2006 - 2007, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -1222,7 +1222,7 @@ Returns:
case PciBarTypeMem32:
case PciBarTypePMem32:
PciIo->Pci.Write (
PciIoWrite (
PciIo,
EfiPciIoWidthUint32,
(Node->PciDev->PciBar[Node->Bar]).Offset,
@ -1239,7 +1239,7 @@ Returns:
Address32 = (UINT32) (Address & 0x00000000FFFFFFFF);
PciIo->Pci.Write (
PciIoWrite (
PciIo,
EfiPciIoWidthUint32,
(Node->PciDev->PciBar[Node->Bar]).Offset,
@ -1249,7 +1249,7 @@ Returns:
Address32 = (UINT32) RShiftU64 (Address, 32);
PciIo->Pci.Write (
PciIoWrite (
PciIo,
EfiPciIoWidthUint32,
(UINT8) ((Node->PciDev->PciBar[Node->Bar]).Offset + 4),
@ -1317,7 +1317,7 @@ Returns:
case PPB_BAR_0:
case PPB_BAR_1:
PciIo->Pci.Write (
PciIoWrite (
PciIo,
EfiPciIoWidthUint32,
(Node->PciDev->PciBar[Node->Bar]).Offset,
@ -1333,7 +1333,7 @@ Returns:
case PPB_IO_RANGE:
Address32 = ((UINT32) (Address)) >> 8;
PciIo->Pci.Write (
PciIoWrite (
PciIo,
EfiPciIoWidthUint8,
0x1C,
@ -1342,7 +1342,7 @@ Returns:
);
Address32 >>= 8;
PciIo->Pci.Write (
PciIoWrite (
PciIo,
EfiPciIoWidthUint16,
0x30,
@ -1352,7 +1352,7 @@ Returns:
Address32 = (UINT32) (Address + Node->Length - 1);
Address32 = ((UINT32) (Address32)) >> 8;
PciIo->Pci.Write (
PciIoWrite (
PciIo,
EfiPciIoWidthUint8,
0x1D,
@ -1361,7 +1361,7 @@ Returns:
);
Address32 >>= 8;
PciIo->Pci.Write (
PciIoWrite (
PciIo,
EfiPciIoWidthUint16,
0x32,
@ -1376,7 +1376,7 @@ Returns:
case PPB_MEM32_RANGE:
Address32 = ((UINT32) (Address)) >> 16;
PciIo->Pci.Write (
PciIoWrite (
PciIo,
EfiPciIoWidthUint16,
0x20,
@ -1386,7 +1386,7 @@ Returns:
Address32 = (UINT32) (Address + Node->Length - 1);
Address32 = ((UINT32) (Address32)) >> 16;
PciIo->Pci.Write (
PciIoWrite (
PciIo,
EfiPciIoWidthUint16,
0x22,
@ -1402,7 +1402,7 @@ Returns:
case PPB_PMEM64_RANGE:
Address32 = ((UINT32) (Address)) >> 16;
PciIo->Pci.Write (
PciIoWrite (
PciIo,
EfiPciIoWidthUint16,
0x24,
@ -1412,7 +1412,7 @@ Returns:
Address32 = (UINT32) (Address + Node->Length - 1);
Address32 = ((UINT32) (Address32)) >> 16;
PciIo->Pci.Write (
PciIoWrite (
PciIo,
EfiPciIoWidthUint16,
0x26,
@ -1421,7 +1421,7 @@ Returns:
);
Address32 = (UINT32) RShiftU64 (Address, 32);
PciIo->Pci.Write (
PciIoWrite (
PciIo,
EfiPciIoWidthUint32,
0x28,
@ -1430,7 +1430,7 @@ Returns:
);
Address32 = (UINT32) RShiftU64 ((Address + Node->Length - 1), 32);
PciIo->Pci.Write (
PciIoWrite (
PciIo,
EfiPciIoWidthUint32,
0x2C,
@ -1915,7 +1915,7 @@ Returns:
switch (Node->Bar) {
case P2C_BAR_0:
PciIo->Pci.Write (
PciIoWrite (
PciIo,
EfiPciIoWidthUint32,
(Node->PciDev->PciBar[Node->Bar]).Offset,
@ -1928,7 +1928,7 @@ Returns:
break;
case P2C_MEM_1:
PciIo->Pci.Write (
PciIoWrite (
PciIo,
EfiPciIoWidthUint32,
0x1c,
@ -1937,7 +1937,7 @@ Returns:
);
TempAddress = Address + Node->Length - 1;
PciIo->Pci.Write (
PciIoWrite (
PciIo,
EfiPciIoWidthUint32,
0x20,
@ -1950,7 +1950,7 @@ Returns:
//
// Set non-prefetchable bit
//
PciIo->Pci.Read (
PciIoRead (
PciIo,
EfiPciIoWidthUint16,
0x3e,
@ -1959,7 +1959,7 @@ Returns:
);
BridgeControl &= 0xfeff;
PciIo->Pci.Write (
PciIoWrite (
PciIo,
EfiPciIoWidthUint16,
0x3e,
@ -1972,7 +1972,7 @@ Returns:
//
// Set pre-fetchable bit
//
PciIo->Pci.Read (
PciIoRead (
PciIo,
EfiPciIoWidthUint16,
0x3e,
@ -1981,7 +1981,7 @@ Returns:
);
BridgeControl |= 0x0100;
PciIo->Pci.Write (
PciIoWrite (
PciIo,
EfiPciIoWidthUint16,
0x3e,
@ -1997,7 +1997,7 @@ Returns:
break;
case P2C_MEM_2:
PciIo->Pci.Write (
PciIoWrite (
PciIo,
EfiPciIoWidthUint32,
0x24,
@ -2007,7 +2007,7 @@ Returns:
TempAddress = Address + Node->Length - 1;
PciIo->Pci.Write (
PciIoWrite (
PciIo,
EfiPciIoWidthUint32,
0x28,
@ -2020,7 +2020,7 @@ Returns:
//
// Set non-prefetchable bit
//
PciIo->Pci.Read (
PciIoRead (
PciIo,
EfiPciIoWidthUint16,
0x3e,
@ -2029,7 +2029,7 @@ Returns:
);
BridgeControl &= 0xfdff;
PciIo->Pci.Write (
PciIoWrite (
PciIo,
EfiPciIoWidthUint16,
0x3e,
@ -2041,7 +2041,7 @@ Returns:
//
// Set pre-fetchable bit
//
PciIo->Pci.Read (
PciIoRead (
PciIo,
EfiPciIoWidthUint16,
0x3e,
@ -2050,7 +2050,7 @@ Returns:
);
BridgeControl |= 0x0200;
PciIo->Pci.Write (
PciIoWrite (
PciIo,
EfiPciIoWidthUint16,
0x3e,
@ -2065,7 +2065,7 @@ Returns:
break;
case P2C_IO_1:
PciIo->Pci.Write (
PciIoWrite (
PciIo,
EfiPciIoWidthUint32,
0x2c,
@ -2073,7 +2073,7 @@ Returns:
&Address
);
TempAddress = Address + Node->Length - 1;
PciIo->Pci.Write (
PciIoWrite (
PciIo,
EfiPciIoWidthUint32,
0x30,
@ -2088,7 +2088,7 @@ Returns:
break;
case P2C_IO_2:
PciIo->Pci.Write (
PciIoWrite (
PciIo,
EfiPciIoWidthUint32,
0x34,
@ -2097,7 +2097,7 @@ Returns:
);
TempAddress = Address + Node->Length - 1;
PciIo->Pci.Write (
PciIoWrite (
PciIo,
EfiPciIoWidthUint32,
0x38,

9
EdkModulePkg/Bus/Pci/PciBus/Dxe/pcibus.c
View File

@ -1,6 +1,6 @@
/*++
Copyright (c) 2006, Intel Corporation
Copyright (c) 2006 - 2007, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -36,7 +36,6 @@ EFI_DRIVER_BINDING_PROTOCOL gPciBusDriverBinding = {
NULL
};
EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *gEfiIncompatiblePciDeviceSupport = NULL;
EFI_HANDLE gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];
UINTN gPciHostBridgeNumber;
BOOLEAN gFullEnumeration;
@ -211,12 +210,6 @@ Returns:
{
EFI_STATUS Status;
Status = gBS->LocateProtocol (
&gEfiIncompatiblePciDeviceSupportProtocolGuid,
NULL,
(VOID **) &gEfiIncompatiblePciDeviceSupport
);
//
// If PCI Platform protocol is available, get it now.
// If the platform implements this, it must be installed before BDS phase

3
EdkModulePkg/Bus/Pci/PciBus/Dxe/pcibus.h
View File

@ -1,6 +1,6 @@
/*++
Copyright (c) 2006, Intel Corporation
Copyright (c) 2006 - 2007, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -216,7 +216,6 @@ typedef struct _PCI_IO_DEVICE {
//
// Global Variables
//
extern EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *gEfiIncompatiblePciDeviceSupport;
extern EFI_DRIVER_BINDING_PROTOCOL gPciBusDriverBinding;
extern EFI_COMPONENT_NAME_PROTOCOL gPciBusComponentName;
extern LIST_ENTRY gPciDevicePool;

40
EdkModulePkg/EdkModulePkg.fpd
View File

@ -3575,6 +3575,8 @@
<Instance ModuleGuid="4674739d-3195-4fb2-8094-ac1d22d00194" PackageGuid="5e0e9358-46b6-4ae2-8218-4ab8b9bbdcec"/>
<Instance ModuleGuid="91c1677a-e57f-4191-8b8e-eb7711a716e0" PackageGuid="5e0e9358-46b6-4ae2-8218-4ab8b9bbdcec"/>
<Instance ModuleGuid="be490364-73d2-420d-950e-f6450ca75dfb" PackageGuid="5e0e9358-46b6-4ae2-8218-4ab8b9bbdcec"/>
<!--Pkg: EdkModulePkg Mod: EdkDxePciIncompatibleDeviceSuppportLib Path: EdkModulePkg\Library\EdkDxePciIncompatibleDeviceSupportLib\EdkDxePciIncompatibleDeviceSupportLib.msa-->
<Instance ModuleGuid="1ca1c1f9-5baf-4204-b6e5-5e24109a4e4e" ModuleVersion="1.0" PackageGuid="68169ab0-d41b-4009-9060-292c253ac43d" PackageVersion="0.3"/>
</Libraries>
<PcdBuildDefinition>
<PcdData ItemType="FIXED_AT_BUILD">
@ -3689,6 +3691,14 @@
<MaxDatumSize>4</MaxDatumSize>
<Value>320</Value>
</PcdData>
<PcdData ItemType="FIXED_AT_BUILD">
<C_Name>PcdPciIncompatibleDeviceSupportMask</C_Name>
<Token>0x0001003f</Token>
<TokenSpaceGuidCName>gEfiEdkModulePkgTokenSpaceGuid</TokenSpaceGuidCName>
<DatumType>UINT8</DatumType>
<MaxDatumSize>1</MaxDatumSize>
<Value>0x0</Value>
</PcdData>
</PcdBuildDefinition>
<ModuleSaBuildOptions>
<FvBinding>NULL</FvBinding>
@ -9019,6 +9029,8 @@
<Instance ModuleGuid="4674739d-3195-4fb2-8094-ac1d22d00194" PackageGuid="5e0e9358-46b6-4ae2-8218-4ab8b9bbdcec"/>
<Instance ModuleGuid="91c1677a-e57f-4191-8b8e-eb7711a716e0" PackageGuid="5e0e9358-46b6-4ae2-8218-4ab8b9bbdcec"/>
<Instance ModuleGuid="be490364-73d2-420d-950e-f6450ca75dfb" PackageGuid="5e0e9358-46b6-4ae2-8218-4ab8b9bbdcec"/>
<!--Pkg: EdkModulePkg Mod: EdkDxePciIncompatibleDeviceSuppportLib Path: EdkModulePkg\Library\EdkDxePciIncompatibleDeviceSupportLib\EdkDxePciIncompatibleDeviceSupportLib.msa-->
<Instance ModuleGuid="1ca1c1f9-5baf-4204-b6e5-5e24109a4e4e" ModuleVersion="1.0" PackageGuid="68169ab0-d41b-4009-9060-292c253ac43d" PackageVersion="0.3"/>
</Libraries>
<PcdBuildDefinition>
<PcdData ItemType="FIXED_AT_BUILD">
@ -9133,6 +9145,14 @@
<MaxDatumSize>4</MaxDatumSize>
<Value>320</Value>
</PcdData>
<PcdData ItemType="FIXED_AT_BUILD">
<C_Name>PcdPciIncompatibleDeviceSupportMask</C_Name>
<Token>0x0001003f</Token>
<TokenSpaceGuidCName>gEfiEdkModulePkgTokenSpaceGuid</TokenSpaceGuidCName>
<DatumType>UINT8</DatumType>
<MaxDatumSize>1</MaxDatumSize>
<Value>0x0</Value>
</PcdData>
</PcdBuildDefinition>
<ModuleSaBuildOptions>
<FvBinding>NULL</FvBinding>
@ -13569,6 +13589,8 @@
<Instance ModuleGuid="4674739d-3195-4fb2-8094-ac1d22d00194" PackageGuid="5e0e9358-46b6-4ae2-8218-4ab8b9bbdcec"/>
<Instance ModuleGuid="91c1677a-e57f-4191-8b8e-eb7711a716e0" PackageGuid="5e0e9358-46b6-4ae2-8218-4ab8b9bbdcec"/>
<Instance ModuleGuid="be490364-73d2-420d-950e-f6450ca75dfb" PackageGuid="5e0e9358-46b6-4ae2-8218-4ab8b9bbdcec"/>
<!--Pkg: EdkModulePkg Mod: EdkDxePciIncompatibleDeviceSuppportLib Path: EdkModulePkg\Library\EdkDxePciIncompatibleDeviceSupportLib\EdkDxePciIncompatibleDeviceSupportLib.msa-->
<Instance ModuleGuid="1ca1c1f9-5baf-4204-b6e5-5e24109a4e4e" ModuleVersion="1.0" PackageGuid="68169ab0-d41b-4009-9060-292c253ac43d" PackageVersion="0.3"/>
</Libraries>
<PcdBuildDefinition>
<PcdData ItemType="FIXED_AT_BUILD">
@ -13683,6 +13705,14 @@
<MaxDatumSize>4</MaxDatumSize>
<Value>320</Value>
</PcdData>
<PcdData ItemType="FIXED_AT_BUILD">
<C_Name>PcdPciIncompatibleDeviceSupportMask</C_Name>
<Token>0x0001003f</Token>
<TokenSpaceGuidCName>gEfiEdkModulePkgTokenSpaceGuid</TokenSpaceGuidCName>
<DatumType>UINT8</DatumType>
<MaxDatumSize>1</MaxDatumSize>
<Value>0x0</Value>
</PcdData>
</PcdBuildDefinition>
<ModuleSaBuildOptions>
<FvBinding>NULL</FvBinding>
@ -17741,6 +17771,8 @@
<Instance ModuleGuid="4674739d-3195-4fb2-8094-ac1d22d00194" PackageGuid="5e0e9358-46b6-4ae2-8218-4ab8b9bbdcec"/>
<Instance ModuleGuid="91c1677a-e57f-4191-8b8e-eb7711a716e0" PackageGuid="5e0e9358-46b6-4ae2-8218-4ab8b9bbdcec"/>
<Instance ModuleGuid="be490364-73d2-420d-950e-f6450ca75dfb" PackageGuid="5e0e9358-46b6-4ae2-8218-4ab8b9bbdcec"/>
<!--Pkg: EdkModulePkg Mod: EdkDxePciIncompatibleDeviceSuppportLib Path: EdkModulePkg\Library\EdkDxePciIncompatibleDeviceSupportLib\EdkDxePciIncompatibleDeviceSupportLib.msa-->
<Instance ModuleGuid="1ca1c1f9-5baf-4204-b6e5-5e24109a4e4e" ModuleVersion="1.0" PackageGuid="68169ab0-d41b-4009-9060-292c253ac43d" PackageVersion="0.3"/>
</Libraries>
<PcdBuildDefinition>
<PcdData ItemType="FIXED_AT_BUILD">
@ -17855,6 +17887,14 @@
<MaxDatumSize>4</MaxDatumSize>
<Value>320</Value>
</PcdData>
<PcdData ItemType="FIXED_AT_BUILD">
<C_Name>PcdPciIncompatibleDeviceSupportMask</C_Name>
<Token>0x0001003f</Token>
<TokenSpaceGuidCName>gEfiEdkModulePkgTokenSpaceGuid</TokenSpaceGuidCName>
<DatumType>UINT8</DatumType>
<MaxDatumSize>1</MaxDatumSize>
<Value>0x0</Value>
</PcdData>
</PcdBuildDefinition>
<ModuleSaBuildOptions>
<FvBinding>NULL</FvBinding>

20
EdkModulePkg/EdkModulePkg.spd
View File

@ -72,6 +72,10 @@
<IncludeHeader>Include/Library/EdkGenericPlatformBdsLib.h</IncludeHeader>
<HelpText>Generic Platform Bds library</HelpText>
</LibraryClass>
<LibraryClass Name="PciIncompatibleDeviceSupportLib">
<IncludeHeader>Include/Library/PciIncompatibleDeviceSupportLib.h</IncludeHeader>
<HelpText>This library includes the PCI incompatible devices list.</HelpText>
</LibraryClass>
</LibraryClassDeclarations>
<IndustryStdIncludes>
<IndustryStdHeader Name="CapsuleName">
@ -404,6 +408,7 @@
<Filename>Library/EdkOemHookStatusCodeLibNull/EdkOemHookStatusCodeLibNull.msa</Filename>
<Filename>Library/EdkGenericBdsLib/EdkGenericBdsLib.msa</Filename>
<Filename>Library/EdkGenericPlatformBdsLib/EdkGenericPlatformBdsLib.msa</Filename>
<Filename>Library/EdkPciIncompatibleDeviceSupportLib/EdkPciIncompatibleDeviceSupportLib.msa</Filename>
<Filename>Universal/Console/ConSplitter/Dxe/ConSplitter.msa</Filename>
<Filename>Universal/Console/GraphicsConsole/Dxe/GraphicsConsole.msa</Filename>
<Filename>Universal/Console/Terminal/Dxe/Terminal.msa</Filename>
@ -1294,5 +1299,20 @@
<DefaultValue>FALSE</DefaultValue>
<HelpText>If this PCD is set as TRUE, NT emulator will be endabled.</HelpText>
</PcdEntry>
<PcdEntry>
<C_Name>PcdPciIncompatibleDeviceSupportMask</C_Name>
<Token>0x0001003f</Token>
<TokenSpaceGuidCName>gEfiEdkModulePkgTokenSpaceGuid</TokenSpaceGuidCName>
<DatumType>UINT8</DatumType>
<ValidUsage>FIXED_AT_BUILD</ValidUsage>
<DefaultValue>0x0</DefaultValue>
<HelpText>The PCD masks for PCI incompatible devices support.
Acpi_Resource_Update_Support :1;
Register_Read_Support :1;
Register_Write_Support :1;
Register_Update_Support :1;
Register_Access_Width_Support :1;
Reserved :3;</HelpText>
</PcdEntry>
</PcdDeclarations>
</PackageSurfaceArea>

134
EdkModulePkg/Include/Library/PciIncompatibleDeviceSupportLib.h Normal file
View File

@ -0,0 +1,134 @@
/** @file
PCI Incompatible device support Libary.
Copyright (c) 2007 Intel Corporation. All rights reserved. <BR>
This software and associated documentation (if any) is furnished
under a license and may only be used or copied in accordance
with the terms of the license. Except as permitted by such
license, no part of this software or documentation may be
reproduced, stored in a retrieval system, or transmitted in any
form or by any means without the express written consent of
Intel Corporation.
**/
#define PCI_REGISTER_READ 0xfffffffffffffff1ULL
#define PCI_REGISTER_WRITE 0xfffffffffffffff2ULL
#define VALUE_NOCARE 0xffffffffffffffffULL
//
// PCI device device information
//
typedef struct {
UINT64 VendorID;
UINT64 DeviceID;
UINT64 RevisionID;
UINT64 SubsystemVendorID;
UINT64 SubsystemID;
} EFI_PCI_DEVICE_INFO;
//
// store hardcode value of resgister
//
typedef struct {
UINT64 AndValue;
UINT64 OrValue;
} EFI_PCI_REGISTER_VALUE_DATA;
//
// store access width information
//
typedef struct {
UINT64 StartOffset;
UINT64 EndOffset;
UINT64 Width;
} EFI_PCI_REGISTER_ACCESS_DATA;
//
// ACPI resource descriptor
//
typedef struct {
UINT64 ResType;
UINT64 GenFlag;
UINT64 SpecificFlag;
UINT64 AddrSpaceGranularity;
UINT64 AddrRangeMin;
UINT64 AddrRangeMax;
UINT64 AddrTranslationOffset;
UINT64 AddrLen;
} EFI_PCI_RESOUCE_DESCRIPTOR;
/**
Checks the incompatible device list for ACPI resource update and return
the configuration.
This function searches the incompatible device list according to request
information. If the PCI device belongs to the devices list, corresponding
configuration informtion will be returned, in the meantime return EFI_SUCCESS.
@param PciDeviceInfo A pointer to PCI device information.
@param Configuration Returned information.
@retval returns EFI_SUCCESS if check incompatible device ok.
Otherwise return EFI_UNSUPPORTED.
**/
RETURN_STATUS
EFIAPI
PciResourceUpdateCheck (
IN EFI_PCI_DEVICE_INFO *PciDeviceInfo,
OUT VOID *Configuration
);
/**
Checks the incompatible device list and return configuration register mask values.
This function searches the incompatible device list according to request
information. If the PCI device belongs to the devices list, corresponding
configuration informtion will be returned, in the meantime return EFI_SUCCESS.
@param PciDeviceInfo A pointer to EFI_PCI_DEVICE_INFO.
@param AccessType Access Type, READ or WRITE.
@param Offset The address within the PCI configuration space.
@param Configuration Returned information.
@retval returns EFI_SUCCESS if check incompatible device ok.
Otherwise return EFI_UNSUPPORTED.
**/
RETURN_STATUS
EFIAPI
PciRegisterUpdateCheck (
IN EFI_PCI_DEVICE_INFO *PciDeviceInfo,
IN UINT64 AccessType,
IN UINT64 Offset,
OUT VOID *Configuration
);
/**
Checks the incompatible device list for access width incompatibility and
return the configuration
This function searches the incompatible device list for access width
incompatibility according to request information. If the PCI device
belongs to the devices list, corresponding configuration informtion
will be returned, in the meantime return EFI_SUCCESS.
@param PciDeviceInfo A pointer to PCI device information.
@param AccessType Access type, READ or WRITE.
@param Offset The address within the PCI configuration space.
@param AccessWidth Access width needs to check incompatibility.
@param Configuration Returned information.
@retval returns EFI_SUCCESS if check incompatible device ok.
Otherwise return EFI_UNSUPPORTED.
**/
RETURN_STATUS
EFIAPI
PciRegisterAccessCheck (
IN EFI_PCI_DEVICE_INFO *PciDeviceInfo,
IN UINT64 AccessType,
IN UINT64 Offset,
IN UINT64 AccessWidth,
OUT VOID *Configuration
);

388
EdkModulePkg/Library/EdkPciIncompatibleDeviceSupportLib/EdkPciIncompatibleDeviceSupportLib.c Normal file
View File

@ -0,0 +1,388 @@
/** @file
The implementation of PCI incompatible device support libary.
Copyright (c) 2007 Intel Corporation. All rights reserved. <BR>
This software and associated documentation (if any) is furnished
under a license and may only be used or copied in accordance
with the terms of the license. Except as permitted by such
license, no part of this software or documentation may be
reproduced, stored in a retrieval system, or transmitted in any
form or by any means without the express written consent of
Intel Corporation.
**/
#include "IncompatiblePciDeviceList.h"
/**
Check whether two PCI devices matched
@param PciDeviceInfo A pointer to EFI_PCI_DEVICE_INFO.
@param Header A pointer to EFI_PCI_DEVICE_INFO.
@retval returns EFI_SUCCESS if two PCI device matched.
**/
STATIC
EFI_STATUS
DeviceCheck (
IN EFI_PCI_DEVICE_INFO *PciDeviceInfo,
IN EFI_PCI_DEVICE_INFO *Header
)
{
//
// See if the Header matches the parameters passed in
//
if (Header->VendorID != DEVICE_ID_NOCARE) {
if (PciDeviceInfo->VendorID != Header->VendorID) {
return EFI_UNSUPPORTED;
}
}
if (Header->DeviceID != DEVICE_ID_NOCARE) {
if (PciDeviceInfo->DeviceID != Header->DeviceID) {
return EFI_UNSUPPORTED;
}
}
if (Header->RevisionID != DEVICE_ID_NOCARE) {
if (PciDeviceInfo->RevisionID != Header->RevisionID) {
return EFI_UNSUPPORTED;
}
}
if (Header->SubsystemVendorID != DEVICE_ID_NOCARE) {
if (PciDeviceInfo->SubsystemVendorID != Header->SubsystemVendorID) {
return EFI_UNSUPPORTED;
}
}
if (Header->SubsystemID != DEVICE_ID_NOCARE) {
if (PciDeviceInfo->SubsystemID != Header->SubsystemID) {
return EFI_UNSUPPORTED;
}
}
return EFI_SUCCESS;
}
/**
Check the incompatible device list for ACPI resource update and return
the configuration
This function searches the incompatible device list according to request
information. If the PCI device belongs to the devices list, corresponding
configuration informtion will be returned, in the meantime return EFI_SUCCESS.
@param PciDeviceInfo A pointer to PCI device information.
@param Configuration Returned information.
@retval returns EFI_SUCCESS if check incompatible device ok.
Otherwise return EFI_UNSUPPORTED.
**/
RETURN_STATUS
EFIAPI
PciResourceUpdateCheck (
IN EFI_PCI_DEVICE_INFO *PciDeviceInfo,
OUT VOID *Configuration
)
{
UINT64 Tag;
UINT64 *ListPtr;
UINT64 *TempListPtr;
EFI_PCI_DEVICE_INFO *Header;
EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *AcpiPtr;
EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *OldAcpiPtr;
EFI_PCI_RESOUCE_DESCRIPTOR *Dsc;
EFI_ACPI_END_TAG_DESCRIPTOR *PtrEnd;
UINTN Index;
ASSERT (PciDeviceInfo != NULL);
//
// Initialize the return value to NULL
//
* (VOID **) Configuration = NULL;
ListPtr = IncompatiblePciDeviceListForResource;
while (*ListPtr != LIST_END_TAG) {
Tag = *ListPtr;
switch (Tag) {
case DEVICE_INF_TAG:
Header = (EFI_PCI_DEVICE_INFO *) (ListPtr + 1);
ListPtr = ListPtr + 1 + sizeof (EFI_PCI_DEVICE_INFO) / sizeof (UINT64);
if (DeviceCheck (PciDeviceInfo, Header) != EFI_SUCCESS) {
continue;
}
//
// Matched an item, so construct the ACPI descriptor for the resource.
//
//
// Count the resource items so that to allocate space
//
for (Index = 0, TempListPtr = ListPtr; *TempListPtr == DEVICE_RES_TAG; Index++) {
TempListPtr = TempListPtr + 1 + ((sizeof (EFI_PCI_RESOUCE_DESCRIPTOR)) / sizeof (UINT64));
}
//
// If there is at least one type of resource request,
// allocate a acpi resource node
//
if (Index == 0) {
return EFI_ABORTED;
}
AcpiPtr = AllocateZeroPool (
sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * Index + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)
);
OldAcpiPtr = AcpiPtr;
//
// Fill the EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR structure
// according to the EFI_PCI_RESOUCE_DESCRIPTOR structure
//
for (; *ListPtr == DEVICE_RES_TAG;) {
Dsc = (EFI_PCI_RESOUCE_DESCRIPTOR *) (ListPtr + 1);
AcpiPtr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
AcpiPtr->Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);
AcpiPtr->ResType = (UINT8) Dsc->ResType;
AcpiPtr->GenFlag = (UINT8) Dsc->GenFlag;
AcpiPtr->SpecificFlag = (UINT8) Dsc->SpecificFlag;
AcpiPtr->AddrSpaceGranularity = Dsc->AddrSpaceGranularity;;
AcpiPtr->AddrRangeMin = Dsc->AddrRangeMin;
AcpiPtr->AddrRangeMax = Dsc->AddrRangeMax;
AcpiPtr->AddrTranslationOffset = Dsc->AddrTranslationOffset;
AcpiPtr->AddrLen = Dsc->AddrLen;
ListPtr = ListPtr + 1 + ((sizeof (EFI_PCI_RESOUCE_DESCRIPTOR)) / sizeof (UINT64));
AcpiPtr++;
}
//
// put the checksum
//
PtrEnd = (EFI_ACPI_END_TAG_DESCRIPTOR *) (AcpiPtr);
PtrEnd->Desc = ACPI_END_TAG_DESCRIPTOR;
PtrEnd->Checksum = 0;
*(VOID **) Configuration = OldAcpiPtr;
return EFI_SUCCESS;
case DEVICE_RES_TAG:
//
// Adjust the pointer to the next PCI resource descriptor item
//
ListPtr = ListPtr + 1 + ((sizeof (EFI_PCI_RESOUCE_DESCRIPTOR)) / sizeof (UINT64));
break;
default:
return EFI_UNSUPPORTED;
}
}
return EFI_UNSUPPORTED;
}
/**
Check the incompatible device list and return configuraton register mask values.
This function searches the incompatible device list according to request
information. If the PCI device belongs to the devices list, corresponding
configuration informtion will be returned, in the meantime return EFI_SUCCESS.
@param PciDeviceInfo A pointer to EFI_PCI_DEVICE_INFO.
@param AccessType Access Type, READ or WRITE.
@param Offset The address within the PCI configuration space.
@param Configuration Returned information.
@retval returns EFI_SUCCESS if check incompatible device ok.
Otherwise return EFI_UNSUPPORTED.
**/
RETURN_STATUS
EFIAPI
PciRegisterUpdateCheck (
IN EFI_PCI_DEVICE_INFO *PciDeviceInfo,
IN UINT64 AccessType,
IN UINT64 Offset,
OUT VOID *Configuration
)
{
EFI_PCI_DEVICE_INFO *Header;
UINT64 Tag;
UINT64 *ListPtr;
EFI_PCI_REGISTER_VALUE_DATA *RegisterPtr;
EFI_PCI_REGISTER_VALUE_DATA *Dsc;
ASSERT (PciDeviceInfo != NULL);
ListPtr = IncompatiblePciDeviceListForRegister;
//
// Initialize the return value to NULL
//
* (VOID **) Configuration = NULL;
while (*ListPtr != LIST_END_TAG) {
Tag = *ListPtr;
switch (Tag) {
case DEVICE_INF_TAG:
Header = (EFI_PCI_DEVICE_INFO *) (ListPtr + 1);
ListPtr = ListPtr + 1 + sizeof (EFI_PCI_DEVICE_INFO) / sizeof (UINT64);
//
// Check whether the PCI device matches the device in the incompatible devices list?
// If not, ship next
//
if (DeviceCheck (PciDeviceInfo, Header) != EFI_SUCCESS) {
continue;
}
//
// Matched an item, check whether access matches?
//
for (; *ListPtr == DEVICE_RES_TAG;) {
ListPtr ++;
if (((EFI_PCI_REGISTER_VALUE_DESCRIPTOR *)ListPtr)->Offset == (Offset & 0xfc)) {
if (((EFI_PCI_REGISTER_VALUE_DESCRIPTOR *)ListPtr)->AccessType == AccessType) {
Dsc = (EFI_PCI_REGISTER_VALUE_DATA *) (ListPtr + 2);
RegisterPtr = AllocateZeroPool (sizeof (EFI_PCI_REGISTER_VALUE_DATA));
RegisterPtr->AndValue = Dsc->AndValue;
RegisterPtr->OrValue = Dsc->OrValue;
*(VOID **) Configuration = RegisterPtr;
return EFI_SUCCESS;
}
}
ListPtr += sizeof (EFI_PCI_REGISTER_VALUE_DESCRIPTOR) / (sizeof (UINT64));
}
return EFI_UNSUPPORTED;
case DEVICE_RES_TAG:
//
// Adjust the pointer to the next item
//
ListPtr = ListPtr + 1 + ((sizeof (EFI_PCI_REGISTER_VALUE_DESCRIPTOR)) / sizeof (UINT64));
break;
default:
return EFI_UNSUPPORTED;
}
}
return EFI_UNSUPPORTED;
}
/**
Check the incompatible device list for access width incompatibility and
return the configuration
This function searches the incompatible device list for access width
incompatibility according to request information. If the PCI device
belongs to the devices list, corresponding configuration informtion
will be returned, in the meantime return EFI_SUCCESS.
@param PciDeviceInfo A pointer to PCI device information.
@param AccessType Access type, READ or WRITE.
@param Offset The address within the PCI configuration space.
@param AccessWidth Access width needs to check incompatibility.
@param Configuration Returned information.
@retval returns EFI_SUCCESS if check incompatible device ok.
Otherwise return EFI_UNSUPPORTED.
**/
RETURN_STATUS
EFIAPI
PciRegisterAccessCheck (
IN EFI_PCI_DEVICE_INFO *PciDeviceInfo,
IN UINT64 AccessType,
IN UINT64 Offset,
IN UINT64 AccessWidth,
OUT VOID *Configuration
)
{
EFI_PCI_DEVICE_INFO *Header;
UINT64 Tag;
UINT64 *ListPtr;
EFI_PCI_REGISTER_ACCESS_DATA *RegisterPtr;
EFI_PCI_REGISTER_ACCESS_DATA *Dsc;
ASSERT (PciDeviceInfo != NULL);
ListPtr = DeviceListForAccessWidth;
//
// Initialize the return value to NULL
//
* (VOID **) Configuration = NULL;
while (*ListPtr != LIST_END_TAG) {
Tag = *ListPtr;
switch (Tag) {
case DEVICE_INF_TAG:
Header = (EFI_PCI_DEVICE_INFO *) (ListPtr + 1);
ListPtr = ListPtr + 1 + sizeof (EFI_PCI_DEVICE_INFO) / sizeof (UINT64);
//
// Check whether the PCI device matches the device in the incompatible devices list?
// If not, ship next
//
if (DeviceCheck (PciDeviceInfo, Header) != EFI_SUCCESS) {
continue;
}
//
// Matched an item, check whether access matches?
//
for (; *ListPtr == DEVICE_RES_TAG;) {
ListPtr ++;
if (((EFI_PCI_REGISTER_ACCESS_DESCRIPTOR *) ListPtr)->AccessType == AccessType &&
((EFI_PCI_REGISTER_ACCESS_DESCRIPTOR *) ListPtr)->AccessWidth == AccessWidth ) {
Dsc = (EFI_PCI_REGISTER_ACCESS_DATA *) (ListPtr + 2);
if((Dsc->StartOffset <= Offset) && (Dsc->EndOffset > Offset)) {
RegisterPtr = AllocateZeroPool (sizeof (EFI_PCI_REGISTER_ACCESS_DATA));
RegisterPtr->StartOffset = Dsc->StartOffset;
RegisterPtr->EndOffset = Dsc->EndOffset;
RegisterPtr->Width = Dsc->Width;
*(VOID **) Configuration = RegisterPtr;
return EFI_SUCCESS;
}
}
ListPtr += sizeof (EFI_PCI_REGISTER_ACCESS_DESCRIPTOR) / (sizeof (UINT64));
}
return EFI_UNSUPPORTED;
case DEVICE_RES_TAG:
//
// Adjust the pointer to the next item
//
ListPtr = ListPtr + 1 + ((sizeof (EFI_PCI_REGISTER_ACCESS_DESCRIPTOR)) / sizeof (UINT64));
break;
default:
return EFI_UNSUPPORTED;
}
}
return EFI_UNSUPPORTED;
}

44
EdkModulePkg/Library/EdkPciIncompatibleDeviceSupportLib/EdkPciIncompatibleDeviceSupportLib.msa Normal file
View File

@ -0,0 +1,44 @@
<?xml version="1.0" encoding="UTF-8"?>
<ModuleSurfaceArea xmlns="http://www.TianoCore.org/2006/Edk2.0" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<MsaHeader>
<ModuleName>EdkPciIncompatibleDeviceSuppportLib</ModuleName>
<ModuleType>DXE_DRIVER</ModuleType>
<GuidValue>1ca1c1f9-5baf-4204-b6e5-5e24109a4e4e</GuidValue>
<Version>1.0</Version>
<Abstract>PCI Incompatible device support Library</Abstract>
<Description>Check PCI incompatible devices and set necessary configuration</Description>
<Copyright>Copyright (c) 2007, Intel Corporation.</Copyright>
<License>All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.</License>
<Specification>FRAMEWORK_BUILD_PACKAGING_SPECIFICATION 0x00000052</Specification>
</MsaHeader>
<ModuleDefinitions>
<SupportedArchitectures>IA32 X64 IPF EBC</SupportedArchitectures>
<BinaryModule>false</BinaryModule>
<OutputFileBasename>EdkPciIncompatibleDeviceSupportLib</OutputFileBasename>
</ModuleDefinitions>
<LibraryClassDefinitions>
<LibraryClass Usage="ALWAYS_PRODUCED">
<Keyword>PciIncompatibleDeviceSupportLib</Keyword>
</LibraryClass>
<LibraryClass Usage="ALWAYS_CONSUMED">
<Keyword>MemoryAllocationLib</Keyword>
</LibraryClass>
</LibraryClassDefinitions>
<SourceFiles>
<Filename>EdkPciIncompatibleDeviceSupportLib.c</Filename>
<Filename>IncompatiblePciDeviceList.h</Filename>
</SourceFiles>
<PackageDependencies>
<Package PackageGuid="5e0e9358-46b6-4ae2-8218-4ab8b9bbdcec"/>
<Package PackageGuid="68169ab0-d41b-4009-9060-292c253ac43d"/>
</PackageDependencies>
<Externs>
<Specification>EFI_SPECIFICATION_VERSION 0x00020000</Specification>
<Specification>EDK_RELEASE_VERSION 0x00020000</Specification>
</Externs>
</ModuleSurfaceArea>

209
EdkModulePkg/Library/EdkPciIncompatibleDeviceSupportLib/IncompatiblePciDeviceList.h Normal file
View File

@ -0,0 +1,209 @@
/** @file
The incompatible PCI device list
Copyright (c) 2007 Intel Corporation. All rights reserved. <BR>
This software and associated documentation (if any) is furnished
under a license and may only be used or copied in accordance
with the terms of the license. Except as permitted by such
license, no part of this software or documentation may be
reproduced, stored in a retrieval system, or transmitted in any
form or by any means without the express written consent of
Intel Corporation.
**/
#ifndef _EFI_INCOMPATIBLE_PCI_DEVICE_LIST_H
#define _EFI_INCOMPATIBLE_PCI_DEVICE_LIST_H
#include <IndustryStandard/pci22.h>
#include <IndustryStandard/Acpi.h>
#define PCI_DEVICE_ID(VendorId, DeviceId, Revision, SubVendorId, SubDeviceId) \
VendorId, DeviceId, Revision, SubVendorId, SubDeviceId
#define PCI_BAR_TYPE_IO ACPI_ADDRESS_SPACE_TYPE_IO
#define PCI_BAR_TYPE_MEM ACPI_ADDRESS_SPACE_TYPE_MEM
#define DEVICE_INF_TAG 0xFFF2
#define DEVICE_RES_TAG 0xFFF1
#define LIST_END_TAG 0x0000
//
// descriptor for access width of incompatible PCI device
//
typedef struct {
UINT64 AccessType;
UINT64 AccessWidth;
EFI_PCI_REGISTER_ACCESS_DATA PciRegisterAccessData;
} EFI_PCI_REGISTER_ACCESS_DESCRIPTOR;
//
// descriptor for register value of incompatible PCI device
//
typedef struct {
UINT64 AccessType;
UINT64 Offset;
EFI_PCI_REGISTER_VALUE_DATA PciRegisterValueData;
} EFI_PCI_REGISTER_VALUE_DESCRIPTOR;
//
// the incompatible PCI devices list for ACPI resource
//
GLOBAL_REMOVE_IF_UNREFERENCED UINT64 IncompatiblePciDeviceListForResource[] = {
//
// DEVICE_INF_TAG,
// PCI_DEVICE_ID (VendorID, DeviceID, Revision, SubVendorId, SubDeviceId),
// DEVICE_RES_TAG,
// ResType, GFlag , SFlag, Granularity, RangeMin,
// RangeMax, Offset, AddrLen
//
//
// Device Adaptec 9004
//
DEVICE_INF_TAG,
PCI_DEVICE_ID(0x9004, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),
DEVICE_RES_TAG,
PCI_BAR_TYPE_IO,
PCI_ACPI_UNUSED,
PCI_ACPI_UNUSED,
PCI_ACPI_UNUSED,
PCI_ACPI_UNUSED,
PCI_BAR_EVEN_ALIGN,
PCI_BAR_ALL,
PCI_BAR_NOCHANGE,
//
// Device Adaptec 9005
//
DEVICE_INF_TAG,
PCI_DEVICE_ID(0x9005, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),
DEVICE_RES_TAG,
PCI_BAR_TYPE_IO,
PCI_ACPI_UNUSED,
PCI_ACPI_UNUSED,
PCI_ACPI_UNUSED,
PCI_ACPI_UNUSED,
PCI_BAR_EVEN_ALIGN,
PCI_BAR_ALL,
PCI_BAR_NOCHANGE,
//
// Device QLogic 1007
//
DEVICE_INF_TAG,
PCI_DEVICE_ID(0x1077, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),
DEVICE_RES_TAG,
PCI_BAR_TYPE_IO,
PCI_ACPI_UNUSED,
PCI_ACPI_UNUSED,
PCI_ACPI_UNUSED,
PCI_ACPI_UNUSED,
PCI_BAR_EVEN_ALIGN,
PCI_BAR_ALL,
PCI_BAR_NOCHANGE,
//
// Device Agilent 103C
//
DEVICE_INF_TAG,
PCI_DEVICE_ID(0x103C, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),
DEVICE_RES_TAG,
PCI_BAR_TYPE_IO,
PCI_ACPI_UNUSED,
PCI_ACPI_UNUSED,
PCI_ACPI_UNUSED,
PCI_ACPI_UNUSED,
PCI_BAR_EVEN_ALIGN,
PCI_BAR_ALL,
PCI_BAR_NOCHANGE,
//
// Device Agilent 15BC
//
DEVICE_INF_TAG,
PCI_DEVICE_ID(0x15BC, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),
DEVICE_RES_TAG,
PCI_BAR_TYPE_IO,
PCI_ACPI_UNUSED,
PCI_ACPI_UNUSED,
PCI_ACPI_UNUSED,
PCI_ACPI_UNUSED,
PCI_BAR_EVEN_ALIGN,
PCI_BAR_ALL,
PCI_BAR_NOCHANGE,
//
// The end of the list
//
LIST_END_TAG
};
//
// the incompatible PCI devices list for the values of configuration registers
//
GLOBAL_REMOVE_IF_UNREFERENCED UINT64 IncompatiblePciDeviceListForRegister[] = {
//
// DEVICE_INF_TAG,
// PCI_DEVICE_ID (VendorID, DeviceID, Revision, SubVendorId, SubDeviceId),
// PCI_RES_TAG,
// PCI_ACCESS_TYPE, PCI_CONFIG_ADDRESS,
// AND_VALUE, OR_VALUE
//
// Device Lava 0x1407, DeviceId 0x0110
//
DEVICE_INF_TAG,
PCI_DEVICE_ID(0x1407, 0x0110, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),
DEVICE_RES_TAG,
PCI_REGISTER_READ,
PCI_CAPBILITY_POINTER_OFFSET,
0xffffff00,
VALUE_NOCARE,
//
// Device Lava 0x1407, DeviceId 0x0111
//
DEVICE_INF_TAG,
PCI_DEVICE_ID(0x1407, 0x0111, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),
DEVICE_RES_TAG,
PCI_REGISTER_READ,
PCI_CAPBILITY_POINTER_OFFSET,
0xffffff00,
VALUE_NOCARE,
//
// The end of the list
//
LIST_END_TAG
};
//
// the incompatible PCI devices list for the access width of configuration registers
//
GLOBAL_REMOVE_IF_UNREFERENCED UINT64 DeviceListForAccessWidth[] = {
//
// DEVICE_INF_TAG,
// PCI_DEVICE_ID (VendorID, DeviceID, Revision, SubVendorId, SubDeviceId),
// DEVICE_RES_TAG,
// PCI_ACCESS_TYPE, PCI_ACCESS_WIDTH,
// START_ADDRESS, END_ADDRESS,
// ACTUAL_PCI_ACCESS_WIDTH,
//
//
// Sample Device
//
//DEVICE_INF_TAG,
//PCI_DEVICE_ID(0xXXXX, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),
//DEVICE_RES_TAG,
//PCI_REGISTER_READ,
//EfiPciWidthUint8,
//0,
//0xFF,
//EfiPciWidthUint32,
//
//
// The end of the list
//
LIST_END_TAG
};
#endif