mirror of https://github.com/acidanthera/audk.git
IntelSiliconPkg: Updated IgdOpregion.h based on latest spec
Updated IgdOpregion.h to align with latest specification https://01.org/sites/default/files/documentation/skl_opregion_rev0p5.pdf 1) Updated Mailbox structures to align with latest spec 2) Added Mailbox 5 structure 3) Added defines for Signature and Mailbox support Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
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Giri P Mudusuru
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98e059ba16
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@ -2,14 +2,7 @@
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IGD OpRegion definition from Intel Integrated Graphics Device OpRegion
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Specification.
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https://01.org/sites/default/files/documentation/acpi_igd_opregion_spec_0.pdf
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There are some mismatch between the specification and the implementation.
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The definition follows the latest implementation.
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1) INTEL_IGD_OPREGION_HEADER.RSV1[0xA0]
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2) INTEL_IGD_OPREGION_MBOX1.RSV3[0x3C]
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3) INTEL_IGD_OPREGION_MBOX3.RSV5[0x62]
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4) INTEL_IGD_OPREGION_VBT.RVBT[0x1800] Size is 6KB
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https://01.org/sites/default/files/documentation/skl_opregion_rev0p5.pdf
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Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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@ -24,6 +17,13 @@
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#ifndef _IGD_OPREGION_H_
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#define _IGD_OPREGION_H_
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#define IGD_OPREGION_HEADER_SIGN "IntelGraphicsMem"
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#define IGD_OPREGION_HEADER_MBOX1 BIT0
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#define IGD_OPREGION_HEADER_MBOX2 BIT1
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#define IGD_OPREGION_HEADER_MBOX3 BIT2
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#define IGD_OPREGION_HEADER_MBOX4 BIT3
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#define IGD_OPREGION_HEADER_MBOX5 BIT4
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/**
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OpRegion structures:
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Sub-structures define the different parts of the OpRegion followed by the
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@ -49,7 +49,9 @@ typedef struct {
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UINT8 GVER[0x10]; ///< Offset 0x48 Graphic Driver Build Version
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UINT32 MBOX; ///< Offset 0x58 Supported Mailboxes
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UINT32 DMOD; ///< Offset 0x5C Driver Model
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UINT8 RSV1[0xA0]; ///< Offset 0x60 Reserved
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UINT32 PCON; ///< Offset 0x60 Platform Configuration
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CHAR16 DVER[0x10] ///< Offset 0x64 GOP Version
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UINT8 RM01[0x7C]; ///< Offset 0x84 Reserved Must be zero
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} IGD_OPREGION_HEADER;
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///
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@ -60,7 +62,7 @@ typedef struct {
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UINT32 DRDY; ///< Offset 0x100 Driver Readiness
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UINT32 CSTS; ///< Offset 0x104 Status
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UINT32 CEVT; ///< Offset 0x108 Current Event
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UINT8 RSVD[0x14]; ///< Offset 0x10C Reserved Must be Zero
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UINT8 RM11[0x14]; ///< Offset 0x10C Reserved Must be Zero
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UINT32 DIDL[8]; ///< Offset 0x120 Supported Display Devices ID List
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UINT32 CPDL[8]; ///< Offset 0x140 Currently Attached Display Devices List
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UINT32 CADL[8]; ///< Offset 0x160 Currently Active Display Devices List
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@ -74,7 +76,9 @@ typedef struct {
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UINT32 EVTS; ///< Offset 0x1B8 Events supported by ASL
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UINT32 CNOT; ///< Offset 0x1BC Current OS Notification
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UINT32 NRDY; ///< Offset 0x1C0 Driver Status
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UINT8 RSV3[0x3C]; ///< Offset 0x1C4 - 0x1FF Reserved
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UINT8 DID2[0x1C]; ///< Offset 0x1C4 Extended Supported Devices ID List (DOD)
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UINT8 CPD2[0x1C]; ///< Offset 0x1E0 Extended Attached Display Devices List
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UINT8 RM12[4]; ///< Offset 0x1FC - 0x1FF Reserved Must be zero
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} IGD_OPREGION_MBOX1;
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///
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@ -85,7 +89,7 @@ typedef struct {
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UINT32 SCIC; ///< Offset 0x200 Software SCI Command / Status / Data
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UINT32 PARM; ///< Offset 0x204 Software SCI Parameters
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UINT32 DSLP; ///< Offset 0x208 Driver Sleep Time Out
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UINT8 RSV4[0xF4]; ///< Offset 0x20C - 0x2FF Reserved
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UINT8 RM21[0xF4]; ///< Offset 0x20C - 0x2FF Reserved Must be zero
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} IGD_OPREGION_MBOX2;
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///
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@ -106,7 +110,13 @@ typedef struct {
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UINT8 PLUT[0x4A]; ///< Offset 0x34C Panel Look Up Table & Identifier
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UINT32 PFMB; ///< Offset 0x396 PWM Frequency and Minimum Brightness
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UINT32 CCDV; ///< Offset 0x39A Color Correction Default Values
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UINT8 RSV5[0x62]; ///< Offset 0x39E - 0x3FF Reserved
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UINT32 PCFT; ///< Offset 0x39E Power Conservation Features
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UINT32 SROT; ///< Offset 0x3A2 Supported Rotation Angles
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UINT32 IUER; ///< Offset 0x3A6 Intel Ultrabook(TM) Event Register
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UINT64 FDSS; ///< Offset 0x3AA DSS Buffer address allocated for IFFS feature
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UINT32 FDSP; ///< Offset 0x3B2 Size of DSS buffer
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UINT32 STAT; ///< Offset 0x3B6 State Indicator
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UINT8 RM31[0x45]; ///< Offset 0x3BA - 0x3FF Reserved Must be zero
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} IGD_OPREGION_MBOX3;
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///
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@ -117,6 +127,16 @@ typedef struct {
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UINT8 RVBT[0x1800]; ///< Offset 0x400 - 0x1BFF Raw VBT Data
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} IGD_OPREGION_MBOX4;
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///
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/// OpRegion Mailbox 5 - BIOS/Driver Notification - Data storage BIOS to Driver data sync
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/// Offset 0x1C00, Size 0x400
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///
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typedef struct {
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UINT32 PHED; ///< Offset 0x1C00 Panel Header
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UINT8 BDDC[0x100]; ///< Offset 0x1C04 Panel EDID (DDC data)
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UINT8 RM51[0x2FC]; ///< Offset 0x1D04 - 0x1FFF Reserved Must be zero
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} IGD_OPREGION_MBOX5;
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///
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/// IGD OpRegion Structure
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///
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@ -126,6 +146,7 @@ typedef struct {
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IGD_OPREGION_MBOX2 MBox2; ///< Mailbox 2: Software SCI Interface (Offset 0x200, Size 0x100)
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IGD_OPREGION_MBOX3 MBox3; ///< Mailbox 3: BIOS to Driver Notification (Offset 0x300, Size 0x100)
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IGD_OPREGION_MBOX4 MBox4; ///< Mailbox 4: Video BIOS Table (VBT) (Offset 0x400, Size 0x1800)
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IGD_OPREGION_MBOX5 MBox5; ///< Mailbox 5: BIOS to Driver Notification Extension (Offset 0x1C00, Size 0x400)
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} IGD_OPREGION_STRUCTURE;
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#pragma pack()
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