mirror of https://github.com/acidanthera/audk.git
UefiCpuPkg PiSmmCpuDxeSmm: Convert X64/SmiEntry.asm to NASM
Manually convert X64/SmiEntry.asm to X64/SmiEntry.nasm Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com>
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Liming Gao
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;------------------------------------------------------------------------------ ;
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; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
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; This program and the accompanying materials
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; are licensed and made available under the terms and conditions of the BSD License
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; which accompanies this distribution. The full text of the license may be found at
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; http://opensource.org/licenses/bsd-license.php.
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;
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; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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;
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; Module Name:
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;
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; SmiEntry.nasm
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;
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; Abstract:
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;
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; Code template of the SMI handler for a particular processor
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;
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;-------------------------------------------------------------------------------
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;
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; Variables referrenced by C code
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;
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;
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; Constants relating to PROCESSOR_SMM_DESCRIPTOR
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;
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%define DSC_OFFSET 0xfb00
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%define DSC_GDTPTR 0x30
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%define DSC_GDTSIZ 0x38
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%define DSC_CS 14
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%define DSC_DS 16
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%define DSC_SS 18
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%define DSC_OTHERSEG 20
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;
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; Constants relating to CPU State Save Area
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;
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%define SSM_DR6 0xffd0
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%define SSM_DR7 0xffc8
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%define PROTECT_MODE_CS 0x8
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%define PROTECT_MODE_DS 0x20
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%define LONG_MODE_CS 0x38
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%define TSS_SEGMENT 0x40
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%define GDT_SIZE 0x50
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extern ASM_PFX(SmiRendezvous)
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extern ASM_PFX(gSmiHandlerIdtr)
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extern ASM_PFX(CpuSmmDebugEntry)
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extern ASM_PFX(CpuSmmDebugExit)
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global ASM_PFX(gSmbase)
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global ASM_PFX(gSmiStack)
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global ASM_PFX(gSmiCr3)
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global ASM_PFX(gcSmiHandlerTemplate)
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global ASM_PFX(gcSmiHandlerSize)
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DEFAULT REL
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SECTION .text
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BITS 16
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ASM_PFX(gcSmiHandlerTemplate):
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_SmiEntryPoint:
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mov bx, _GdtDesc - _SmiEntryPoint + 0x8000
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mov ax,[cs:DSC_OFFSET + DSC_GDTSIZ]
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dec ax
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mov [cs:bx], ax
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mov eax, [cs:DSC_OFFSET + DSC_GDTPTR]
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mov [cs:bx + 2], eax
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o32 lgdt [cs:bx] ; lgdt fword ptr cs:[bx]
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mov ax, PROTECT_MODE_CS
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mov [cs:bx-0x2],ax
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DB 0x66, 0xbf ; mov edi, SMBASE
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ASM_PFX(gSmbase): DD 0
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lea eax, [edi + (@ProtectedMode - _SmiEntryPoint) + 0x8000]
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mov [cs:bx-0x6],eax
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mov ebx, cr0
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and ebx, 0x9ffafff3
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or ebx, 0x23
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mov cr0, ebx
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jmp dword 0x0:0x0
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_GdtDesc:
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DW 0
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DD 0
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BITS 32
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@ProtectedMode:
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mov ax, PROTECT_MODE_DS
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o16 mov ds, ax
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o16 mov es, ax
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o16 mov fs, ax
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o16 mov gs, ax
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o16 mov ss, ax
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DB 0xbc ; mov esp, imm32
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ASM_PFX(gSmiStack): DD 0
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jmp ProtFlatMode
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BITS 64
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ProtFlatMode:
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DB 0xb8 ; mov eax, offset gSmiCr3
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ASM_PFX(gSmiCr3): DD 0
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mov cr3, rax
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mov eax, 0x668 ; as cr4.PGE is not set here, refresh cr3
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mov cr4, rax ; in PreModifyMtrrs() to flush TLB.
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; Load TSS
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sub esp, 8 ; reserve room in stack
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sgdt [rsp]
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mov eax, [rsp + 2] ; eax = GDT base
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add esp, 8
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mov dl, 0x89
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mov [rax + TSS_SEGMENT + 5], dl ; clear busy flag
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mov eax, TSS_SEGMENT
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ltr ax
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; Switch into @LongMode
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push LONG_MODE_CS ; push cs hardcore here
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call Base ; push reture address for retf later
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Base:
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add dword [rsp], @LongMode - Base; offset for far retf, seg is the 1st arg
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mov ecx, 0xc0000080
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rdmsr
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or ah, 1
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wrmsr
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mov rbx, cr0
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or ebx, 080010000h ; enable paging + WP
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mov cr0, rbx
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retf
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@LongMode: ; long mode (64-bit code) starts here
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mov rax, ASM_PFX(gSmiHandlerIdtr)
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lidt [rax]
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lea ebx, [rdi + DSC_OFFSET]
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mov ax, [rbx + DSC_DS]
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mov ds, eax
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mov ax, [rbx + DSC_OTHERSEG]
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mov es, eax
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mov fs, eax
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mov gs, eax
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mov ax, [rbx + DSC_SS]
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mov ss, eax
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; jmp _SmiHandler ; instruction is not needed
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_SmiHandler:
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mov rbx, [rsp] ; rbx <- CpuIndex
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;
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; Save FP registers
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;
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sub rsp, 0x208
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DB 0x48 ; FXSAVE64
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fxsave [rsp]
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add rsp, -0x20
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mov rcx, rbx
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mov rax, CpuSmmDebugEntry
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call rax
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mov rcx, rbx
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mov rax, SmiRendezvous ; rax <- absolute addr of SmiRedezvous
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call rax
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mov rcx, rbx
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mov rax, CpuSmmDebugExit
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call rax
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add rsp, 0x20
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;
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; Restore FP registers
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;
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DB 0x48 ; FXRSTOR64
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fxrstor [rsp]
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rsm
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gcSmiHandlerSize DW $ - _SmiEntryPoint
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