mirror of https://github.com/acidanthera/audk.git
EmbeddedPkg: remove DwEmmcDxe host controller driver
The Synopsys DesignWare eMMC host controller driver does not implement that SD/MMC host controller protocol that the UEFI spec defines, but an obsolete EDK2-specific one that predates it. It also does not implement the UEFI driver model. Due to this, it has been moved into the edk2-platforms repository, alongside its remaining users, which have been updated to refer to it in its new location. So drop this version from EmbeddedPkg. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@arm.com> Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
This commit is contained in:
Ard Biesheuvel
mergify[bot]
parent
e54310451f
commit
9ad9dc9d4f
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@ -1,127 +0,0 @@
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/** @file
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*
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* Copyright (c) 2014-2017, Linaro Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*
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**/
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#ifndef __DWEMMC_H__
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#define __DWEMMC_H__
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#include <Protocol/EmbeddedGpio.h>
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// DW MMC Registers
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#define DWEMMC_CTRL ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x000)
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#define DWEMMC_PWREN ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x004)
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#define DWEMMC_CLKDIV ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x008)
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#define DWEMMC_CLKSRC ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x00c)
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#define DWEMMC_CLKENA ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x010)
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#define DWEMMC_TMOUT ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x014)
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#define DWEMMC_CTYPE ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x018)
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#define DWEMMC_BLKSIZ ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x01c)
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#define DWEMMC_BYTCNT ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x020)
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#define DWEMMC_INTMASK ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x024)
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#define DWEMMC_CMDARG ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x028)
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#define DWEMMC_CMD ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x02c)
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#define DWEMMC_RESP0 ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x030)
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#define DWEMMC_RESP1 ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x034)
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#define DWEMMC_RESP2 ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x038)
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#define DWEMMC_RESP3 ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x03c)
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#define DWEMMC_RINTSTS ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x044)
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#define DWEMMC_STATUS ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x048)
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#define DWEMMC_FIFOTH ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x04c)
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#define DWEMMC_TCBCNT ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x05c)
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#define DWEMMC_TBBCNT ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x060)
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#define DWEMMC_DEBNCE ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x064)
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#define DWEMMC_HCON ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x070)
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#define DWEMMC_UHSREG ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x074)
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#define DWEMMC_BMOD ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x080)
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#define DWEMMC_DBADDR ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x088)
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#define DWEMMC_IDSTS ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x08c)
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#define DWEMMC_IDINTEN ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x090)
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#define DWEMMC_DSCADDR ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x094)
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#define DWEMMC_BUFADDR ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x098)
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#define DWEMMC_CARDTHRCTL ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0X100)
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#define DWEMMC_DATA ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0X200)
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#define CMD_UPDATE_CLK 0x80202000
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#define CMD_START_BIT (1 << 31)
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#define MMC_8BIT_MODE (1 << 16)
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#define BIT_CMD_RESPONSE_EXPECT (1 << 6)
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#define BIT_CMD_LONG_RESPONSE (1 << 7)
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#define BIT_CMD_CHECK_RESPONSE_CRC (1 << 8)
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#define BIT_CMD_DATA_EXPECTED (1 << 9)
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#define BIT_CMD_READ (0 << 10)
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#define BIT_CMD_WRITE (1 << 10)
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#define BIT_CMD_BLOCK_TRANSFER (0 << 11)
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#define BIT_CMD_STREAM_TRANSFER (1 << 11)
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#define BIT_CMD_SEND_AUTO_STOP (1 << 12)
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#define BIT_CMD_WAIT_PRVDATA_COMPLETE (1 << 13)
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#define BIT_CMD_STOP_ABORT_CMD (1 << 14)
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#define BIT_CMD_SEND_INIT (1 << 15)
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#define BIT_CMD_UPDATE_CLOCK_ONLY (1 << 21)
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#define BIT_CMD_READ_CEATA_DEVICE (1 << 22)
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#define BIT_CMD_CCS_EXPECTED (1 << 23)
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#define BIT_CMD_ENABLE_BOOT (1 << 24)
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#define BIT_CMD_EXPECT_BOOT_ACK (1 << 25)
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#define BIT_CMD_DISABLE_BOOT (1 << 26)
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#define BIT_CMD_MANDATORY_BOOT (0 << 27)
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#define BIT_CMD_ALTERNATE_BOOT (1 << 27)
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#define BIT_CMD_VOLT_SWITCH (1 << 28)
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#define BIT_CMD_USE_HOLD_REG (1 << 29)
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#define BIT_CMD_START (1 << 31)
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#define DWEMMC_INT_EBE (1 << 15) /* End-bit Err */
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#define DWEMMC_INT_SBE (1 << 13) /* Start-bit Err */
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#define DWEMMC_INT_HLE (1 << 12) /* Hardware-lock Err */
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#define DWEMMC_INT_FRUN (1 << 11) /* FIFO UN/OV RUN */
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#define DWEMMC_INT_DRT (1 << 9) /* Data timeout */
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#define DWEMMC_INT_RTO (1 << 8) /* Response timeout */
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#define DWEMMC_INT_DCRC (1 << 7) /* Data CRC err */
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#define DWEMMC_INT_RCRC (1 << 6) /* Response CRC err */
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#define DWEMMC_INT_RXDR (1 << 5)
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#define DWEMMC_INT_TXDR (1 << 4)
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#define DWEMMC_INT_DTO (1 << 3) /* Data trans over */
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#define DWEMMC_INT_CMD_DONE (1 << 2)
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#define DWEMMC_INT_RE (1 << 1)
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#define DWEMMC_IDMAC_DES0_DIC (1 << 1)
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#define DWEMMC_IDMAC_DES0_LD (1 << 2)
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#define DWEMMC_IDMAC_DES0_FS (1 << 3)
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#define DWEMMC_IDMAC_DES0_CH (1 << 4)
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#define DWEMMC_IDMAC_DES0_ER (1 << 5)
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#define DWEMMC_IDMAC_DES0_CES (1 << 30)
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#define DWEMMC_IDMAC_DES0_OWN (1 << 31)
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#define DWEMMC_IDMAC_DES1_BS1(x) ((x) & 0x1fff)
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#define DWEMMC_IDMAC_DES2_BS2(x) (((x) & 0x1fff) << 13)
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#define DWEMMC_IDMAC_SWRESET (1 << 0)
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#define DWEMMC_IDMAC_FB (1 << 1)
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#define DWEMMC_IDMAC_ENABLE (1 << 7)
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#define EMMC_FIX_RCA 6
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/* bits in MMC0_CTRL */
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#define DWEMMC_CTRL_RESET (1 << 0)
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#define DWEMMC_CTRL_FIFO_RESET (1 << 1)
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#define DWEMMC_CTRL_DMA_RESET (1 << 2)
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#define DWEMMC_CTRL_INT_EN (1 << 4)
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#define DWEMMC_CTRL_DMA_EN (1 << 5)
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#define DWEMMC_CTRL_IDMAC_EN (1 << 25)
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#define DWEMMC_CTRL_RESET_ALL (DWEMMC_CTRL_RESET | DWEMMC_CTRL_FIFO_RESET | DWEMMC_CTRL_DMA_RESET)
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#define DWEMMC_STS_DATA_BUSY (1 << 9)
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#define DWEMMC_FIFO_TWMARK(x) (x & 0xfff)
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#define DWEMMC_FIFO_RWMARK(x) ((x & 0x1ff) << 16)
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#define DWEMMC_DMA_BURST_SIZE(x) ((x & 0x7) << 28)
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#define DWEMMC_CARD_RD_THR(x) ((x & 0xfff) << 16)
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#define DWEMMC_CARD_RD_THR_EN (1 << 0)
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#define DWEMMC_GET_HDATA_WIDTH(x) (((x) >> 7) & 0x7)
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#endif // __DWEMMC_H__
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@ -1,688 +0,0 @@
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/** @file
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This file implement the MMC Host Protocol for the DesignWare eMMC.
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Copyright (c) 2014-2017, Linaro Limited. All rights reserved.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Library/BaseMemoryLib.h>
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#include <Library/CacheMaintenanceLib.h>
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#include <Library/DebugLib.h>
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#include <Library/DevicePathLib.h>
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#include <Library/IoLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/PcdLib.h>
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#include <Library/TimerLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <Library/UefiLib.h>
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#include <Protocol/MmcHost.h>
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#include "DwEmmc.h"
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#define DWEMMC_DESC_PAGE 1
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#define DWEMMC_BLOCK_SIZE 512
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#define DWEMMC_DMA_BUF_SIZE (512 * 8)
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#define DWEMMC_MAX_DESC_PAGES 512
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typedef struct {
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UINT32 Des0;
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UINT32 Des1;
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UINT32 Des2;
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UINT32 Des3;
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} DWEMMC_IDMAC_DESCRIPTOR;
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EFI_MMC_HOST_PROTOCOL *gpMmcHost;
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DWEMMC_IDMAC_DESCRIPTOR *gpIdmacDesc;
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EFI_GUID mDwEmmcDevicePathGuid = EFI_CALLER_ID_GUID;
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STATIC UINT32 mDwEmmcCommand;
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STATIC UINT32 mDwEmmcArgument;
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EFI_STATUS
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DwEmmcReadBlockData (
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IN EFI_MMC_HOST_PROTOCOL *This,
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IN EFI_LBA Lba,
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IN UINTN Length,
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IN UINT32* Buffer
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);
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BOOLEAN
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DwEmmcIsPowerOn (
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VOID
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)
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{
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return TRUE;
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}
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EFI_STATUS
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DwEmmcInitialize (
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VOID
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)
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{
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DEBUG ((DEBUG_BLKIO, "DwEmmcInitialize()"));
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return EFI_SUCCESS;
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}
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BOOLEAN
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DwEmmcIsCardPresent (
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IN EFI_MMC_HOST_PROTOCOL *This
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)
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{
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return TRUE;
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}
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BOOLEAN
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DwEmmcIsReadOnly (
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IN EFI_MMC_HOST_PROTOCOL *This
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)
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{
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return FALSE;
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}
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BOOLEAN
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DwEmmcIsDmaSupported (
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IN EFI_MMC_HOST_PROTOCOL *This
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)
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{
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return TRUE;
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}
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EFI_STATUS
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DwEmmcBuildDevicePath (
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IN EFI_MMC_HOST_PROTOCOL *This,
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IN EFI_DEVICE_PATH_PROTOCOL **DevicePath
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)
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{
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EFI_DEVICE_PATH_PROTOCOL *NewDevicePathNode;
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NewDevicePathNode = CreateDeviceNode (HARDWARE_DEVICE_PATH, HW_VENDOR_DP, sizeof (VENDOR_DEVICE_PATH));
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CopyGuid (& ((VENDOR_DEVICE_PATH*)NewDevicePathNode)->Guid, &mDwEmmcDevicePathGuid);
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*DevicePath = NewDevicePathNode;
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return EFI_SUCCESS;
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}
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EFI_STATUS
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DwEmmcUpdateClock (
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VOID
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)
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{
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UINT32 Data;
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/* CMD_UPDATE_CLK */
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Data = BIT_CMD_WAIT_PRVDATA_COMPLETE | BIT_CMD_UPDATE_CLOCK_ONLY |
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BIT_CMD_START;
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MmioWrite32 (DWEMMC_CMD, Data);
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while (1) {
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Data = MmioRead32 (DWEMMC_CMD);
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if (!(Data & CMD_START_BIT)) {
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break;
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}
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Data = MmioRead32 (DWEMMC_RINTSTS);
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if (Data & DWEMMC_INT_HLE) {
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Print (L"failed to update mmc clock frequency\n");
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return EFI_DEVICE_ERROR;
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}
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}
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return EFI_SUCCESS;
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}
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EFI_STATUS
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DwEmmcSetClock (
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IN UINTN ClockFreq
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)
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{
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UINT32 Divider, Rate, Data;
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EFI_STATUS Status;
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BOOLEAN Found = FALSE;
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for (Divider = 1; Divider < 256; Divider++) {
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Rate = PcdGet32 (PcdDwEmmcDxeClockFrequencyInHz);
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if ((Rate / (2 * Divider)) <= ClockFreq) {
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Found = TRUE;
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break;
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}
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}
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if (Found == FALSE) {
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return EFI_NOT_FOUND;
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}
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// Wait until MMC is idle
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do {
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Data = MmioRead32 (DWEMMC_STATUS);
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} while (Data & DWEMMC_STS_DATA_BUSY);
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// Disable MMC clock first
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MmioWrite32 (DWEMMC_CLKENA, 0);
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Status = DwEmmcUpdateClock ();
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ASSERT (!EFI_ERROR (Status));
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MmioWrite32 (DWEMMC_CLKDIV, Divider);
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Status = DwEmmcUpdateClock ();
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ASSERT (!EFI_ERROR (Status));
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// Enable MMC clock
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MmioWrite32 (DWEMMC_CLKENA, 1);
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MmioWrite32 (DWEMMC_CLKSRC, 0);
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Status = DwEmmcUpdateClock ();
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ASSERT (!EFI_ERROR (Status));
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return EFI_SUCCESS;
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}
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EFI_STATUS
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DwEmmcNotifyState (
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IN EFI_MMC_HOST_PROTOCOL *This,
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IN MMC_STATE State
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)
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{
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UINT32 Data;
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EFI_STATUS Status;
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switch (State) {
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case MmcInvalidState:
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return EFI_INVALID_PARAMETER;
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case MmcHwInitializationState:
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MmioWrite32 (DWEMMC_PWREN, 1);
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// If device already turn on then restart it
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Data = DWEMMC_CTRL_RESET_ALL;
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MmioWrite32 (DWEMMC_CTRL, Data);
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do {
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// Wait until reset operation finished
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Data = MmioRead32 (DWEMMC_CTRL);
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} while (Data & DWEMMC_CTRL_RESET_ALL);
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// Setup clock that could not be higher than 400KHz.
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Status = DwEmmcSetClock (400000);
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ASSERT (!EFI_ERROR (Status));
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// Wait clock stable
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MicroSecondDelay (100);
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MmioWrite32 (DWEMMC_RINTSTS, ~0);
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MmioWrite32 (DWEMMC_INTMASK, 0);
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MmioWrite32 (DWEMMC_TMOUT, ~0);
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MmioWrite32 (DWEMMC_IDINTEN, 0);
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MmioWrite32 (DWEMMC_BMOD, DWEMMC_IDMAC_SWRESET);
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MmioWrite32 (DWEMMC_BLKSIZ, DWEMMC_BLOCK_SIZE);
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do {
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Data = MmioRead32 (DWEMMC_BMOD);
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} while (Data & DWEMMC_IDMAC_SWRESET);
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break;
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case MmcIdleState:
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break;
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case MmcReadyState:
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break;
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case MmcIdentificationState:
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break;
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case MmcStandByState:
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break;
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case MmcTransferState:
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break;
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case MmcSendingDataState:
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break;
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case MmcReceiveDataState:
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break;
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case MmcProgrammingState:
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break;
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case MmcDisconnectState:
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break;
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default:
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return EFI_INVALID_PARAMETER;
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}
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return EFI_SUCCESS;
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}
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// Need to prepare DMA buffer first before sending commands to MMC card
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BOOLEAN
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IsPendingReadCommand (
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IN MMC_CMD MmcCmd
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)
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{
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UINTN Mask;
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Mask = BIT_CMD_DATA_EXPECTED | BIT_CMD_READ;
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if ((MmcCmd & Mask) == Mask) {
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return TRUE;
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}
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return FALSE;
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}
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BOOLEAN
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IsPendingWriteCommand (
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IN MMC_CMD MmcCmd
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)
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{
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UINTN Mask;
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Mask = BIT_CMD_DATA_EXPECTED | BIT_CMD_WRITE;
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if ((MmcCmd & Mask) == Mask) {
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return TRUE;
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}
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return FALSE;
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}
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EFI_STATUS
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SendCommand (
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IN MMC_CMD MmcCmd,
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IN UINT32 Argument
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)
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{
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UINT32 Data, ErrMask;
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// Wait until MMC is idle
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do {
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Data = MmioRead32 (DWEMMC_STATUS);
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} while (Data & DWEMMC_STS_DATA_BUSY);
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MmioWrite32 (DWEMMC_RINTSTS, ~0);
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MmioWrite32 (DWEMMC_CMDARG, Argument);
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MmioWrite32 (DWEMMC_CMD, MmcCmd);
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ErrMask = DWEMMC_INT_EBE | DWEMMC_INT_HLE | DWEMMC_INT_RTO |
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DWEMMC_INT_RCRC | DWEMMC_INT_RE;
|
||||
ErrMask |= DWEMMC_INT_DCRC | DWEMMC_INT_DRT | DWEMMC_INT_SBE;
|
||||
do {
|
||||
MicroSecondDelay(500);
|
||||
Data = MmioRead32 (DWEMMC_RINTSTS);
|
||||
|
||||
if (Data & ErrMask) {
|
||||
return EFI_DEVICE_ERROR;
|
||||
}
|
||||
if (Data & DWEMMC_INT_DTO) { // Transfer Done
|
||||
break;
|
||||
}
|
||||
} while (!(Data & DWEMMC_INT_CMD_DONE));
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
EFI_STATUS
|
||||
DwEmmcSendCommand (
|
||||
IN EFI_MMC_HOST_PROTOCOL *This,
|
||||
IN MMC_CMD MmcCmd,
|
||||
IN UINT32 Argument
|
||||
)
|
||||
{
|
||||
UINT32 Cmd = 0;
|
||||
EFI_STATUS Status = EFI_SUCCESS;
|
||||
|
||||
switch (MMC_GET_INDX(MmcCmd)) {
|
||||
case MMC_INDX(0):
|
||||
Cmd = BIT_CMD_SEND_INIT;
|
||||
break;
|
||||
case MMC_INDX(1):
|
||||
Cmd = BIT_CMD_RESPONSE_EXPECT;
|
||||
break;
|
||||
case MMC_INDX(2):
|
||||
Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_LONG_RESPONSE |
|
||||
BIT_CMD_CHECK_RESPONSE_CRC | BIT_CMD_SEND_INIT;
|
||||
break;
|
||||
case MMC_INDX(3):
|
||||
Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
|
||||
BIT_CMD_SEND_INIT;
|
||||
break;
|
||||
case MMC_INDX(7):
|
||||
if (Argument)
|
||||
Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC;
|
||||
else
|
||||
Cmd = 0;
|
||||
break;
|
||||
case MMC_INDX(8):
|
||||
Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
|
||||
BIT_CMD_DATA_EXPECTED | BIT_CMD_READ |
|
||||
BIT_CMD_WAIT_PRVDATA_COMPLETE;
|
||||
break;
|
||||
case MMC_INDX(9):
|
||||
Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
|
||||
BIT_CMD_LONG_RESPONSE;
|
||||
break;
|
||||
case MMC_INDX(12):
|
||||
Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
|
||||
BIT_CMD_STOP_ABORT_CMD;
|
||||
break;
|
||||
case MMC_INDX(13):
|
||||
Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
|
||||
BIT_CMD_WAIT_PRVDATA_COMPLETE;
|
||||
break;
|
||||
case MMC_INDX(16):
|
||||
Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
|
||||
BIT_CMD_DATA_EXPECTED | BIT_CMD_READ |
|
||||
BIT_CMD_WAIT_PRVDATA_COMPLETE;
|
||||
break;
|
||||
case MMC_INDX(17):
|
||||
case MMC_INDX(18):
|
||||
Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
|
||||
BIT_CMD_DATA_EXPECTED | BIT_CMD_READ |
|
||||
BIT_CMD_WAIT_PRVDATA_COMPLETE;
|
||||
break;
|
||||
case MMC_INDX(24):
|
||||
case MMC_INDX(25):
|
||||
Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
|
||||
BIT_CMD_DATA_EXPECTED | BIT_CMD_WRITE |
|
||||
BIT_CMD_WAIT_PRVDATA_COMPLETE;
|
||||
break;
|
||||
case MMC_INDX(30):
|
||||
Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
|
||||
BIT_CMD_DATA_EXPECTED;
|
||||
break;
|
||||
default:
|
||||
Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC;
|
||||
break;
|
||||
}
|
||||
|
||||
Cmd |= MMC_GET_INDX(MmcCmd) | BIT_CMD_USE_HOLD_REG | BIT_CMD_START;
|
||||
if (IsPendingReadCommand (Cmd) || IsPendingWriteCommand (Cmd)) {
|
||||
mDwEmmcCommand = Cmd;
|
||||
mDwEmmcArgument = Argument;
|
||||
} else {
|
||||
Status = SendCommand (Cmd, Argument);
|
||||
}
|
||||
return Status;
|
||||
}
|
||||
|
||||
EFI_STATUS
|
||||
DwEmmcReceiveResponse (
|
||||
IN EFI_MMC_HOST_PROTOCOL *This,
|
||||
IN MMC_RESPONSE_TYPE Type,
|
||||
IN UINT32* Buffer
|
||||
)
|
||||
{
|
||||
if (Buffer == NULL) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
if ( (Type == MMC_RESPONSE_TYPE_R1)
|
||||
|| (Type == MMC_RESPONSE_TYPE_R1b)
|
||||
|| (Type == MMC_RESPONSE_TYPE_R3)
|
||||
|| (Type == MMC_RESPONSE_TYPE_R6)
|
||||
|| (Type == MMC_RESPONSE_TYPE_R7))
|
||||
{
|
||||
Buffer[0] = MmioRead32 (DWEMMC_RESP0);
|
||||
} else if (Type == MMC_RESPONSE_TYPE_R2) {
|
||||
Buffer[0] = MmioRead32 (DWEMMC_RESP0);
|
||||
Buffer[1] = MmioRead32 (DWEMMC_RESP1);
|
||||
Buffer[2] = MmioRead32 (DWEMMC_RESP2);
|
||||
Buffer[3] = MmioRead32 (DWEMMC_RESP3);
|
||||
}
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
VOID
|
||||
DwEmmcAdjustFifoThreshold (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
/* DMA multiple transaction size map to reg value as array index */
|
||||
CONST UINT32 BurstSize[] = {1, 4, 8, 16, 32, 64, 128, 256};
|
||||
UINT32 BlkDepthInFifo, FifoThreshold, FifoWidth, FifoDepth;
|
||||
UINT32 BlkSize = DWEMMC_BLOCK_SIZE, Idx = 0, RxWatermark = 1, TxWatermark, TxWatermarkInvers;
|
||||
|
||||
/* Skip FIFO adjustment if we do not have platform FIFO depth info */
|
||||
FifoDepth = PcdGet32 (PcdDwEmmcDxeFifoDepth);
|
||||
if (!FifoDepth) {
|
||||
return;
|
||||
}
|
||||
|
||||
TxWatermark = FifoDepth / 2;
|
||||
TxWatermarkInvers = FifoDepth - TxWatermark;
|
||||
|
||||
FifoWidth = DWEMMC_GET_HDATA_WIDTH (MmioRead32 (DWEMMC_HCON));
|
||||
if (!FifoWidth) {
|
||||
FifoWidth = 2;
|
||||
} else if (FifoWidth == 2) {
|
||||
FifoWidth = 8;
|
||||
} else {
|
||||
FifoWidth = 4;
|
||||
}
|
||||
|
||||
BlkDepthInFifo = BlkSize / FifoWidth;
|
||||
|
||||
Idx = ARRAY_SIZE (BurstSize) - 1;
|
||||
while (Idx && ((BlkDepthInFifo % BurstSize[Idx]) || (TxWatermarkInvers % BurstSize[Idx]))) {
|
||||
Idx--;
|
||||
}
|
||||
|
||||
RxWatermark = BurstSize[Idx] - 1;
|
||||
FifoThreshold = DWEMMC_DMA_BURST_SIZE (Idx) | DWEMMC_FIFO_TWMARK (TxWatermark)
|
||||
| DWEMMC_FIFO_RWMARK (RxWatermark);
|
||||
MmioWrite32 (DWEMMC_FIFOTH, FifoThreshold);
|
||||
}
|
||||
|
||||
EFI_STATUS
|
||||
PrepareDmaData (
|
||||
IN DWEMMC_IDMAC_DESCRIPTOR* IdmacDesc,
|
||||
IN UINTN Length,
|
||||
IN UINT32* Buffer
|
||||
)
|
||||
{
|
||||
UINTN Cnt, Blks, Idx, LastIdx;
|
||||
|
||||
Cnt = (Length + DWEMMC_DMA_BUF_SIZE - 1) / DWEMMC_DMA_BUF_SIZE;
|
||||
Blks = (Length + DWEMMC_BLOCK_SIZE - 1) / DWEMMC_BLOCK_SIZE;
|
||||
Length = DWEMMC_BLOCK_SIZE * Blks;
|
||||
|
||||
for (Idx = 0; Idx < Cnt; Idx++) {
|
||||
(IdmacDesc + Idx)->Des0 = DWEMMC_IDMAC_DES0_OWN | DWEMMC_IDMAC_DES0_CH |
|
||||
DWEMMC_IDMAC_DES0_DIC;
|
||||
(IdmacDesc + Idx)->Des1 = DWEMMC_IDMAC_DES1_BS1(DWEMMC_DMA_BUF_SIZE);
|
||||
/* Buffer Address */
|
||||
(IdmacDesc + Idx)->Des2 = (UINT32)((UINTN)Buffer + DWEMMC_DMA_BUF_SIZE * Idx);
|
||||
/* Next Descriptor Address */
|
||||
(IdmacDesc + Idx)->Des3 = (UINT32)((UINTN)IdmacDesc +
|
||||
(sizeof(DWEMMC_IDMAC_DESCRIPTOR) * (Idx + 1)));
|
||||
}
|
||||
/* First Descriptor */
|
||||
IdmacDesc->Des0 |= DWEMMC_IDMAC_DES0_FS;
|
||||
/* Last Descriptor */
|
||||
LastIdx = Cnt - 1;
|
||||
(IdmacDesc + LastIdx)->Des0 |= DWEMMC_IDMAC_DES0_LD;
|
||||
(IdmacDesc + LastIdx)->Des0 &= ~(DWEMMC_IDMAC_DES0_DIC | DWEMMC_IDMAC_DES0_CH);
|
||||
(IdmacDesc + LastIdx)->Des1 = DWEMMC_IDMAC_DES1_BS1(Length -
|
||||
(LastIdx * DWEMMC_DMA_BUF_SIZE));
|
||||
/* Set the Next field of Last Descriptor */
|
||||
(IdmacDesc + LastIdx)->Des3 = 0;
|
||||
MmioWrite32 (DWEMMC_DBADDR, (UINT32)((UINTN)IdmacDesc));
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
VOID
|
||||
StartDma (
|
||||
UINTN Length
|
||||
)
|
||||
{
|
||||
UINT32 Data;
|
||||
|
||||
Data = MmioRead32 (DWEMMC_CTRL);
|
||||
Data |= DWEMMC_CTRL_INT_EN | DWEMMC_CTRL_DMA_EN | DWEMMC_CTRL_IDMAC_EN;
|
||||
MmioWrite32 (DWEMMC_CTRL, Data);
|
||||
Data = MmioRead32 (DWEMMC_BMOD);
|
||||
Data |= DWEMMC_IDMAC_ENABLE | DWEMMC_IDMAC_FB;
|
||||
MmioWrite32 (DWEMMC_BMOD, Data);
|
||||
|
||||
MmioWrite32 (DWEMMC_BLKSIZ, DWEMMC_BLOCK_SIZE);
|
||||
MmioWrite32 (DWEMMC_BYTCNT, Length);
|
||||
}
|
||||
|
||||
EFI_STATUS
|
||||
DwEmmcReadBlockData (
|
||||
IN EFI_MMC_HOST_PROTOCOL *This,
|
||||
IN EFI_LBA Lba,
|
||||
IN UINTN Length,
|
||||
IN UINT32* Buffer
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
UINT32 DescPages, CountPerPage, Count;
|
||||
EFI_TPL Tpl;
|
||||
|
||||
Tpl = gBS->RaiseTPL (TPL_NOTIFY);
|
||||
|
||||
CountPerPage = EFI_PAGE_SIZE / 16;
|
||||
Count = (Length + DWEMMC_DMA_BUF_SIZE - 1) / DWEMMC_DMA_BUF_SIZE;
|
||||
DescPages = (Count + CountPerPage - 1) / CountPerPage;
|
||||
|
||||
InvalidateDataCacheRange (Buffer, Length);
|
||||
|
||||
Status = PrepareDmaData (gpIdmacDesc, Length, Buffer);
|
||||
if (EFI_ERROR (Status)) {
|
||||
goto out;
|
||||
}
|
||||
|
||||
WriteBackDataCacheRange (gpIdmacDesc, DescPages * EFI_PAGE_SIZE);
|
||||
StartDma (Length);
|
||||
|
||||
Status = SendCommand (mDwEmmcCommand, mDwEmmcArgument);
|
||||
if (EFI_ERROR (Status)) {
|
||||
DEBUG ((DEBUG_ERROR, "Failed to read data, mDwEmmcCommand:%x, mDwEmmcArgument:%x, Status:%r\n", mDwEmmcCommand, mDwEmmcArgument, Status));
|
||||
goto out;
|
||||
}
|
||||
out:
|
||||
// Restore Tpl
|
||||
gBS->RestoreTPL (Tpl);
|
||||
return Status;
|
||||
}
|
||||
|
||||
EFI_STATUS
|
||||
DwEmmcWriteBlockData (
|
||||
IN EFI_MMC_HOST_PROTOCOL *This,
|
||||
IN EFI_LBA Lba,
|
||||
IN UINTN Length,
|
||||
IN UINT32* Buffer
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
UINT32 DescPages, CountPerPage, Count;
|
||||
EFI_TPL Tpl;
|
||||
|
||||
Tpl = gBS->RaiseTPL (TPL_NOTIFY);
|
||||
|
||||
CountPerPage = EFI_PAGE_SIZE / 16;
|
||||
Count = (Length + DWEMMC_DMA_BUF_SIZE - 1) / DWEMMC_DMA_BUF_SIZE;
|
||||
DescPages = (Count + CountPerPage - 1) / CountPerPage;
|
||||
|
||||
WriteBackDataCacheRange (Buffer, Length);
|
||||
|
||||
Status = PrepareDmaData (gpIdmacDesc, Length, Buffer);
|
||||
if (EFI_ERROR (Status)) {
|
||||
goto out;
|
||||
}
|
||||
|
||||
WriteBackDataCacheRange (gpIdmacDesc, DescPages * EFI_PAGE_SIZE);
|
||||
StartDma (Length);
|
||||
|
||||
Status = SendCommand (mDwEmmcCommand, mDwEmmcArgument);
|
||||
if (EFI_ERROR (Status)) {
|
||||
DEBUG ((DEBUG_ERROR, "Failed to write data, mDwEmmcCommand:%x, mDwEmmcArgument:%x, Status:%r\n", mDwEmmcCommand, mDwEmmcArgument, Status));
|
||||
goto out;
|
||||
}
|
||||
out:
|
||||
// Restore Tpl
|
||||
gBS->RestoreTPL (Tpl);
|
||||
return Status;
|
||||
}
|
||||
|
||||
EFI_STATUS
|
||||
DwEmmcSetIos (
|
||||
IN EFI_MMC_HOST_PROTOCOL *This,
|
||||
IN UINT32 BusClockFreq,
|
||||
IN UINT32 BusWidth,
|
||||
IN UINT32 TimingMode
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status = EFI_SUCCESS;
|
||||
UINT32 Data;
|
||||
|
||||
if ((PcdGet32 (PcdDwEmmcDxeMaxClockFreqInHz) != 0) &&
|
||||
(BusClockFreq > PcdGet32 (PcdDwEmmcDxeMaxClockFreqInHz))) {
|
||||
return EFI_UNSUPPORTED;
|
||||
}
|
||||
if (TimingMode != EMMCBACKWARD) {
|
||||
Data = MmioRead32 (DWEMMC_UHSREG);
|
||||
switch (TimingMode) {
|
||||
case EMMCHS52DDR1V2:
|
||||
case EMMCHS52DDR1V8:
|
||||
Data |= 1 << 16;
|
||||
break;
|
||||
case EMMCHS52:
|
||||
case EMMCHS26:
|
||||
Data &= ~(1 << 16);
|
||||
break;
|
||||
default:
|
||||
return EFI_UNSUPPORTED;
|
||||
}
|
||||
MmioWrite32 (DWEMMC_UHSREG, Data);
|
||||
}
|
||||
|
||||
switch (BusWidth) {
|
||||
case 1:
|
||||
MmioWrite32 (DWEMMC_CTYPE, 0);
|
||||
break;
|
||||
case 4:
|
||||
MmioWrite32 (DWEMMC_CTYPE, 1);
|
||||
break;
|
||||
case 8:
|
||||
MmioWrite32 (DWEMMC_CTYPE, 1 << 16);
|
||||
break;
|
||||
default:
|
||||
return EFI_UNSUPPORTED;
|
||||
}
|
||||
if (BusClockFreq) {
|
||||
Status = DwEmmcSetClock (BusClockFreq);
|
||||
}
|
||||
return Status;
|
||||
}
|
||||
|
||||
BOOLEAN
|
||||
DwEmmcIsMultiBlock (
|
||||
IN EFI_MMC_HOST_PROTOCOL *This
|
||||
)
|
||||
{
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
EFI_MMC_HOST_PROTOCOL gMciHost = {
|
||||
MMC_HOST_PROTOCOL_REVISION,
|
||||
DwEmmcIsCardPresent,
|
||||
DwEmmcIsReadOnly,
|
||||
DwEmmcBuildDevicePath,
|
||||
DwEmmcNotifyState,
|
||||
DwEmmcSendCommand,
|
||||
DwEmmcReceiveResponse,
|
||||
DwEmmcReadBlockData,
|
||||
DwEmmcWriteBlockData,
|
||||
DwEmmcSetIos,
|
||||
DwEmmcIsMultiBlock
|
||||
};
|
||||
|
||||
EFI_STATUS
|
||||
DwEmmcDxeInitialize (
|
||||
IN EFI_HANDLE ImageHandle,
|
||||
IN EFI_SYSTEM_TABLE *SystemTable
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
EFI_HANDLE Handle;
|
||||
|
||||
Handle = NULL;
|
||||
|
||||
DwEmmcAdjustFifoThreshold ();
|
||||
gpIdmacDesc = (DWEMMC_IDMAC_DESCRIPTOR *)AllocatePages (DWEMMC_MAX_DESC_PAGES);
|
||||
if (gpIdmacDesc == NULL) {
|
||||
return EFI_BUFFER_TOO_SMALL;
|
||||
}
|
||||
|
||||
DEBUG ((DEBUG_BLKIO, "DwEmmcDxeInitialize()\n"));
|
||||
|
||||
//Publish Component Name, BlockIO protocol interfaces
|
||||
Status = gBS->InstallMultipleProtocolInterfaces (
|
||||
&Handle,
|
||||
&gEmbeddedMmcHostProtocolGuid, &gMciHost,
|
||||
NULL
|
||||
);
|
||||
ASSERT_EFI_ERROR (Status);
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
|
@ -1,49 +0,0 @@
|
|||
#/** @file
|
||||
# INF file for the eMMC Host Protocol implementation for the DesignWare MMC.
|
||||
#
|
||||
# Copyright (c) 2014-2017, Linaro Limited. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||
#
|
||||
#**/
|
||||
|
||||
[Defines]
|
||||
INF_VERSION = 0x00010019
|
||||
BASE_NAME = DwEmmcDxe
|
||||
FILE_GUID = b549f005-4bd4-4020-a0cb-06f42bda68c3
|
||||
MODULE_TYPE = DXE_DRIVER
|
||||
VERSION_STRING = 1.0
|
||||
|
||||
ENTRY_POINT = DwEmmcDxeInitialize
|
||||
|
||||
[Sources.common]
|
||||
DwEmmcDxe.c
|
||||
|
||||
[Packages]
|
||||
EmbeddedPkg/EmbeddedPkg.dec
|
||||
MdePkg/MdePkg.dec
|
||||
|
||||
[LibraryClasses]
|
||||
ArmLib
|
||||
BaseLib
|
||||
BaseMemoryLib
|
||||
CacheMaintenanceLib
|
||||
IoLib
|
||||
MemoryAllocationLib
|
||||
TimerLib
|
||||
UefiDriverEntryPoint
|
||||
UefiLib
|
||||
|
||||
[Protocols]
|
||||
gEfiCpuArchProtocolGuid
|
||||
gEfiDevicePathProtocolGuid
|
||||
gEmbeddedMmcHostProtocolGuid
|
||||
|
||||
[Pcd]
|
||||
gEmbeddedTokenSpaceGuid.PcdDwEmmcDxeBaseAddress
|
||||
gEmbeddedTokenSpaceGuid.PcdDwEmmcDxeClockFrequencyInHz
|
||||
gEmbeddedTokenSpaceGuid.PcdDwEmmcDxeMaxClockFreqInHz
|
||||
gEmbeddedTokenSpaceGuid.PcdDwEmmcDxeFifoDepth
|
||||
|
||||
[Depex]
|
||||
TRUE
|
||||
|
|
@ -144,12 +144,6 @@
|
|||
# LAN91x Ethernet Driver PCDs
|
||||
gEmbeddedTokenSpaceGuid.PcdLan91xDxeBaseAddress|0x0|UINT32|0x00000029
|
||||
|
||||
# DwEmmc Driver PCDs
|
||||
gEmbeddedTokenSpaceGuid.PcdDwEmmcDxeBaseAddress|0x0|UINT32|0x00000035
|
||||
gEmbeddedTokenSpaceGuid.PcdDwEmmcDxeClockFrequencyInHz|0x0|UINT32|0x00000036
|
||||
gEmbeddedTokenSpaceGuid.PcdDwEmmcDxeMaxClockFreqInHz|0x0|UINT32|0x00000037
|
||||
gEmbeddedTokenSpaceGuid.PcdDwEmmcDxeFifoDepth|0x0|UINT32|0x00000038
|
||||
|
||||
#
|
||||
# Android FastBoot
|
||||
#
|
||||
|
|
|
|||
Loading…
Reference in New Issue