mirror of https://github.com/acidanthera/audk.git
ArmPlatformPkg/ArmRealViewEb: Add support for PL111 Lcd controller
- Add the LcdGraphicsOutputDxe driver to DSC and FDF file. - Implement LcdPlatformLib for the platform. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11787 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin
parent
7d0f2f23d2
commit
9bc6ef0231
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@ -114,6 +114,7 @@
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BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf
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NorFlashPlatformLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/NorFlashArmRealViewEbLib/NorFlashArmRealViewEbLib.inf
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LcdPlatformLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/PL111LcdArmRealViewEbLib/PL111LcdArmRealViewEbLib.inf
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[LibraryClasses.common.SEC]
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ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf
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@ -448,6 +449,7 @@
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EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
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EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
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ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf
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ArmPlatformPkg/ArmRealViewEbPkg/FvbDxe/FvbDxe.inf
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ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf
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@ -115,6 +115,7 @@
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BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf
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NorFlashPlatformLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/NorFlashArmRealViewEbLib/NorFlashArmRealViewEbLib.inf
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LcdPlatformLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/PL111LcdArmRealViewEbLib/PL111LcdArmRealViewEbLib.inf
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[LibraryClasses.common.SEC]
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ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLibSec.inf
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@ -459,6 +460,7 @@
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EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
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EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
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ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf
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ArmPlatformPkg/ArmRealViewEbPkg/FvbDxe/FvbDxe.inf
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ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf
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@ -125,6 +125,8 @@ READ_LOCK_STATUS = TRUE
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INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
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INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
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INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
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INF ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf
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INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
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@ -125,6 +125,8 @@ READ_LOCK_STATUS = TRUE
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INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
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INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
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INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
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INF ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf
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INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
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@ -21,79 +21,85 @@
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*******************************************/
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// Can be NOR, DOC, DRAM, SRAM
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#define ARM_EB_REMAP_BASE 0x00000000
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#define ARM_EB_REMAP_SZ 0x04000000
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#define ARM_EB_REMAP_BASE 0x00000000
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#define ARM_EB_REMAP_SZ 0x04000000
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// Motherboard Peripheral and On-chip peripheral
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#define ARM_EB_SMB_MB_ON_CHIP_PERIPH_BASE 0x10000000
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#define ARM_EB_SMB_MB_ON_CHIP_PERIPH_SZ 0x00100000
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#define ARM_EB_BOARD_PERIPH_BASE 0x10000000
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//#define ARM_EB_CHIP_PERIPH_BASE 0x10020000
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#define ARM_EB_SMB_MB_ON_CHIP_PERIPH_BASE 0x10000000
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#define ARM_EB_SMB_MB_ON_CHIP_PERIPH_SZ 0x00100000
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#define ARM_EB_BOARD_PERIPH_BASE 0x10000000
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//#define ARM_EB_CHIP_PERIPH_BASE 0x10020000
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// SMC
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#define ARM_EB_SMC_BASE 0x40000000
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#define ARM_EB_SMC_SZ 0x20000000
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#define ARM_EB_SMC_BASE 0x40000000
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#define ARM_EB_SMC_SZ 0x20000000
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// NOR Flash 1
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#define ARM_EB_SMB_NOR_BASE 0x40000000
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#define ARM_EB_SMB_NOR_SZ 0x04000000 /* 64 MB */
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#define ARM_EB_SMB_NOR_BASE 0x40000000
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#define ARM_EB_SMB_NOR_SZ 0x04000000 /* 64 MB */
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// DOC Flash
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#define ARM_EB_SMB_DOC_BASE 0x44000000
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#define ARM_EB_SMB_DOC_SZ 0x04000000 /* 64 MB */
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#define ARM_EB_SMB_DOC_BASE 0x44000000
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#define ARM_EB_SMB_DOC_SZ 0x04000000 /* 64 MB */
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// SRAM
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#define ARM_EB_SMB_SRAM_BASE 0x48000000
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#define ARM_EB_SMB_SRAM_SZ 0x02000000 /* 32 MB */
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#define ARM_EB_SMB_SRAM_BASE 0x48000000
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#define ARM_EB_SMB_SRAM_SZ 0x02000000 /* 32 MB */
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// USB, Ethernet, VRAM
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#define ARM_EB_SMB_PERIPH_BASE 0x4E000000
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//#define ARM_EB_SMB_PERIPH_VRAM 0x4C000000
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#define ARM_EB_SMB_PERIPH_SZ 0x02000000 /* 32 MB */
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#define ARM_EB_SMB_PERIPH_BASE 0x4E000000
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//#define ARM_EB_SMB_PERIPH_VRAM 0x4C000000
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#define ARM_EB_SMB_PERIPH_SZ 0x02000000 /* 32 MB */
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// DRAM
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#define ARM_EB_DRAM_BASE 0x70000000
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#define ARM_EB_DRAM_SZ 0x10000000
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#define ARM_EB_DRAM_BASE 0x70000000
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#define ARM_EB_DRAM_SZ 0x10000000
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// Logic Tile
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#define ARM_EB_LOGIC_TILE_BASE 0xC0000000
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#define ARM_EB_LOGIC_TILE_SZ 0x40000000
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#define ARM_EB_LOGIC_TILE_BASE 0xC0000000
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#define ARM_EB_LOGIC_TILE_SZ 0x40000000
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/*******************************************
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// Motherboard peripherals
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*******************************************/
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// Define MotherBoard SYS flags offsets (from ARM_EB_BOARD_PERIPH_BASE)
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#define ARM_EB_SYS_FLAGS_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00030)
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#define ARM_EB_SYS_FLAGS_SET_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00030)
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#define ARM_EB_SYS_FLAGS_CLR_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00034)
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#define ARM_EB_SYS_FLAGS_NV_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00038)
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#define ARM_EB_SYS_FLAGS_NV_SET_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00038)
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#define ARM_EB_SYS_FLAGS_NV_CLR_REG (ARM_EB_BOARD_PERIPH_BASE + 0x0003C)
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#define ARM_EB_SYS_PROCID0_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00084)
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#define ARM_EB_SYS_PROCID1_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00088)
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#define ARM_EB_SYS_CFGDATA_REG (ARM_EB_BOARD_PERIPH_BASE + 0x000A0)
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#define ARM_EB_SYS_CFGCTRL_REG (ARM_EB_BOARD_PERIPH_BASE + 0x000A4)
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#define ARM_EB_SYS_CFGSTAT_REG (ARM_EB_BOARD_PERIPH_BASE + 0x000A8)
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#define ARM_EB_SYS_OSC4_REG (ARM_EB_BOARD_PERIPH_BASE + 0x0001C)
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#define ARM_EB_SYS_LOCK_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00020)
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#define ARM_EB_SYS_100HZ_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00024)
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#define ARM_EB_SYS_FLAGS_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00030)
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#define ARM_EB_SYS_FLAGS_SET_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00030)
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#define ARM_EB_SYS_FLAGS_CLR_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00034)
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#define ARM_EB_SYS_FLAGS_NV_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00038)
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#define ARM_EB_SYS_FLAGS_NV_SET_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00038)
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#define ARM_EB_SYS_FLAGS_NV_CLR_REG (ARM_EB_BOARD_PERIPH_BASE + 0x0003C)
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#define ARM_EB_SYS_CLCD_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00050)
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#define ARM_EB_SYS_PROCID0_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00084)
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#define ARM_EB_SYS_PROCID1_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00088)
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#define ARM_EB_SYS_CFGDATA_REG (ARM_EB_BOARD_PERIPH_BASE + 0x000A0)
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#define ARM_EB_SYS_CFGCTRL_REG (ARM_EB_BOARD_PERIPH_BASE + 0x000A4)
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#define ARM_EB_SYS_CFGSTAT_REG (ARM_EB_BOARD_PERIPH_BASE + 0x000A8)
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// SP810 Controller
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#define SP810_CTRL_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x01000)
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#define SP810_CTRL_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x01000)
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// SYSTRCL Register
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#define ARM_EB_SYSCTRL 0x10001000
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#define ARM_EB_SYSCTRL 0x10001000
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// Uart0
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#define PL011_CONSOLE_UART_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x09000)
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#define PL011_CONSOLE_UART_SPEED 115200
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#define PL011_CONSOLE_UART_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x09000)
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// SP804 Timer Bases
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#define SP804_TIMER0_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x11000)
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#define SP804_TIMER1_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x11020)
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#define SP804_TIMER2_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x12000)
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#define SP804_TIMER3_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x12020)
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#define SP804_TIMER0_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x11000)
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#define SP804_TIMER1_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x11020)
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#define SP804_TIMER2_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x12000)
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#define SP804_TIMER3_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x12020)
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// Dynamic Memory Controller Base
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#define ARM_EB_DMC_BASE 0x10018000
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// Static Memory Controller Base
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#define ARM_EB_SMC_CTRL_BASE 0x10080000
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#define PL111_CLCD_BASE 0x10020000
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//Note: Moving the framebuffer into the 0x70000000-0x80000000 region does not seem to work
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#define PL111_CLCD_VRAM_BASE 0x00100000
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/*// System Configuration Controller register Base addresses
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//#define ARM_EB_SYS_CFG_CTRL_BASE 0x100E2000
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@ -0,0 +1,209 @@
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/** @file
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Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include <PiDxe.h>
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#include <Library/LcdPlatformLib.h>
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#include <Library/IoLib.h>
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#include <Library/DebugLib.h>
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#include <Drivers/PL111Lcd.h>
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#include <ArmPlatform.h>
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typedef struct {
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UINT32 Mode;
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UINT32 HorizontalResolution;
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UINT32 VerticalResolution;
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LCD_BPP Bpp;
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UINT32 ClcdClk;
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UINT32 HSync;
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UINT32 HBackPorch;
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UINT32 HFrontPorch;
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UINT32 VSync;
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UINT32 VBackPorch;
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UINT32 VFrontPorch;
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} CLCD_RESOLUTION;
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CLCD_RESOLUTION mResolutions[] = {
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{ // Mode 0 : VGA : 640 x 480 x 24 bpp
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VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, 0x2C77,
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VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH,
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VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH
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},
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{ // Mode 1 : SVGA : 800 x 600 x 24 bpp
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SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, 0x2CAC,
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SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH,
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SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH
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}
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};
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EFI_STATUS
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LcdPlatformInitializeDisplay (
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VOID
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)
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{
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MmioWrite32(ARM_EB_SYS_CLCD_REG, 1);
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return EFI_SUCCESS;
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}
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EFI_STATUS
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LcdPlatformGetVram (
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OUT EFI_PHYSICAL_ADDRESS* VramBaseAddress,
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OUT UINTN* VramSize
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)
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{
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*VramBaseAddress = PL111_CLCD_VRAM_BASE;
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*VramSize = SIZE_8MB; //FIXME: Can this size change ?
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return EFI_SUCCESS;
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}
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UINT32
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LcdPlatformGetMaxMode (
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VOID
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)
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{
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return (sizeof(mResolutions) / sizeof(CLCD_RESOLUTION));
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}
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EFI_STATUS
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LcdPlatformSetMode (
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IN UINT32 ModeNumber
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)
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{
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if (ModeNumber >= LcdPlatformGetMaxMode ()) {
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return EFI_INVALID_PARAMETER;
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}
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MmioWrite32(ARM_EB_SYS_LOCK_REG,0x0000A05F);
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MmioWrite32(ARM_EB_SYS_OSC4_REG,mResolutions[ModeNumber].ClcdClk);
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MmioWrite32(ARM_EB_SYS_LOCK_REG,0x0);
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return EFI_SUCCESS;
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}
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EFI_STATUS
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LcdPlatformQueryMode (
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IN UINT32 ModeNumber,
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OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *Info
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)
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{
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EFI_STATUS Status;
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if (ModeNumber >= LcdPlatformGetMaxMode ()) {
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return EFI_INVALID_PARAMETER;
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}
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Status = EFI_UNSUPPORTED;
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Info->Version = 0;
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Info->HorizontalResolution = mResolutions[ModeNumber].HorizontalResolution;
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Info->VerticalResolution = mResolutions[ModeNumber].VerticalResolution;
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Info->PixelsPerScanLine = mResolutions[ModeNumber].HorizontalResolution;
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switch (mResolutions[ModeNumber].Bpp) {
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case LCD_BITS_PER_PIXEL_24:
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Info->PixelFormat = PixelRedGreenBlueReserved8BitPerColor;
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Info->PixelInformation.RedMask = LCD_24BPP_RED_MASK;
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Info->PixelInformation.GreenMask = LCD_24BPP_GREEN_MASK;
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Info->PixelInformation.BlueMask = LCD_24BPP_BLUE_MASK;
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Info->PixelInformation.ReservedMask = LCD_24BPP_RESERVED_MASK;
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Status = EFI_SUCCESS;
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break;
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case LCD_BITS_PER_PIXEL_16_555:
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Info->PixelFormat = PixelBitMask;
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Info->PixelInformation.RedMask = LCD_16BPP_555_RED_MASK;
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Info->PixelInformation.GreenMask = LCD_16BPP_555_GREEN_MASK;
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Info->PixelInformation.BlueMask = LCD_16BPP_555_BLUE_MASK;
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Info->PixelInformation.ReservedMask = LCD_16BPP_555_RESERVED_MASK;
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Status = EFI_SUCCESS;
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break;
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case LCD_BITS_PER_PIXEL_16_565:
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Info->PixelFormat = PixelBitMask;
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Info->PixelInformation.RedMask = LCD_16BPP_565_RED_MASK;
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Info->PixelInformation.GreenMask = LCD_16BPP_565_GREEN_MASK;
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Info->PixelInformation.BlueMask = LCD_16BPP_565_BLUE_MASK;
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Info->PixelInformation.ReservedMask = LCD_16BPP_565_RESERVED_MASK;
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Status = EFI_SUCCESS;
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break;
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case LCD_BITS_PER_PIXEL_12_444:
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Info->PixelFormat = PixelBitMask;
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Info->PixelInformation.RedMask = LCD_12BPP_444_RED_MASK;
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Info->PixelInformation.GreenMask = LCD_12BPP_444_GREEN_MASK;
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Info->PixelInformation.BlueMask = LCD_12BPP_444_BLUE_MASK;
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Info->PixelInformation.ReservedMask = LCD_12BPP_444_RESERVED_MASK;
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Status = EFI_SUCCESS;
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break;
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case LCD_BITS_PER_PIXEL_8:
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case LCD_BITS_PER_PIXEL_4:
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case LCD_BITS_PER_PIXEL_2:
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case LCD_BITS_PER_PIXEL_1:
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default:
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// These are not supported
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break;
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}
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return Status;
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}
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EFI_STATUS
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LcdPlatformGetTimings (
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IN UINT32 ModeNumber,
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OUT UINT32* HRes,
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OUT UINT32* HSync,
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OUT UINT32* HBackPorch,
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OUT UINT32* HFrontPorch,
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OUT UINT32* VRes,
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OUT UINT32* VSync,
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OUT UINT32* VBackPorch,
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OUT UINT32* VFrontPorch
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)
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{
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if (ModeNumber >= LcdPlatformGetMaxMode ()) {
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return EFI_INVALID_PARAMETER;
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}
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*HRes = mResolutions[ModeNumber].HorizontalResolution;
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*HSync = mResolutions[ModeNumber].HSync;
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*HBackPorch = mResolutions[ModeNumber].HBackPorch;
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*HFrontPorch = mResolutions[ModeNumber].HFrontPorch;
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*VRes = mResolutions[ModeNumber].VerticalResolution;
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*VSync = mResolutions[ModeNumber].VSync;
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*VBackPorch = mResolutions[ModeNumber].VBackPorch;
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*VFrontPorch = mResolutions[ModeNumber].VFrontPorch;
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|
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return EFI_SUCCESS;
|
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}
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|
||||
EFI_STATUS
|
||||
LcdPlatformGetBpp (
|
||||
IN UINT32 ModeNumber,
|
||||
OUT LCD_BPP * Bpp
|
||||
)
|
||||
{
|
||||
if (ModeNumber >= LcdPlatformGetMaxMode ()) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
*Bpp = mResolutions[ModeNumber].Bpp;
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
#/** @file
|
||||
#
|
||||
# Component discription file for ArmVeGraphicsDxe module
|
||||
#
|
||||
# Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>
|
||||
# This program and the accompanying materials
|
||||
# are licensed and made available under the terms and conditions of the BSD License
|
||||
# which accompanies this distribution. The full text of the license may be found at
|
||||
# http://opensource.org/licenses/bsd-license.php
|
||||
#
|
||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
#
|
||||
#**/
|
||||
|
||||
[Defines]
|
||||
INF_VERSION = 0x00010005
|
||||
BASE_NAME = PL111LcdArmRealViewEbLib
|
||||
FILE_GUID = 51396ee0-4973-11e0-868a-0002a5d5c51b
|
||||
MODULE_TYPE = DXE_DRIVER
|
||||
VERSION_STRING = 1.0
|
||||
LIBRARY_CLASS = PL111LcdPlatformLib
|
||||
|
||||
[Sources.common]
|
||||
PL111LcdArmRealViewEb.c
|
||||
|
||||
[Packages]
|
||||
MdePkg/MdePkg.dec
|
||||
ArmPlatformPkg/ArmPlatformPkg.dec
|
||||
|
||||
[LibraryClasses]
|
||||
BaseLib
|
||||
DebugLib
|
||||
IoLib
|
||||
|
||||
[Guids]
|
||||
|
||||
[Protocols]
|
||||
|
||||
[FixedPcd.common]
|
||||
|
||||
#
|
||||
# The following modes are supported by PL111
|
||||
#
|
||||
# 0 : 640 x 480 x 24 bpp
|
||||
# 1 : 800 x 600 x 24 bpp
|
||||
# 2 : 1024 x 768 x 24 bpp
|
||||
# 3 : 640 x 480 x 16 bpp (565 RGB Mode)
|
||||
# 4 : 800 x 600 x 16 bpp (565 RGB Mode)
|
||||
# 5 : 1024 x 768 x 16 bpp (565 RGB Mode)
|
||||
# 6 : 640 x 480 x 15 bpp (555 RGB Mode)
|
||||
# 7 : 800 x 600 x 15 bpp (555 RGB Mode)
|
||||
# 8 : 1024 x 768 x 15 bpp (555 RGB Mode)
|
||||
# 9 : 1024 x 768 x 15 bpp (555 RGB Mode) - Linux driver settings
|
||||
# 10 : 640 x 480 x 12 bpp (444 RGB Mode)
|
||||
# 11 : 800 x 600 x 12 bpp (444 RGB Mode)
|
||||
# 12 : 1024 x 768 x 12 bpp (444 RGB Mode)
|
||||
#
|
||||
|
||||
[Pcd.common]
|
||||
|
||||
[Depex]
|
||||
# gEfiCpuArchProtocolGuid
|
||||
Loading…
Reference in New Issue