mirror of https://github.com/acidanthera/audk.git
1. Save/restore ICR high 32bit value and check Delivery Status before sending IPI. It could be fix the interrupted issue between ICR high/low writes by SMI handler.
2. Save/restore CPU Interrupt state around sending IPI. It could avoid sending IPI be interrupted by CPU interrupt handler. 3. Add note for SetApicMode() API that must not be called from an interrupt handler or SMI handler. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Kinney, Michael <michael.d.kinney@intel.com> Reviewed-by: Mudusuru, Giri <giri.p.mudusuru@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15652 6f19259b-4bc3-4df7-8a09-765794883524
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Jeff Fan
vanjeff
parent
d2ea3b8399
commit
9c71e1e056
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@ -4,7 +4,7 @@
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Local APIC library assumes local APIC is enabled. It does not
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handles cases where local APIC is disabled.
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Copyright (c) 2010 - 2013, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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@ -68,6 +68,9 @@ GetApicMode (
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If the specified local APIC mode can't be set as current, then ASSERT.
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@param ApicMode APIC mode to be set.
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@note This API must not be called from an interrupt handler or SMI handler.
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It may result in unpredictable behavior.
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**/
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VOID
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EFIAPI
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@ -139,18 +139,47 @@ SendIpi (
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)
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{
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LOCAL_APIC_ICR_LOW IcrLowReg;
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UINT32 IcrHigh;
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BOOLEAN InterruptState;
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ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
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ASSERT (ApicId <= 0xff);
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InterruptState = SaveAndDisableInterrupts ();
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//
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// Save existing contents of ICR high 32 bits
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//
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IcrHigh = ReadLocalApicReg (XAPIC_ICR_HIGH_OFFSET);
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//
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// Wait for DeliveryStatus clear in case a previous IPI
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// is still being sent
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//
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do {
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IcrLowReg.Uint32 = ReadLocalApicReg (XAPIC_ICR_LOW_OFFSET);
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} while (IcrLowReg.Bits.DeliveryStatus != 0);
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//
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// For xAPIC, the act of writing to the low doubleword of the ICR causes the IPI to be sent.
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//
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WriteLocalApicReg (XAPIC_ICR_HIGH_OFFSET, ApicId << 24);
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WriteLocalApicReg (XAPIC_ICR_LOW_OFFSET, IcrLow);
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//
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// Wait for DeliveryStatus clear again
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//
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do {
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IcrLowReg.Uint32 = ReadLocalApicReg (XAPIC_ICR_LOW_OFFSET);
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} while (IcrLowReg.Bits.DeliveryStatus != 0);
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//
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// And restore old contents of ICR high
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//
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WriteLocalApicReg (XAPIC_ICR_HIGH_OFFSET, IcrHigh);
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SetInterruptState (InterruptState);
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}
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//
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@ -193,6 +222,9 @@ GetApicMode (
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If the specified local APIC mode can't be set as current, then ASSERT.
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@param ApicMode APIC mode to be set.
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@note This API must not be called from an interrupt handler or SMI handler.
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It may result in unpredictable behavior.
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**/
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VOID
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EFIAPI
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@ -180,19 +180,55 @@ SendIpi (
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UINT64 MsrValue;
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LOCAL_APIC_ICR_LOW IcrLowReg;
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UINTN LocalApciBaseAddress;
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UINT32 IcrHigh;
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BOOLEAN InterruptState;
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//
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// Legacy APIC or X2APIC?
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//
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if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {
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ASSERT (ApicId <= 0xff);
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InterruptState = SaveAndDisableInterrupts ();
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//
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// Get base address of this LAPIC
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//
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LocalApciBaseAddress = GetLocalApicBaseAddress();
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//
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// Save existing contents of ICR high 32 bits
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//
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IcrHigh = MmioRead32 (LocalApciBaseAddress + XAPIC_ICR_HIGH_OFFSET);
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//
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// Wait for DeliveryStatus clear in case a previous IPI
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// is still being sent
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//
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do {
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IcrLowReg.Uint32 = MmioRead32 (LocalApciBaseAddress + XAPIC_ICR_LOW_OFFSET);
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} while (IcrLowReg.Bits.DeliveryStatus != 0);
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//
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// For xAPIC, the act of writing to the low doubleword of the ICR causes the IPI to be sent.
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//
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LocalApciBaseAddress = GetLocalApicBaseAddress();
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MmioWrite32 (LocalApciBaseAddress + XAPIC_ICR_HIGH_OFFSET, ApicId << 24);
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MmioWrite32 (LocalApciBaseAddress + XAPIC_ICR_LOW_OFFSET, IcrLow);
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//
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// Wait for DeliveryStatus clear again
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//
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do {
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IcrLowReg.Uint32 = MmioRead32 (LocalApciBaseAddress + XAPIC_ICR_LOW_OFFSET);
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} while (IcrLowReg.Bits.DeliveryStatus != 0);
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//
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// And restore old contents of ICR high
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//
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MmioWrite32 (LocalApciBaseAddress + XAPIC_ICR_HIGH_OFFSET, IcrHigh);
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SetInterruptState (InterruptState);
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} else {
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//
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// For x2APIC, A single MSR write to the Interrupt Command Register is required for dispatching an
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@ -242,6 +278,9 @@ GetApicMode (
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If the specified local APIC mode can't be set as current, then ASSERT.
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@param ApicMode APIC mode to be set.
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@note This API must not be called from an interrupt handler or SMI handler.
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It may result in unpredictable behavior.
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**/
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VOID
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EFIAPI
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