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CpuPageTableLib: Split the page entry when LA is aligned but PA is not 

When PageTableMap() is called to create non 1:1 mapping
such as [0, 1G) to [8K, 1G+8K), it should split the page entry to the
4K page level, but old logic has a bug that it just uses 1G page
entry.

The patch fixes the bug.

Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
This commit is contained in:
Ray Ni 2022-07-14 20:08:29 +08:00 committed by mergify[bot]
parent 13a0471bfd
commit 9cb8974f06
1 changed files with 6 additions and 1 deletions
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7
UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
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@ -360,7 +360,12 @@ PageTableLibMapInLevel (
PagingEntry = (IA32_PAGING_ENTRY *)(UINTN)IA32_PNLE_PAGE_TABLE_BASE_ADDRESS (&ParentPagingEntry->Pnle);
while (Offset < Length && Index < 512) {
SubLength = MIN (Length - Offset, RegionStart + RegionLength - (LinearAddress + Offset));
if ((Level <= MaxLeafLevel) && (((LinearAddress + Offset) & RegionMask) == 0) && (SubLength == RegionLength)) {
if ((Level <= MaxLeafLevel) &&
(((LinearAddress + Offset) & RegionMask) == 0) &&
(((IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (Attribute) + Offset) & RegionMask) == 0) &&
(SubLength == RegionLength)
)
{
//
// Create one entry mapping the entire region (1G, 2M or 4K).
//