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UefiCpuPkg/AcpiCpuData: Update RegisterTableEntry type 

Current RegisterTableEntry filed in CPU_REGISTER_TABLE is one pointer to
CPU_REGISTER_TABLE_ENTRY. If CPU register table wants to be passed from 32bit
PEI to x64 DXE/SMM, x64 DXE/SMM cannot get the correct RegisterTableEntry.

This update is to update RegisterTableEntry type to EFI_PHYSICAL_ADDRESS and
make RegisterTableEntry is fixed length.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
This commit is contained in:
Jeff Fan 2017-03-07 14:32:28 +08:00
parent 5920a9d16b
commit 9cc45009ba
3 changed files with 11 additions and 11 deletions
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6
UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c
View File

@ -9,7 +9,7 @@ number of CPUs reported by the MP Services Protocol, so this module does not
support hot plug CPUs. This module can be copied into a CPU specific package support hot plug CPUs. This module can be copied into a CPU specific package
and customized if these additional features are required. and customized if these additional features are required.
Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.<BR> Copyright (c) 2013 - 2017, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2015, Red Hat, Inc. Copyright (c) 2015, Red Hat, Inc.
This program and the accompanying materials This program and the accompanying materials
@ -246,12 +246,12 @@ CpuS3DataInitialize (
RegisterTable[Index].InitialApicId = (UINT32)ProcessorInfoBuffer.ProcessorId; RegisterTable[Index].InitialApicId = (UINT32)ProcessorInfoBuffer.ProcessorId;
RegisterTable[Index].TableLength = 0; RegisterTable[Index].TableLength = 0;
RegisterTable[Index].AllocatedSize = 0; RegisterTable[Index].AllocatedSize = 0;
RegisterTable[Index].RegisterTableEntry = NULL; RegisterTable[Index].RegisterTableEntry = 0;
RegisterTable[NumberOfCpus + Index].InitialApicId = (UINT32)ProcessorInfoBuffer.ProcessorId; RegisterTable[NumberOfCpus + Index].InitialApicId = (UINT32)ProcessorInfoBuffer.ProcessorId;
RegisterTable[NumberOfCpus + Index].TableLength = 0; RegisterTable[NumberOfCpus + Index].TableLength = 0;
RegisterTable[NumberOfCpus + Index].AllocatedSize = 0; RegisterTable[NumberOfCpus + Index].AllocatedSize = 0;
RegisterTable[NumberOfCpus + Index].RegisterTableEntry = NULL; RegisterTable[NumberOfCpus + Index].RegisterTableEntry = 0;
} }
AcpiCpuData->RegisterTable = (EFI_PHYSICAL_ADDRESS)(UINTN)RegisterTable; AcpiCpuData->RegisterTable = (EFI_PHYSICAL_ADDRESS)(UINTN)RegisterTable;
AcpiCpuData->PreSmmInitRegisterTable = (EFI_PHYSICAL_ADDRESS)(UINTN)(RegisterTable + NumberOfCpus); AcpiCpuData->PreSmmInitRegisterTable = (EFI_PHYSICAL_ADDRESS)(UINTN)(RegisterTable + NumberOfCpus);

6
UefiCpuPkg/Include/AcpiCpuData.h
View File

@ -1,7 +1,7 @@
/** @file /** @file
Definitions for CPU S3 data. Definitions for CPU S3 data.
Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR> Copyright (c) 2013 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at which accompanies this distribution. The full text of the license may be found at
@ -55,10 +55,10 @@ typedef struct {
// //
UINT32 InitialApicId; UINT32 InitialApicId;
// //
// Buffer of CPU_REGISTER_TABLE_ENTRY structures. This buffer must be // Physical address of CPU_REGISTER_TABLE_ENTRY structures. This buffer must be
// allocated below 4GB from memory of type EfiACPIMemoryNVS. // allocated below 4GB from memory of type EfiACPIMemoryNVS.
// //
CPU_REGISTER_TABLE_ENTRY *RegisterTableEntry; EFI_PHYSICAL_ADDRESS RegisterTableEntry;
} CPU_REGISTER_TABLE; } CPU_REGISTER_TABLE;
// //

10
UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
View File

@ -1,7 +1,7 @@
/** @file /** @file
Code for Processor S3 restoration Code for Processor S3 restoration
Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR> Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at which accompanies this distribution. The full text of the license may be found at
@ -826,13 +826,12 @@ CopyRegisterTable (
CopyMem (DestinationRegisterTableList, SourceRegisterTableList, NumberOfCpus * sizeof (CPU_REGISTER_TABLE)); CopyMem (DestinationRegisterTableList, SourceRegisterTableList, NumberOfCpus * sizeof (CPU_REGISTER_TABLE));
for (Index = 0; Index < NumberOfCpus; Index++) { for (Index = 0; Index < NumberOfCpus; Index++) {
DestinationRegisterTableList[Index].RegisterTableEntry = AllocatePool (DestinationRegisterTableList[Index].AllocatedSize); RegisterTableEntry = AllocatePool (DestinationRegisterTableList[Index].AllocatedSize);
ASSERT (DestinationRegisterTableList[Index].RegisterTableEntry != NULL); ASSERT (RegisterTableEntry != NULL);
CopyMem (DestinationRegisterTableList[Index].RegisterTableEntry, SourceRegisterTableList[Index].RegisterTableEntry, DestinationRegisterTableList[Index].AllocatedSize); CopyMem (RegisterTableEntry, (VOID *)(UINTN)SourceRegisterTableList[Index].RegisterTableEntry, DestinationRegisterTableList[Index].AllocatedSize);
// //
// Go though all MSRs in register table to initialize MSR spin lock // Go though all MSRs in register table to initialize MSR spin lock
// //
RegisterTableEntry = DestinationRegisterTableList[Index].RegisterTableEntry;
for (Index1 = 0; Index1 < DestinationRegisterTableList[Index].TableLength; Index1++, RegisterTableEntry++) { for (Index1 = 0; Index1 < DestinationRegisterTableList[Index].TableLength; Index1++, RegisterTableEntry++) {
if ((RegisterTableEntry->RegisterType == Msr) && (RegisterTableEntry->ValidBitLength < 64)) { if ((RegisterTableEntry->RegisterType == Msr) && (RegisterTableEntry->ValidBitLength < 64)) {
// //
@ -841,6 +840,7 @@ CopyRegisterTable (
InitMsrSpinLockByIndex (RegisterTableEntry->Index); InitMsrSpinLockByIndex (RegisterTableEntry->Index);
} }
} }
DestinationRegisterTableList[Index].RegisterTableEntry = (EFI_PHYSICAL_ADDRESS)(UINTN)RegisterTableEntry;
} }
} }