mirror of https://github.com/acidanthera/audk.git
ArmPkg/ArmCpuLib: Fixed SMP Cortex-A9 and Cortex-A15
Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13261 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
parent
e314d564db
commit
9d59a88be1
|
@ -20,7 +20,7 @@
|
||||||
#include <Library/IoLib.h>
|
#include <Library/IoLib.h>
|
||||||
#include <Library/PcdLib.h>
|
#include <Library/PcdLib.h>
|
||||||
|
|
||||||
#include <Chipset/ArmV7.h>
|
#include <Chipset/ArmCortexA15.h>
|
||||||
|
|
||||||
VOID
|
VOID
|
||||||
ArmCpuSetup (
|
ArmCpuSetup (
|
||||||
|
@ -41,10 +41,11 @@ ArmCpuSetup (
|
||||||
// if security extensions are implemented.
|
// if security extensions are implemented.
|
||||||
ArmArchTimerSetTimerFreq (PcdGet32 (PcdArmArchTimerFreqInHz));
|
ArmArchTimerSetTimerFreq (PcdGet32 (PcdArmArchTimerFreqInHz));
|
||||||
|
|
||||||
/*// If MPCore then Enable the SCU
|
|
||||||
if (ArmIsMpCore()) {
|
if (ArmIsMpCore()) {
|
||||||
ArmEnableScu ();
|
// Turn on SMP coherency
|
||||||
}*/
|
ArmSetAuxCrBit (A15_FEATURE_SMP);
|
||||||
|
}
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
@ -53,8 +54,6 @@ ArmCpuSetupSmpNonSecure (
|
||||||
IN UINTN MpId
|
IN UINTN MpId
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
//ArmSetAuxCrBit (A15_FEATURE_SMP);
|
|
||||||
|
|
||||||
/*// Make the SCU accessible in Non Secure world
|
/*// Make the SCU accessible in Non Secure world
|
||||||
if (IS_PRIMARY_CORE(MpId)) {
|
if (IS_PRIMARY_CORE(MpId)) {
|
||||||
ScuBase = ArmGetScuBaseAddress();
|
ScuBase = ArmGetScuBaseAddress();
|
||||||
|
|
|
@ -48,6 +48,9 @@ ArmCpuSetup (
|
||||||
|
|
||||||
// If MPCore then Enable the SCU
|
// If MPCore then Enable the SCU
|
||||||
if (ArmIsMpCore()) {
|
if (ArmIsMpCore()) {
|
||||||
|
// Signals the Cortex-A9 processor is taking part in coherency
|
||||||
|
ArmSetAuxCrBit (A9_FEATURE_SMP);
|
||||||
|
|
||||||
ArmEnableScu ();
|
ArmEnableScu ();
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -60,8 +63,6 @@ ArmCpuSetupSmpNonSecure (
|
||||||
{
|
{
|
||||||
INTN ScuBase;
|
INTN ScuBase;
|
||||||
|
|
||||||
ArmSetAuxCrBit (A9_FEATURE_SMP);
|
|
||||||
|
|
||||||
// Make the SCU accessible in Non Secure world
|
// Make the SCU accessible in Non Secure world
|
||||||
if (IS_PRIMARY_CORE(MpId)) {
|
if (IS_PRIMARY_CORE(MpId)) {
|
||||||
ScuBase = ArmGetScuBaseAddress();
|
ScuBase = ArmGetScuBaseAddress();
|
||||||
|
|
|
@ -0,0 +1,25 @@
|
||||||
|
/** @file
|
||||||
|
|
||||||
|
Copyright (c) 2012, ARM Limited. All rights reserved.
|
||||||
|
|
||||||
|
This program and the accompanying materials
|
||||||
|
are licensed and made available under the terms and conditions of the BSD License
|
||||||
|
which accompanies this distribution. The full text of the license may be found at
|
||||||
|
http://opensource.org/licenses/bsd-license.php
|
||||||
|
|
||||||
|
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||||
|
|
||||||
|
**/
|
||||||
|
|
||||||
|
#ifndef __ARM_CORTEX_A15_H__
|
||||||
|
#define __ARM_CORTEX_A15_H__
|
||||||
|
|
||||||
|
#include <Chipset/ArmV7.h>
|
||||||
|
|
||||||
|
//
|
||||||
|
// Cortex A15 feature bit definitions
|
||||||
|
//
|
||||||
|
#define A15_FEATURE_SMP (1<<6)
|
||||||
|
|
||||||
|
#endif
|
Loading…
Reference in New Issue