mirror of https://github.com/acidanthera/audk.git
MdePkg: Add registers of boot partition feature
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3757 Add registers of boot partition feature which defined in NVM Express 1.4 Spec Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Maggie Chu <maggie.chu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
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Maggie Chu
mergify[bot]
parent
079a58276b
commit
9dd14fc91c
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@ -2,11 +2,12 @@
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Definitions based on NVMe spec. version 1.1.
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(C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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@par Specification Reference:
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NVMe Specification 1.1
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NVMe Specification 1.4
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**/
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@ -18,18 +19,21 @@
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//
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// controller register offsets
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//
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#define NVME_CAP_OFFSET 0x0000 // Controller Capabilities
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#define NVME_VER_OFFSET 0x0008 // Version
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#define NVME_INTMS_OFFSET 0x000c // Interrupt Mask Set
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#define NVME_INTMC_OFFSET 0x0010 // Interrupt Mask Clear
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#define NVME_CC_OFFSET 0x0014 // Controller Configuration
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#define NVME_CSTS_OFFSET 0x001c // Controller Status
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#define NVME_NSSR_OFFSET 0x0020 // NVM Subsystem Reset
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#define NVME_AQA_OFFSET 0x0024 // Admin Queue Attributes
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#define NVME_ASQ_OFFSET 0x0028 // Admin Submission Queue Base Address
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#define NVME_ACQ_OFFSET 0x0030 // Admin Completion Queue Base Address
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#define NVME_SQ0_OFFSET 0x1000 // Submission Queue 0 (admin) Tail Doorbell
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#define NVME_CQ0_OFFSET 0x1004 // Completion Queue 0 (admin) Head Doorbell
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#define NVME_CAP_OFFSET 0x0000 // Controller Capabilities
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#define NVME_VER_OFFSET 0x0008 // Version
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#define NVME_INTMS_OFFSET 0x000c // Interrupt Mask Set
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#define NVME_INTMC_OFFSET 0x0010 // Interrupt Mask Clear
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#define NVME_CC_OFFSET 0x0014 // Controller Configuration
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#define NVME_CSTS_OFFSET 0x001c // Controller Status
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#define NVME_NSSR_OFFSET 0x0020 // NVM Subsystem Reset
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#define NVME_AQA_OFFSET 0x0024 // Admin Queue Attributes
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#define NVME_ASQ_OFFSET 0x0028 // Admin Submission Queue Base Address
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#define NVME_ACQ_OFFSET 0x0030 // Admin Completion Queue Base Address
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#define NVME_BPINFO_OFFSET 0x0040 // Boot Partition Information
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#define NVME_BPRSEL_OFFSET 0x0044 // Boot Partition Read Select
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#define NVME_BPMBL_OFFSET 0x0048 // Boot Partition Memory Buffer Location
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#define NVME_SQ0_OFFSET 0x1000 // Submission Queue 0 (admin) Tail Doorbell
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#define NVME_CQ0_OFFSET 0x1004 // Completion Queue 0 (admin) Head Doorbell
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//
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// These register offsets are defined as 0x1000 + (N * (4 << CAP.DSTRD))
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@ -51,11 +55,14 @@ typedef struct {
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UINT8 To; // Timeout
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UINT16 Dstrd : 4;
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UINT16 Nssrs : 1; // NVM Subsystem Reset Supported NSSRS
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UINT16 Css : 4; // Command Sets Supported - Bit 37
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UINT16 Rsvd3 : 7;
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UINT16 Css : 8; // Command Sets Supported - Bit 37
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UINT16 Bps : 1; // Boot Partition Support - Bit 45 in NVMe1.4
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UINT16 Rsvd3 : 2;
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UINT8 Mpsmin : 4;
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UINT8 Mpsmax : 4;
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UINT8 Rsvd4;
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UINT8 Pmrs : 1;
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UINT8 Cmbs : 1;
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UINT8 Rsvd4 : 6;
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} NVME_CAP;
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//
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@ -115,7 +122,36 @@ typedef struct {
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#define NVME_ACQ UINT64
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//
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// 3.1.11 Offset (1000h + ((2y) * (4 << CAP.DSTRD))): SQyTDBL - Submission Queue y Tail Doorbell
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// 3.1.13 Offset 40h: BPINFO - Boot Partition Information
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//
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typedef struct {
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UINT32 Bpsz : 15; // Boot Partition Size
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UINT32 Rsvd1 : 9;
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UINT32 Brs : 2; // Boot Read Status
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UINT32 Rsvd2 : 5;
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UINT32 Abpid : 1; // Active Boot Partition ID
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} NVME_BPINFO;
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//
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// 3.1.14 Offset 44h: BPRSEL - Boot Partition Read Select
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//
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typedef struct {
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UINT32 Bprsz : 10; // Boot Partition Read Size
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UINT32 Bprof : 20; // Boot Partition Read Offset
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UINT32 Rsvd1 : 1;
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UINT32 Bpid : 1; // Boot Partition Identifier
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} NVME_BPRSEL;
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//
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// 3.1.15 Offset 48h: BPMBL - Boot Partition Memory Buffer Location (Optional)
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//
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typedef struct {
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UINT64 Rsvd1 : 12;
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UINT64 Bmbba : 52; // Boot Partition Memory Buffer Base Address
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} NVME_BPMBL;
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//
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// 3.1.25 Offset (1000h + ((2y) * (4 << CAP.DSTRD))): SQyTDBL - Submission Queue y Tail Doorbell
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//
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typedef struct {
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UINT16 Sqt;
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@ -353,7 +389,7 @@ typedef struct {
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UINT8 Avscc; /* Admin Vendor Specific Command Configuration */
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UINT8 Apsta; /* Autonomous Power State Transition Attributes */
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//
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// Below fields before Rsvd2 are defined in NVM Express 1.3 Spec
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// Below fields before Rsvd2 are defined in NVM Express 1.4 Spec
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//
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UINT16 Wctemp; /* Warning Composite Temperature Threshold */
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UINT16 Cctemp; /* Critical Composite Temperature Threshold */
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@ -361,7 +397,12 @@ typedef struct {
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UINT32 Hmpre; /* Host Memory Buffer Preferred Size */
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UINT32 Hmmin; /* Host Memory Buffer Minimum Size */
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UINT8 Tnvmcap[16]; /* Total NVM Capacity */
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UINT8 Rsvd2[216]; /* Reserved as of NVM Express */
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UINT8 Unvmcap[16]; /* Unallocated NVM Capacity */
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UINT32 Rpmbs; /* Replay Protected Memory Block Support */
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UINT16 Edstt; /* Extended Device Self-test Time */
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UINT8 Dsto; /* Device Self-test Options */
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UINT8 Fwug; /* Firmware Update Granularity */
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UINT8 Rsvd2[192]; /* Reserved as of Nvm Express 1.4 Spec */
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//
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// NVM Command Set Attributes
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//
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@ -433,6 +474,34 @@ typedef struct {
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UINT8 VendorData[3712]; /* Vendor specific data */
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} NVME_ADMIN_NAMESPACE_DATA;
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//
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// RPMB Device Configuration Block Data Structure as of Nvm Express 1.4 Spec
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//
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typedef struct {
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UINT8 Bppe; /* Boot Partition Protection Enable */
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UINT8 Bpl; /* Boot Partition Lock */
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UINT8 Nwpac; /* Namespace Write Protection Authentication Control */
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UINT8 Rsvd1[509]; /* Reserved as of Nvm Express 1.4 Spec */
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} NVME_RPMB_CONFIGURATION_DATA;
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#define RPMB_FRAME_STUFF_BYTES 223
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//
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// RPMB Data Frame as of Nvm Express 1.4 Spec
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//
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typedef struct {
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UINT8 Sbakamc[RPMB_FRAME_STUFF_BYTES]; /* [222-N:00] Stuff Bytes */
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/* [222:222-(N-1)] Authentication Key or Message Authentication Code (MAC) */
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UINT8 Rpmbt; /* RPMB Target */
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UINT64 Nonce[2];
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UINT32 Wcounter; /* Write Counter */
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UINT32 Address; /* Starting address of data to be programmed to or read from the RPMB. */
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UINT32 Scount; /* Sector Count */
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UINT16 Result;
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UINT16 Rpmessage; /* Request/Response Message */
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// UINT8 *Data; /* Data to be written or read by signed access where M = 512 * Sector Count. */
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} NVME_RPMB_DATA_FRAME;
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//
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// NvmExpress Admin Identify Cmd
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//
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@ -564,6 +633,7 @@ typedef struct {
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#define LID_ERROR_INFO 0x1
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#define LID_SMART_INFO 0x2
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#define LID_FW_SLOT_INFO 0x3
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#define LID_BP_INFO 0x15
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UINT32 Rsvd1 : 8;
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UINT32 Numd : 12; /* Number of Dwords */
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UINT32 Rsvd2 : 4; /* Reserved as of Nvm Express 1.1 Spec */
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