mirror of https://github.com/acidanthera/audk.git
ArmPkg: Fix coding style to follow EDK2 coding convention
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11789 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin
parent
838725abd7
commit
9e2b420ee9
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@ -126,7 +126,7 @@ EnableInterruptSource (
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RegShift = Source % 32;
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// write set-enable register
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MmioWrite32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDISER+(4*RegOffset), 1 << RegShift);
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MmioWrite32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDISER + (4*RegOffset), 1 << RegShift);
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return EFI_SUCCESS;
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}
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@ -156,12 +156,12 @@ DisableInterruptSource (
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return EFI_UNSUPPORTED;
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}
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// calculate enable register offset and bit position
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// Calculate enable register offset and bit position
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RegOffset = Source / 32;
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RegShift = Source % 32;
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// write set-enable register
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MmioWrite32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDICER+(4*RegOffset), 1 << RegShift);
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// Write set-enable register
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MmioWrite32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDICER + (4*RegOffset), 1 << RegShift);
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return EFI_SUCCESS;
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}
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@ -197,7 +197,7 @@ GetInterruptSourceState (
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RegOffset = Source / 32;
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RegShift = Source % 32;
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if ((MmioRead32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDISER+(4*RegOffset)) & (1<<RegShift)) == 0) {
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if ((MmioRead32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDISER + (4*RegOffset)) & (1<<RegShift)) == 0) {
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*InterruptState = FALSE;
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} else {
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*InterruptState = TRUE;
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@ -389,27 +389,27 @@ InterruptDxeInitialize (
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RegOffset = i / 4;
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RegShift = (i % 4) * 8;
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MmioAndThenOr32 (
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PcdGet32(PcdGicDistributorBase) + GIC_ICDIPR+(4*RegOffset),
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PcdGet32(PcdGicDistributorBase) + GIC_ICDIPR + (4*RegOffset),
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~(0xff << RegShift),
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GIC_DEFAULT_PRIORITY << RegShift
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);
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}
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// configure interrupts for cpu 0
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// Configure interrupts for cpu 0
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for (i = 0; i < GIC_NUM_REG_PER_INT_BYTES; i++) {
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MmioWrite32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDIPTR + (i*4), 0x01010101);
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}
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// set binary point reg to 0x7 (no preemption)
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// Set binary point reg to 0x7 (no preemption)
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MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCBPR, 0x7);
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// set priority mask reg to 0xff to allow all priorities through
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// Set priority mask reg to 0xff to allow all priorities through
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MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCPMR, 0xff);
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// enable gic cpu interface
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// Enable gic cpu interface
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MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCICR, 0x1);
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// enable gic distributor
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// Enable gic distributor
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MmioWrite32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDDCR, 0x1);
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ZeroMem (&gRegisteredInterruptHandlers, sizeof (gRegisteredInterruptHandlers));
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@ -12,6 +12,7 @@
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*
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**/
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#include <Uefi.h>
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#include <Library/IoLib.h>
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#include <Drivers/PL390Gic.h>
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@ -26,28 +27,27 @@ PL390GicSetupNonSecure (
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IN INTN GicInterruptInterfaceBase
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)
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{
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UINTN CachedPriorityMask = MmioRead32(GicInterruptInterfaceBase + GIC_ICCPMR);
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UINTN CachedPriorityMask = MmioRead32(GicInterruptInterfaceBase + GIC_ICCPMR);
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//Set priority Mask so that no interrupts get through to CPU
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MmioWrite32(GicInterruptInterfaceBase + GIC_ICCPMR, 0);
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// Set priority Mask so that no interrupts get through to CPU
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MmioWrite32(GicInterruptInterfaceBase + GIC_ICCPMR, 0);
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//Check if there are any pending interrupts
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while(0 != (MmioRead32(GicDistributorBase + GIC_ICDICPR) & 0xF))
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{
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//Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal
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UINTN InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
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// Check if there are any pending interrupts
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while(0 != (MmioRead32(GicDistributorBase + GIC_ICDICPR) & 0xF)) {
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// Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal
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UINTN InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
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//Write to End of interrupt signal
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MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
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}
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// Write to End of interrupt signal
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MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
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}
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// Ensure all GIC interrupts are Non-Secure
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MmioWrite32(GicDistributorBase + GIC_ICDISR, 0xffffffff); // IRQs 0-31 are Non-Secure : Private Peripheral Interrupt[31:16] & Software Generated Interrupt[15:0]
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MmioWrite32(GicDistributorBase + GIC_ICDISR + 4, 0xffffffff); // IRQs 32-63 are Non-Secure : Shared Peripheral Interrupt
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MmioWrite32(GicDistributorBase + GIC_ICDISR + 8, 0xffffffff); // And another 32 in case we're on the testchip : Shared Peripheral Interrupt (2)
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MmioWrite32(GicDistributorBase + GIC_ICDISR, 0xffffffff); // IRQs 0-31 are Non-Secure : Private Peripheral Interrupt[31:16] & Software Generated Interrupt[15:0]
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MmioWrite32(GicDistributorBase + GIC_ICDISR + 4, 0xffffffff); // IRQs 32-63 are Non-Secure : Shared Peripheral Interrupt
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MmioWrite32(GicDistributorBase + GIC_ICDISR + 8, 0xffffffff); // And another 32 in case we're on the testchip : Shared Peripheral Interrupt (2)
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// Ensure all interrupts can get through the priority mask
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MmioWrite32(GicInterruptInterfaceBase + GIC_ICCPMR, CachedPriorityMask);
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MmioWrite32(GicInterruptInterfaceBase + GIC_ICCPMR, CachedPriorityMask);
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}
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VOID
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@ -63,12 +63,12 @@ PL390GicEnableInterruptInterface (
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* Enable CPU inteface in Non-secure World
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* Signal Secure Interrupts to CPU using FIQ line *
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*/
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MmioWrite32(GicInterruptInterfaceBase + GIC_ICCICR,
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GIC_ICCICR_ENABLE_SECURE(1) |
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GIC_ICCICR_ENABLE_NS(1) |
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GIC_ICCICR_ACK_CTL(0) |
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GIC_ICCICR_SIGNAL_SECURE_TO_FIQ(1) |
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GIC_ICCICR_USE_SBPR(0));
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MmioWrite32(GicInterruptInterfaceBase + GIC_ICCICR,
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GIC_ICCICR_ENABLE_SECURE(1) |
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GIC_ICCICR_ENABLE_NS(1) |
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GIC_ICCICR_ACK_CTL(0) |
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GIC_ICCICR_SIGNAL_SECURE_TO_FIQ(1) |
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GIC_ICCICR_USE_SBPR(0));
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}
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VOID
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@ -77,7 +77,7 @@ PL390GicEnableDistributor (
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IN INTN GicDistributorBase
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)
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{
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MmioWrite32(GicDistributorBase + GIC_ICDDCR, 1); // turn on the GIC distributor
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MmioWrite32(GicDistributorBase + GIC_ICDDCR, 1); // turn on the GIC distributor
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}
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VOID
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@ -98,18 +98,18 @@ PL390GicAcknowledgeSgiFrom (
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IN INTN CoreId
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)
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{
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INTN InterruptId;
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INTN InterruptId;
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InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
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InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
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//Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
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// Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
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if (((CoreId & 0x7) << 10) == (InterruptId & 0x1C00)) {
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//Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
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// Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
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MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
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return 1;
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} else {
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return 0;
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}
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return 1;
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} else {
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return 0;
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}
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}
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UINT32
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@ -120,16 +120,16 @@ PL390GicAcknowledgeSgi2From (
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IN INTN SgiId
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)
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{
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INTN InterruptId;
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INTN InterruptId;
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InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
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InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
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//Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
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// Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
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if((((CoreId & 0x7) << 10) | (SgiId & 0x3FF)) == (InterruptId & 0x1FFF)) {
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//Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
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// Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
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MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
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return 1;
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} else {
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return 0;
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}
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return 1;
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} else {
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return 0;
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}
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}
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@ -339,7 +339,7 @@ ArmGetScuBaseAddress (
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UINT32
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EFIAPI
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ArmIsScuEnable(
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ArmIsScuEnable (
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VOID
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);
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@ -370,35 +370,35 @@ ArmSetupSmpNonSecure (
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UINTN
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EFIAPI
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ArmReadCbar(
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VOID
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);
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ArmReadCbar (
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VOID
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);
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VOID
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EFIAPI
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ArmInvalidateInstructionAndDataTlb(
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VOID
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);
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ArmInvalidateInstructionAndDataTlb (
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VOID
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);
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UINTN
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EFIAPI
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ArmReadMpidr(
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VOID
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);
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ArmReadMpidr (
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VOID
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);
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UINTN
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EFIAPI
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ArmReadTpidrurw(
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VOID
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);
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ArmReadTpidrurw (
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VOID
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);
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VOID
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EFIAPI
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ArmWriteTpidrurw(
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UINTN Value
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);
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ArmWriteTpidrurw (
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UINTN Value
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);
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#endif // __ARM_V7_H__
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@ -67,247 +67,285 @@
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typedef enum { Level0, Level1,Level2 } MMU_LEVEL;
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typedef struct {
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MMU_LEVEL Level;
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UINT32 Value;
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UINT32 Index;
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UINT32* Table;
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MMU_LEVEL Level;
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UINT32 Value;
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UINT32 Index;
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UINT32* Table;
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} MMU_ENTRY;
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MMU_ENTRY MmuEntryCreate(MMU_LEVEL Level,UINT32* Table,UINT32 Index) {
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MMU_ENTRY Entry;
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Entry.Level = Level;
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Entry.Value = Table[Index];
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Entry.Table = Table;
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Entry.Index = Index;
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return Entry;
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MMU_ENTRY
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MmuEntryCreate (
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IN MMU_LEVEL Level,
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IN UINT32* Table,
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IN UINT32 Index
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)
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{
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MMU_ENTRY Entry;
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Entry.Level = Level;
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Entry.Value = Table[Index];
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Entry.Table = Table;
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Entry.Index = Index;
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return Entry;
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}
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UINT32 MmuEntryIsValidAddress(MMU_LEVEL Level, UINT32 Entry) {
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if (Level == Level0) {
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return 0;
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} else if (Level == Level1) {
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if ((Entry & 0x3) == 0) { // Ignored
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return 0;
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} else if ((Entry & 0x3) == 2) { // Section Type
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return 1;
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} else { // Page Type
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return 0;
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}
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} else if (Level == Level2){
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if ((Entry & 0x3) == 0) { // Ignored
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return 0;
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} else { // Page Type
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return 1;
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}
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} else {
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DEBUG((EFI_D_ERROR,"MmuEntryIsValidAddress: Level:%d Entry:0x%X\n",(UINT32)Level,(UINT32)Entry));
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ASSERT(0);
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return 0;
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UINT32
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MmuEntryIsValidAddress (
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IN MMU_LEVEL Level,
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IN UINT32 Entry
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)
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{
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if (Level == Level0) {
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return 0;
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} else if (Level == Level1) {
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if ((Entry & 0x3) == 0) { // Ignored
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return 0;
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} else if ((Entry & 0x3) == 2) { // Section Type
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return 1;
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} else { // Page Type
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return 0;
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}
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}
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UINT32 MmuEntryGetAddress(MMU_ENTRY Entry) {
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if (Entry.Level == Level1) {
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if ((Entry.Value & 0x3) == 0) {
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return 0;
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} else if ((Entry.Value & 0x3) == 2) { // Section Type
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return Entry.Value & TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK;
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} else if ((Entry.Value & 0x3) == 1) { // Level2 Table
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MMU_ENTRY Entry = MmuEntryCreate(Level2,(UINT32*)(Entry.Value & 0xFFFFC000),0);
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return MmuEntryGetAddress(Entry);
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} else { // Page Type
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return 0;
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}
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} else if (Entry.Level == Level2) {
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if ((Entry.Value & 0x3) == 0) { // Ignored
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return 0;
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} else if ((Entry.Value & 0x3) == 1) { // Large Page
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return Entry.Value & 0xFFFF0000;
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} else if ((Entry.Value & 0x2) == 2) { // Small Page
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return Entry.Value & 0xFFFFF000;
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} else {
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return 0;
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}
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} else {
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ASSERT(0);
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return 0;
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} else if (Level == Level2){
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if ((Entry & 0x3) == 0) { // Ignored
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return 0;
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} else { // Page Type
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return 1;
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}
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} else {
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DEBUG((EFI_D_ERROR,"MmuEntryIsValidAddress: Level:%d Entry:0x%X\n",(UINT32)Level,(UINT32)Entry));
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ASSERT(0);
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return 0;
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}
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}
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UINT32 MmuEntryGetSize(MMU_ENTRY Entry) {
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if (Entry.Level == Level1) {
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if ((Entry.Value & 0x3) == 0) {
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return 0;
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} else if ((Entry.Value & 0x3) == 2) {
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if (Entry.Value & (1 << 18))
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return 16*SIZE_1MB;
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else
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return SIZE_1MB;
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} else if ((Entry.Value & 0x3) == 1) { // Level2 Table split 1MB section
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return SIZE_1MB;
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} else {
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DEBUG((EFI_D_ERROR, "MmuEntryGetSize: Value:0x%X",Entry.Value));
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ASSERT(0);
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return 0;
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}
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} else if (Entry.Level == Level2) {
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if ((Entry.Value & 0x3) == 0) { // Ignored
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return 0;
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} else if ((Entry.Value & 0x3) == 1) { // Large Page
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return SIZE_64KB;
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} else if ((Entry.Value & 0x2) == 2) { // Small Page
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return SIZE_4KB;
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} else {
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ASSERT(0);
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return 0;
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}
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} else {
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ASSERT(0);
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return 0;
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UINT32
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MmuEntryGetAddress (
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IN MMU_ENTRY Entry
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)
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{
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if (Entry.Level == Level1) {
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if ((Entry.Value & 0x3) == 0) {
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return 0;
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} else if ((Entry.Value & 0x3) == 2) { // Section Type
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return Entry.Value & TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK;
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} else if ((Entry.Value & 0x3) == 1) { // Level2 Table
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MMU_ENTRY Entry = MmuEntryCreate(Level2,(UINT32*)(Entry.Value & 0xFFFFC000),0);
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return MmuEntryGetAddress(Entry);
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} else { // Page Type
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return 0;
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}
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}
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CONST CHAR8* MmuEntryGetAttributesName(MMU_ENTRY Entry) {
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if (Entry.Level == Level1) {
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if (GET_TT_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_SECTION_WRITE_BACK(0))
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return "TT_DESCRIPTOR_SECTION_WRITE_BACK";
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else if (GET_TT_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0))
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return "TT_DESCRIPTOR_SECTION_WRITE_THROUGH";
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else if (GET_TT_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_SECTION_DEVICE(0))
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return "TT_DESCRIPTOR_SECTION_DEVICE";
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else if (GET_TT_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_SECTION_UNCACHED(0))
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return "TT_DESCRIPTOR_SECTION_UNCACHED";
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else if (GET_TT_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_SECTION_STRONGLY_ORDER)
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return "TT_DESCRIPTOR_SECTION_STRONGLY_ORDERED";
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else {
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return "SectionUnknown";
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}
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} else if ((Entry.Level == Level2) && ((Entry.Value & 0x2) == 2)) { //Small Page
|
||||
if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_WRITE_BACK)
|
||||
return "TT_DESCRIPTOR_PAGE_WRITE_BACK";
|
||||
else if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_WRITE_THROUGH)
|
||||
return "TT_DESCRIPTOR_PAGE_WRITE_THROUGH";
|
||||
else if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_DEVICE)
|
||||
return "TT_DESCRIPTOR_PAGE_DEVICE";
|
||||
else if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_UNCACHED)
|
||||
return "TT_DESCRIPTOR_PAGE_UNCACHED";
|
||||
else if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_STRONGLY_ORDER)
|
||||
return "TT_DESCRIPTOR_PAGE_STRONGLY_ORDERED";
|
||||
else {
|
||||
return "PageUnknown";
|
||||
}
|
||||
} else if ((Entry.Level == Level2) && ((Entry.Value & 0x3) == 1)) { //Large Page
|
||||
if (GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_LARGEPAGE_WRITE_BACK)
|
||||
return "TT_DESCRIPTOR_LARGEPAGE_WRITE_BACK";
|
||||
else if (GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_LARGEPAGE_WRITE_THROUGH)
|
||||
return "TT_DESCRIPTOR_LARGEPAGE_WRITE_THROUGH";
|
||||
else if (GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_LARGEPAGE_DEVICE)
|
||||
return "TT_DESCRIPTOR_LARGEPAGE_DEVICE";
|
||||
else if (GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_LARGEPAGE_UNCACHED)
|
||||
return "TT_DESCRIPTOR_LARGEPAGE_UNCACHED";
|
||||
else {
|
||||
return "LargePageUnknown";
|
||||
}
|
||||
} else if (Entry.Level == Level2) {
|
||||
if ((Entry.Value & 0x3) == 0) { // Ignored
|
||||
return 0;
|
||||
} else if ((Entry.Value & 0x3) == 1) { // Large Page
|
||||
return Entry.Value & 0xFFFF0000;
|
||||
} else if ((Entry.Value & 0x2) == 2) { // Small Page
|
||||
return Entry.Value & 0xFFFFF000;
|
||||
} else {
|
||||
ASSERT(0);
|
||||
return "";
|
||||
return 0;
|
||||
}
|
||||
} else {
|
||||
ASSERT(0);
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
UINT32 MmuEntryGetAttributes(MMU_ENTRY Entry) {
|
||||
if (Entry.Level == Level1) {
|
||||
if ((Entry.Value & 0x3) == 0) {
|
||||
return 0;
|
||||
} else if ((Entry.Value & 0x3) == 2) {
|
||||
return GET_TT_ATTRIBUTES(Entry.Value);
|
||||
} else {
|
||||
return 0;
|
||||
}
|
||||
} else if ((Entry.Level == Level2) && ((Entry.Value & 0x2) == 2)) { //Small Page
|
||||
if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_WRITE_BACK)
|
||||
return TT_DESCRIPTOR_SECTION_WRITE_BACK(0);
|
||||
else if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_WRITE_THROUGH)
|
||||
return TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0);
|
||||
else if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_DEVICE)
|
||||
return TT_DESCRIPTOR_SECTION_DEVICE(0);
|
||||
else if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_UNCACHED)
|
||||
return TT_DESCRIPTOR_SECTION_UNCACHED(0);
|
||||
else if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_STRONGLY_ORDER)
|
||||
return TT_DESCRIPTOR_SECTION_STRONGLY_ORDER;
|
||||
else {
|
||||
return 0;
|
||||
}
|
||||
} else if ((Entry.Level == Level2) && ((Entry.Value & 0x3) == 1)) { //Large Page
|
||||
if (GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_LARGEPAGE_WRITE_BACK)
|
||||
return TT_DESCRIPTOR_SECTION_WRITE_BACK(0);
|
||||
else if (GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_LARGEPAGE_WRITE_THROUGH)
|
||||
return TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0);
|
||||
else if (GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_LARGEPAGE_DEVICE)
|
||||
return TT_DESCRIPTOR_SECTION_DEVICE(0);
|
||||
else if (GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_LARGEPAGE_UNCACHED)
|
||||
return TT_DESCRIPTOR_SECTION_UNCACHED(0);
|
||||
else {
|
||||
return 0;
|
||||
}
|
||||
UINT32
|
||||
MmuEntryGetSize (
|
||||
IN MMU_ENTRY Entry
|
||||
)
|
||||
{
|
||||
if (Entry.Level == Level1) {
|
||||
if ((Entry.Value & 0x3) == 0) {
|
||||
return 0;
|
||||
} else if ((Entry.Value & 0x3) == 2) {
|
||||
if (Entry.Value & (1 << 18))
|
||||
return 16*SIZE_1MB;
|
||||
else
|
||||
return SIZE_1MB;
|
||||
} else if ((Entry.Value & 0x3) == 1) { // Level2 Table split 1MB section
|
||||
return SIZE_1MB;
|
||||
} else {
|
||||
return 0;
|
||||
DEBUG((EFI_D_ERROR, "MmuEntryGetSize: Value:0x%X",Entry.Value));
|
||||
ASSERT(0);
|
||||
return 0;
|
||||
}
|
||||
} else if (Entry.Level == Level2) {
|
||||
if ((Entry.Value & 0x3) == 0) { // Ignored
|
||||
return 0;
|
||||
} else if ((Entry.Value & 0x3) == 1) { // Large Page
|
||||
return SIZE_64KB;
|
||||
} else if ((Entry.Value & 0x2) == 2) { // Small Page
|
||||
return SIZE_4KB;
|
||||
} else {
|
||||
ASSERT(0);
|
||||
return 0;
|
||||
}
|
||||
} else {
|
||||
ASSERT(0);
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
CONST CHAR8*
|
||||
MmuEntryGetAttributesName (
|
||||
IN MMU_ENTRY Entry
|
||||
)
|
||||
{
|
||||
UINT32 Value;
|
||||
|
||||
if (Entry.Level == Level1) {
|
||||
Value = GET_TT_ATTRIBUTES(Entry.Value) | TT_DESCRIPTOR_SECTION_NS_MASK;
|
||||
if (Value == TT_DESCRIPTOR_SECTION_WRITE_BACK(0))
|
||||
return "TT_DESCRIPTOR_SECTION_WRITE_BACK";
|
||||
else if (Value == TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0))
|
||||
return "TT_DESCRIPTOR_SECTION_WRITE_THROUGH";
|
||||
else if (Value == TT_DESCRIPTOR_SECTION_DEVICE(0))
|
||||
return "TT_DESCRIPTOR_SECTION_DEVICE";
|
||||
else if (Value == TT_DESCRIPTOR_SECTION_UNCACHED(0))
|
||||
return "TT_DESCRIPTOR_SECTION_UNCACHED";
|
||||
else if (Value == TT_DESCRIPTOR_SECTION_STRONGLY_ORDER)
|
||||
return "TT_DESCRIPTOR_SECTION_STRONGLY_ORDERED";
|
||||
else {
|
||||
return "SectionUnknown";
|
||||
}
|
||||
} else if ((Entry.Level == Level2) && ((Entry.Value & 0x2) == 2)) { //Small Page
|
||||
Value = GET_TT_PAGE_ATTRIBUTES(Entry.Value);
|
||||
if (Value == TT_DESCRIPTOR_PAGE_WRITE_BACK)
|
||||
return "TT_DESCRIPTOR_PAGE_WRITE_BACK";
|
||||
else if (Value == TT_DESCRIPTOR_PAGE_WRITE_THROUGH)
|
||||
return "TT_DESCRIPTOR_PAGE_WRITE_THROUGH";
|
||||
else if (Value == TT_DESCRIPTOR_PAGE_DEVICE)
|
||||
return "TT_DESCRIPTOR_PAGE_DEVICE";
|
||||
else if (Value == TT_DESCRIPTOR_PAGE_UNCACHED)
|
||||
return "TT_DESCRIPTOR_PAGE_UNCACHED";
|
||||
else if (Value == TT_DESCRIPTOR_PAGE_STRONGLY_ORDER)
|
||||
return "TT_DESCRIPTOR_PAGE_STRONGLY_ORDERED";
|
||||
else {
|
||||
return "PageUnknown";
|
||||
}
|
||||
} else if ((Entry.Level == Level2) && ((Entry.Value & 0x3) == 1)) { //Large Page
|
||||
Value = GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value);
|
||||
if (Value == TT_DESCRIPTOR_LARGEPAGE_WRITE_BACK)
|
||||
return "TT_DESCRIPTOR_LARGEPAGE_WRITE_BACK";
|
||||
else if (Value == TT_DESCRIPTOR_LARGEPAGE_WRITE_THROUGH)
|
||||
return "TT_DESCRIPTOR_LARGEPAGE_WRITE_THROUGH";
|
||||
else if (Value == TT_DESCRIPTOR_LARGEPAGE_DEVICE)
|
||||
return "TT_DESCRIPTOR_LARGEPAGE_DEVICE";
|
||||
else if (Value == TT_DESCRIPTOR_LARGEPAGE_UNCACHED)
|
||||
return "TT_DESCRIPTOR_LARGEPAGE_UNCACHED";
|
||||
else {
|
||||
return "LargePageUnknown";
|
||||
}
|
||||
} else {
|
||||
ASSERT(0);
|
||||
return "";
|
||||
}
|
||||
}
|
||||
|
||||
UINT32
|
||||
MmuEntryGetAttributes (
|
||||
IN MMU_ENTRY Entry
|
||||
)
|
||||
{
|
||||
if (Entry.Level == Level1) {
|
||||
if ((Entry.Value & 0x3) == 0) {
|
||||
return 0;
|
||||
} else if ((Entry.Value & 0x3) == 2) {
|
||||
return GET_TT_ATTRIBUTES(Entry.Value);
|
||||
} else {
|
||||
return 0;
|
||||
}
|
||||
} else if ((Entry.Level == Level2) && ((Entry.Value & 0x2) == 2)) { //Small Page
|
||||
if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_WRITE_BACK)
|
||||
return TT_DESCRIPTOR_SECTION_WRITE_BACK(0);
|
||||
else if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_WRITE_THROUGH)
|
||||
return TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0);
|
||||
else if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_DEVICE)
|
||||
return TT_DESCRIPTOR_SECTION_DEVICE(0);
|
||||
else if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_UNCACHED)
|
||||
return TT_DESCRIPTOR_SECTION_UNCACHED(0);
|
||||
else if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_STRONGLY_ORDER)
|
||||
return TT_DESCRIPTOR_SECTION_STRONGLY_ORDER;
|
||||
else {
|
||||
return 0;
|
||||
}
|
||||
} else if ((Entry.Level == Level2) && ((Entry.Value & 0x3) == 1)) { //Large Page
|
||||
if (GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_LARGEPAGE_WRITE_BACK)
|
||||
return TT_DESCRIPTOR_SECTION_WRITE_BACK(0);
|
||||
else if (GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_LARGEPAGE_WRITE_THROUGH)
|
||||
return TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0);
|
||||
else if (GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_LARGEPAGE_DEVICE)
|
||||
return TT_DESCRIPTOR_SECTION_DEVICE(0);
|
||||
else if (GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_LARGEPAGE_UNCACHED)
|
||||
return TT_DESCRIPTOR_SECTION_UNCACHED(0);
|
||||
else {
|
||||
return 0;
|
||||
}
|
||||
} else {
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
MMU_ENTRY DumpMmuLevel(MMU_LEVEL Level, UINT32* Table, MMU_ENTRY PreviousEntry) {
|
||||
UINT32 Index = 0, Count;
|
||||
MMU_ENTRY LastEntry, Entry;
|
||||
MMU_ENTRY
|
||||
DumpMmuLevel (
|
||||
IN MMU_LEVEL Level,
|
||||
IN UINT32* Table,
|
||||
IN MMU_ENTRY PreviousEntry
|
||||
)
|
||||
{
|
||||
UINT32 Index = 0, Count;
|
||||
MMU_ENTRY LastEntry, Entry;
|
||||
|
||||
ASSERT((Level == Level1) || (Level == Level2));
|
||||
|
||||
if (Level == Level1) Count = 4096;
|
||||
else Count = 256;
|
||||
if (Level == Level1) Count = 4096;
|
||||
else Count = 256;
|
||||
|
||||
// At Level1, we will get into this function because PreviousEntry is not valid
|
||||
if (!MmuEntryIsValidAddress((MMU_LEVEL)(Level-1),PreviousEntry.Value)) {
|
||||
// Find the first valid address
|
||||
for (; (Index < Count) && (!MmuEntryIsValidAddress(Level,Table[Index])); Index++);
|
||||
// At Level1, we will get into this function because PreviousEntry is not valid
|
||||
if (!MmuEntryIsValidAddress((MMU_LEVEL)(Level-1),PreviousEntry.Value)) {
|
||||
// Find the first valid address
|
||||
for (; (Index < Count) && (!MmuEntryIsValidAddress(Level,Table[Index])); Index++);
|
||||
|
||||
LastEntry = MmuEntryCreate(Level,Table,Index);
|
||||
Index++;
|
||||
LastEntry = MmuEntryCreate(Level,Table,Index);
|
||||
Index++;
|
||||
} else {
|
||||
LastEntry = PreviousEntry;
|
||||
}
|
||||
|
||||
for (; Index < Count; Index++) {
|
||||
Entry = MmuEntryCreate(Level,Table,Index);
|
||||
if ((Level == Level1) && ((Entry.Value & 0x3) == 1)) { // We have got a Level2 table redirection
|
||||
LastEntry = DumpMmuLevel(Level2,(UINT32*)(Entry.Value & 0xFFFFFC00),LastEntry);
|
||||
} else if (!MmuEntryIsValidAddress(Level,Table[Index])) {
|
||||
if (MmuEntryIsValidAddress(LastEntry.Level,LastEntry.Value)) {
|
||||
AsciiPrint("0x%08X-0x%08X\t%a\n",
|
||||
MmuEntryGetAddress(LastEntry),MmuEntryGetAddress(PreviousEntry)+MmuEntryGetSize(PreviousEntry)-1,
|
||||
MmuEntryGetAttributesName(LastEntry));
|
||||
}
|
||||
LastEntry = Entry;
|
||||
} else {
|
||||
LastEntry = PreviousEntry;
|
||||
if (MmuEntryGetAttributes(LastEntry) != MmuEntryGetAttributes(Entry)) {
|
||||
if (MmuEntryIsValidAddress(Level,LastEntry.Value)) {
|
||||
AsciiPrint("0x%08X-0x%08X\t%a\n",
|
||||
MmuEntryGetAddress(LastEntry),MmuEntryGetAddress(PreviousEntry)+MmuEntryGetSize(PreviousEntry)-1,
|
||||
MmuEntryGetAttributesName(LastEntry));
|
||||
}
|
||||
LastEntry = Entry;
|
||||
} else {
|
||||
ASSERT(LastEntry.Value != 0);
|
||||
}
|
||||
}
|
||||
PreviousEntry = Entry;
|
||||
}
|
||||
|
||||
for (; Index < Count; Index++) {
|
||||
Entry = MmuEntryCreate(Level,Table,Index);
|
||||
if ((Level == Level1) && ((Entry.Value & 0x3) == 1)) { // We have got a Level2 table redirection
|
||||
LastEntry = DumpMmuLevel(Level2,(UINT32*)(Entry.Value & 0xFFFFFC00),LastEntry);
|
||||
} else if (!MmuEntryIsValidAddress(Level,Table[Index])) {
|
||||
if (MmuEntryIsValidAddress(LastEntry.Level,LastEntry.Value)) {
|
||||
AsciiPrint("0x%08X-0x%08X\t%a\n",
|
||||
MmuEntryGetAddress(LastEntry),MmuEntryGetAddress(PreviousEntry)+MmuEntryGetSize(PreviousEntry)-1,
|
||||
MmuEntryGetAttributesName(LastEntry));
|
||||
}
|
||||
LastEntry = Entry;
|
||||
} else {
|
||||
if (MmuEntryGetAttributes(LastEntry) != MmuEntryGetAttributes(Entry)) {
|
||||
if (MmuEntryIsValidAddress(Level,LastEntry.Value)) {
|
||||
AsciiPrint("0x%08X-0x%08X\t%a\n",
|
||||
MmuEntryGetAddress(LastEntry),MmuEntryGetAddress(PreviousEntry)+MmuEntryGetSize(PreviousEntry)-1,
|
||||
MmuEntryGetAttributesName(LastEntry));
|
||||
}
|
||||
LastEntry = Entry;
|
||||
} else {
|
||||
ASSERT(LastEntry.Value != 0);
|
||||
}
|
||||
}
|
||||
PreviousEntry = Entry;
|
||||
}
|
||||
if ((Level == Level1) && (LastEntry.Index != Index) && MmuEntryIsValidAddress(Level,LastEntry.Value)) {
|
||||
AsciiPrint("0x%08X-0x%08X\t%a\n",
|
||||
MmuEntryGetAddress(LastEntry),MmuEntryGetAddress(PreviousEntry)+MmuEntryGetSize(PreviousEntry)-1,
|
||||
MmuEntryGetAttributesName(LastEntry));
|
||||
}
|
||||
|
||||
if ((Level == Level1) && (LastEntry.Index != Index) && MmuEntryIsValidAddress(Level,LastEntry.Value)) {
|
||||
AsciiPrint("0x%08X-0x%08X\t%a\n",
|
||||
MmuEntryGetAddress(LastEntry),MmuEntryGetAddress(PreviousEntry)+MmuEntryGetSize(PreviousEntry)-1,
|
||||
MmuEntryGetAttributesName(LastEntry));
|
||||
}
|
||||
|
||||
return LastEntry;
|
||||
return LastEntry;
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -317,17 +355,17 @@ EblDumpMmu (
|
|||
IN CHAR8 **Argv
|
||||
)
|
||||
{
|
||||
UINT32 *TTEntry;
|
||||
MMU_ENTRY NoEntry;
|
||||
UINT32 *TTEntry;
|
||||
MMU_ENTRY NoEntry;
|
||||
|
||||
TTEntry = ArmGetTTBR0BaseAddress();
|
||||
TTEntry = ArmGetTTBR0BaseAddress();
|
||||
|
||||
AsciiPrint ("\nTranslation Table:0x%X\n",TTEntry);
|
||||
AsciiPrint ("Address Range\t\tAttributes\n");
|
||||
AsciiPrint ("____________________________________________________\n");
|
||||
|
||||
NoEntry.Level = (MMU_LEVEL)200;
|
||||
DumpMmuLevel(Level1,TTEntry,NoEntry);
|
||||
AsciiPrint ("\nTranslation Table:0x%X\n",TTEntry);
|
||||
AsciiPrint ("Address Range\t\tAttributes\n");
|
||||
AsciiPrint ("____________________________________________________\n");
|
||||
|
||||
return EFI_SUCCESS;
|
||||
NoEntry.Level = (MMU_LEVEL)200;
|
||||
DumpMmuLevel(Level1,TTEntry,NoEntry);
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue