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ArmPkg: Fix coding style to follow EDK2 coding convention 

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11789 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin 2011-06-11 11:15:55 +00:00
parent 838725abd7
commit 9e2b420ee9
4 changed files with 327 additions and 289 deletions
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22
ArmPkg/Drivers/PL390Gic/PL390GicDxe.c
View File

@ -126,7 +126,7 @@ EnableInterruptSource (
RegShift = Source % 32; RegShift = Source % 32;
// write set-enable register // write set-enable register
MmioWrite32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDISER+(4*RegOffset), 1 << RegShift); MmioWrite32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDISER + (4*RegOffset), 1 << RegShift);
return EFI_SUCCESS; return EFI_SUCCESS;
} }
@ -156,12 +156,12 @@ DisableInterruptSource (
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
// calculate enable register offset and bit position // Calculate enable register offset and bit position
RegOffset = Source / 32; RegOffset = Source / 32;
RegShift = Source % 32; RegShift = Source % 32;
// write set-enable register // Write set-enable register
MmioWrite32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDICER+(4*RegOffset), 1 << RegShift); MmioWrite32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDICER + (4*RegOffset), 1 << RegShift);
return EFI_SUCCESS; return EFI_SUCCESS;
} }
@ -197,7 +197,7 @@ GetInterruptSourceState (
RegOffset = Source / 32; RegOffset = Source / 32;
RegShift = Source % 32; RegShift = Source % 32;
if ((MmioRead32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDISER+(4*RegOffset)) & (1<<RegShift)) == 0) { if ((MmioRead32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDISER + (4*RegOffset)) & (1<<RegShift)) == 0) {
*InterruptState = FALSE; *InterruptState = FALSE;
} else { } else {
*InterruptState = TRUE; *InterruptState = TRUE;
@ -389,27 +389,27 @@ InterruptDxeInitialize (
RegOffset = i / 4; RegOffset = i / 4;
RegShift = (i % 4) * 8; RegShift = (i % 4) * 8;
MmioAndThenOr32 ( MmioAndThenOr32 (
PcdGet32(PcdGicDistributorBase) + GIC_ICDIPR+(4*RegOffset), PcdGet32(PcdGicDistributorBase) + GIC_ICDIPR + (4*RegOffset),
~(0xff << RegShift), ~(0xff << RegShift),
GIC_DEFAULT_PRIORITY << RegShift GIC_DEFAULT_PRIORITY << RegShift
); );
} }
// configure interrupts for cpu 0 // Configure interrupts for cpu 0
for (i = 0; i < GIC_NUM_REG_PER_INT_BYTES; i++) { for (i = 0; i < GIC_NUM_REG_PER_INT_BYTES; i++) {
MmioWrite32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDIPTR + (i*4), 0x01010101); MmioWrite32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDIPTR + (i*4), 0x01010101);
} }
// set binary point reg to 0x7 (no preemption) // Set binary point reg to 0x7 (no preemption)
MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCBPR, 0x7); MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCBPR, 0x7);
// set priority mask reg to 0xff to allow all priorities through // Set priority mask reg to 0xff to allow all priorities through
MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCPMR, 0xff); MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCPMR, 0xff);
// enable gic cpu interface // Enable gic cpu interface
MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCICR, 0x1); MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCICR, 0x1);
// enable gic distributor // Enable gic distributor
MmioWrite32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDDCR, 0x1); MmioWrite32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDDCR, 0x1);
ZeroMem (&gRegisteredInterruptHandlers, sizeof (gRegisteredInterruptHandlers)); ZeroMem (&gRegisteredInterruptHandlers, sizeof (gRegisteredInterruptHandlers));

20
ArmPkg/Drivers/PL390Gic/PL390GicSec.c
View File

@ -12,6 +12,7 @@
* *
**/ **/
#include <Uefi.h>
#include <Library/IoLib.h> #include <Library/IoLib.h>
#include <Drivers/PL390Gic.h> #include <Drivers/PL390Gic.h>
@ -28,16 +29,15 @@ PL390GicSetupNonSecure (
{ {
UINTN CachedPriorityMask = MmioRead32(GicInterruptInterfaceBase + GIC_ICCPMR); UINTN CachedPriorityMask = MmioRead32(GicInterruptInterfaceBase + GIC_ICCPMR);
//Set priority Mask so that no interrupts get through to CPU // Set priority Mask so that no interrupts get through to CPU
MmioWrite32(GicInterruptInterfaceBase + GIC_ICCPMR, 0); MmioWrite32(GicInterruptInterfaceBase + GIC_ICCPMR, 0);
//Check if there are any pending interrupts // Check if there are any pending interrupts
while(0 != (MmioRead32(GicDistributorBase + GIC_ICDICPR) & 0xF)) while(0 != (MmioRead32(GicDistributorBase + GIC_ICDICPR) & 0xF)) {
{ // Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal
//Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal
UINTN InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR); UINTN InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
//Write to End of interrupt signal // Write to End of interrupt signal
MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId); MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
} }
@ -102,9 +102,9 @@ PL390GicAcknowledgeSgiFrom (
InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR); InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
//Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID // Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
if (((CoreId & 0x7) << 10) == (InterruptId & 0x1C00)) { if (((CoreId & 0x7) << 10) == (InterruptId & 0x1C00)) {
//Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR // Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId); MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
return 1; return 1;
} else { } else {
@ -124,9 +124,9 @@ PL390GicAcknowledgeSgi2From (
InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR); InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
//Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID // Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
if((((CoreId & 0x7) << 10) | (SgiId & 0x3FF)) == (InterruptId & 0x1FFF)) { if((((CoreId & 0x7) << 10) | (SgiId & 0x3FF)) == (InterruptId & 0x1FFF)) {
//Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR // Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId); MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
return 1; return 1;
} else { } else {

32
ArmPkg/Include/Chipset/ArmV7.h
View File

@ -339,7 +339,7 @@ ArmGetScuBaseAddress (
UINT32 UINT32
EFIAPI EFIAPI
ArmIsScuEnable( ArmIsScuEnable (
VOID VOID
); );
@ -370,35 +370,35 @@ ArmSetupSmpNonSecure (
UINTN UINTN
EFIAPI EFIAPI
ArmReadCbar( ArmReadCbar (
VOID VOID
); );
VOID VOID
EFIAPI EFIAPI
ArmInvalidateInstructionAndDataTlb( ArmInvalidateInstructionAndDataTlb (
VOID VOID
); );
UINTN UINTN
EFIAPI EFIAPI
ArmReadMpidr( ArmReadMpidr (
VOID VOID
); );
UINTN UINTN
EFIAPI EFIAPI
ArmReadTpidrurw( ArmReadTpidrurw (
VOID VOID
); );
VOID VOID
EFIAPI EFIAPI
ArmWriteTpidrurw( ArmWriteTpidrurw (
UINTN Value UINTN Value
); );
#endif // __ARM_V7_H__ #endif // __ARM_V7_H__

80
ArmPlatformPkg/Library/EblCmdLib/EblCmdMmu.c
View File

@ -73,7 +73,13 @@ typedef struct {
UINT32* Table; UINT32* Table;
} MMU_ENTRY; } MMU_ENTRY;
MMU_ENTRY MmuEntryCreate(MMU_LEVEL Level,UINT32* Table,UINT32 Index) { MMU_ENTRY
MmuEntryCreate (
IN MMU_LEVEL Level,
IN UINT32* Table,
IN UINT32 Index
)
{
MMU_ENTRY Entry; MMU_ENTRY Entry;
Entry.Level = Level; Entry.Level = Level;
Entry.Value = Table[Index]; Entry.Value = Table[Index];
@ -82,7 +88,12 @@ MMU_ENTRY MmuEntryCreate(MMU_LEVEL Level,UINT32* Table,UINT32 Index) {
return Entry; return Entry;
} }
UINT32 MmuEntryIsValidAddress(MMU_LEVEL Level, UINT32 Entry) { UINT32
MmuEntryIsValidAddress (
IN MMU_LEVEL Level,
IN UINT32 Entry
)
{
if (Level == Level0) { if (Level == Level0) {
return 0; return 0;
} else if (Level == Level1) { } else if (Level == Level1) {
@ -106,7 +117,11 @@ UINT32 MmuEntryIsValidAddress(MMU_LEVEL Level, UINT32 Entry) {
} }
} }
UINT32 MmuEntryGetAddress(MMU_ENTRY Entry) { UINT32
MmuEntryGetAddress (
IN MMU_ENTRY Entry
)
{
if (Entry.Level == Level1) { if (Entry.Level == Level1) {
if ((Entry.Value & 0x3) == 0) { if ((Entry.Value & 0x3) == 0) {
return 0; return 0;
@ -134,7 +149,11 @@ UINT32 MmuEntryGetAddress(MMU_ENTRY Entry) {
} }
} }
UINT32 MmuEntryGetSize(MMU_ENTRY Entry) { UINT32
MmuEntryGetSize (
IN MMU_ENTRY Entry
)
{
if (Entry.Level == Level1) { if (Entry.Level == Level1) {
if ((Entry.Value & 0x3) == 0) { if ((Entry.Value & 0x3) == 0) {
return 0; return 0;
@ -167,43 +186,52 @@ UINT32 MmuEntryGetSize(MMU_ENTRY Entry) {
} }
} }
CONST CHAR8* MmuEntryGetAttributesName(MMU_ENTRY Entry) { CONST CHAR8*
MmuEntryGetAttributesName (
IN MMU_ENTRY Entry
)
{
UINT32 Value;
if (Entry.Level == Level1) { if (Entry.Level == Level1) {
if (GET_TT_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_SECTION_WRITE_BACK(0)) Value = GET_TT_ATTRIBUTES(Entry.Value) | TT_DESCRIPTOR_SECTION_NS_MASK;
if (Value == TT_DESCRIPTOR_SECTION_WRITE_BACK(0))
return "TT_DESCRIPTOR_SECTION_WRITE_BACK"; return "TT_DESCRIPTOR_SECTION_WRITE_BACK";
else if (GET_TT_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0)) else if (Value == TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0))
return "TT_DESCRIPTOR_SECTION_WRITE_THROUGH"; return "TT_DESCRIPTOR_SECTION_WRITE_THROUGH";
else if (GET_TT_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_SECTION_DEVICE(0)) else if (Value == TT_DESCRIPTOR_SECTION_DEVICE(0))
return "TT_DESCRIPTOR_SECTION_DEVICE"; return "TT_DESCRIPTOR_SECTION_DEVICE";
else if (GET_TT_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_SECTION_UNCACHED(0)) else if (Value == TT_DESCRIPTOR_SECTION_UNCACHED(0))
return "TT_DESCRIPTOR_SECTION_UNCACHED"; return "TT_DESCRIPTOR_SECTION_UNCACHED";
else if (GET_TT_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_SECTION_STRONGLY_ORDER) else if (Value == TT_DESCRIPTOR_SECTION_STRONGLY_ORDER)
return "TT_DESCRIPTOR_SECTION_STRONGLY_ORDERED"; return "TT_DESCRIPTOR_SECTION_STRONGLY_ORDERED";
else { else {
return "SectionUnknown"; return "SectionUnknown";
} }
} else if ((Entry.Level == Level2) && ((Entry.Value & 0x2) == 2)) { //Small Page } else if ((Entry.Level == Level2) && ((Entry.Value & 0x2) == 2)) { //Small Page
if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_WRITE_BACK) Value = GET_TT_PAGE_ATTRIBUTES(Entry.Value);
if (Value == TT_DESCRIPTOR_PAGE_WRITE_BACK)
return "TT_DESCRIPTOR_PAGE_WRITE_BACK"; return "TT_DESCRIPTOR_PAGE_WRITE_BACK";
else if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_WRITE_THROUGH) else if (Value == TT_DESCRIPTOR_PAGE_WRITE_THROUGH)
return "TT_DESCRIPTOR_PAGE_WRITE_THROUGH"; return "TT_DESCRIPTOR_PAGE_WRITE_THROUGH";
else if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_DEVICE) else if (Value == TT_DESCRIPTOR_PAGE_DEVICE)
return "TT_DESCRIPTOR_PAGE_DEVICE"; return "TT_DESCRIPTOR_PAGE_DEVICE";
else if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_UNCACHED) else if (Value == TT_DESCRIPTOR_PAGE_UNCACHED)
return "TT_DESCRIPTOR_PAGE_UNCACHED"; return "TT_DESCRIPTOR_PAGE_UNCACHED";
else if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_STRONGLY_ORDER) else if (Value == TT_DESCRIPTOR_PAGE_STRONGLY_ORDER)
return "TT_DESCRIPTOR_PAGE_STRONGLY_ORDERED"; return "TT_DESCRIPTOR_PAGE_STRONGLY_ORDERED";
else { else {
return "PageUnknown"; return "PageUnknown";
} }
} else if ((Entry.Level == Level2) && ((Entry.Value & 0x3) == 1)) { //Large Page } else if ((Entry.Level == Level2) && ((Entry.Value & 0x3) == 1)) { //Large Page
if (GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_LARGEPAGE_WRITE_BACK) Value = GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value);
if (Value == TT_DESCRIPTOR_LARGEPAGE_WRITE_BACK)
return "TT_DESCRIPTOR_LARGEPAGE_WRITE_BACK"; return "TT_DESCRIPTOR_LARGEPAGE_WRITE_BACK";
else if (GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_LARGEPAGE_WRITE_THROUGH) else if (Value == TT_DESCRIPTOR_LARGEPAGE_WRITE_THROUGH)
return "TT_DESCRIPTOR_LARGEPAGE_WRITE_THROUGH"; return "TT_DESCRIPTOR_LARGEPAGE_WRITE_THROUGH";
else if (GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_LARGEPAGE_DEVICE) else if (Value == TT_DESCRIPTOR_LARGEPAGE_DEVICE)
return "TT_DESCRIPTOR_LARGEPAGE_DEVICE"; return "TT_DESCRIPTOR_LARGEPAGE_DEVICE";
else if (GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_LARGEPAGE_UNCACHED) else if (Value == TT_DESCRIPTOR_LARGEPAGE_UNCACHED)
return "TT_DESCRIPTOR_LARGEPAGE_UNCACHED"; return "TT_DESCRIPTOR_LARGEPAGE_UNCACHED";
else { else {
return "LargePageUnknown"; return "LargePageUnknown";
@ -214,7 +242,11 @@ CONST CHAR8* MmuEntryGetAttributesName(MMU_ENTRY Entry) {
} }
} }
UINT32 MmuEntryGetAttributes(MMU_ENTRY Entry) { UINT32
MmuEntryGetAttributes (
IN MMU_ENTRY Entry
)
{
if (Entry.Level == Level1) { if (Entry.Level == Level1) {
if ((Entry.Value & 0x3) == 0) { if ((Entry.Value & 0x3) == 0) {
return 0; return 0;
@ -255,7 +287,13 @@ UINT32 MmuEntryGetAttributes(MMU_ENTRY Entry) {
} }
MMU_ENTRY DumpMmuLevel(MMU_LEVEL Level, UINT32* Table, MMU_ENTRY PreviousEntry) { MMU_ENTRY
DumpMmuLevel (
IN MMU_LEVEL Level,
IN UINT32* Table,
IN MMU_ENTRY PreviousEntry
)
{
UINT32 Index = 0, Count; UINT32 Index = 0, Count;
MMU_ENTRY LastEntry, Entry; MMU_ENTRY LastEntry, Entry;