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ArmPkg: Fix coding style to follow EDK2 coding convention

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git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11789 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin 2011-06-11 11:15:55 +00:00
parent 838725abd7
commit 9e2b420ee9
4 changed files with 327 additions and 289 deletions
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22
ArmPkg/Drivers/PL390Gic/PL390GicDxe.c
View File

@ -126,7 +126,7 @@ EnableInterruptSource (
RegShift = Source % 32; RegShift = Source % 32;
// write set-enable register // write set-enable register
MmioWrite32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDISER+(4*RegOffset), 1 << RegShift); MmioWrite32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDISER + (4*RegOffset), 1 << RegShift);
return EFI_SUCCESS; return EFI_SUCCESS;
} }
@ -156,12 +156,12 @@ DisableInterruptSource (
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
// calculate enable register offset and bit position // Calculate enable register offset and bit position
RegOffset = Source / 32; RegOffset = Source / 32;
RegShift = Source % 32; RegShift = Source % 32;
// write set-enable register // Write set-enable register
MmioWrite32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDICER+(4*RegOffset), 1 << RegShift); MmioWrite32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDICER + (4*RegOffset), 1 << RegShift);
return EFI_SUCCESS; return EFI_SUCCESS;
} }
@ -197,7 +197,7 @@ GetInterruptSourceState (
RegOffset = Source / 32; RegOffset = Source / 32;
RegShift = Source % 32; RegShift = Source % 32;
if ((MmioRead32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDISER+(4*RegOffset)) & (1<<RegShift)) == 0) { if ((MmioRead32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDISER + (4*RegOffset)) & (1<<RegShift)) == 0) {
*InterruptState = FALSE; *InterruptState = FALSE;
} else { } else {
*InterruptState = TRUE; *InterruptState = TRUE;
@ -389,27 +389,27 @@ InterruptDxeInitialize (
RegOffset = i / 4; RegOffset = i / 4;
RegShift = (i % 4) * 8; RegShift = (i % 4) * 8;
MmioAndThenOr32 ( MmioAndThenOr32 (
PcdGet32(PcdGicDistributorBase) + GIC_ICDIPR+(4*RegOffset), PcdGet32(PcdGicDistributorBase) + GIC_ICDIPR + (4*RegOffset),
~(0xff << RegShift), ~(0xff << RegShift),
GIC_DEFAULT_PRIORITY << RegShift GIC_DEFAULT_PRIORITY << RegShift
); );
} }
// configure interrupts for cpu 0 // Configure interrupts for cpu 0
for (i = 0; i < GIC_NUM_REG_PER_INT_BYTES; i++) { for (i = 0; i < GIC_NUM_REG_PER_INT_BYTES; i++) {
MmioWrite32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDIPTR + (i*4), 0x01010101); MmioWrite32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDIPTR + (i*4), 0x01010101);
} }
// set binary point reg to 0x7 (no preemption) // Set binary point reg to 0x7 (no preemption)
MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCBPR, 0x7); MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCBPR, 0x7);
// set priority mask reg to 0xff to allow all priorities through // Set priority mask reg to 0xff to allow all priorities through
MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCPMR, 0xff); MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCPMR, 0xff);
// enable gic cpu interface // Enable gic cpu interface
MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCICR, 0x1); MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCICR, 0x1);
// enable gic distributor // Enable gic distributor
MmioWrite32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDDCR, 0x1); MmioWrite32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDDCR, 0x1);
ZeroMem (&gRegisteredInterruptHandlers, sizeof (gRegisteredInterruptHandlers)); ZeroMem (&gRegisteredInterruptHandlers, sizeof (gRegisteredInterruptHandlers));

76
ArmPkg/Drivers/PL390Gic/PL390GicSec.c
View File

@ -12,6 +12,7 @@
* *
**/ **/
#include <Uefi.h>
#include <Library/IoLib.h> #include <Library/IoLib.h>
#include <Drivers/PL390Gic.h> #include <Drivers/PL390Gic.h>
@ -26,28 +27,27 @@ PL390GicSetupNonSecure (
IN INTN GicInterruptInterfaceBase IN INTN GicInterruptInterfaceBase
) )
{ {
UINTN CachedPriorityMask = MmioRead32(GicInterruptInterfaceBase + GIC_ICCPMR); UINTN CachedPriorityMask = MmioRead32(GicInterruptInterfaceBase + GIC_ICCPMR);
//Set priority Mask so that no interrupts get through to CPU // Set priority Mask so that no interrupts get through to CPU
MmioWrite32(GicInterruptInterfaceBase + GIC_ICCPMR, 0); MmioWrite32(GicInterruptInterfaceBase + GIC_ICCPMR, 0);
//Check if there are any pending interrupts // Check if there are any pending interrupts
while(0 != (MmioRead32(GicDistributorBase + GIC_ICDICPR) & 0xF)) while(0 != (MmioRead32(GicDistributorBase + GIC_ICDICPR) & 0xF)) {
{ // Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal
//Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal UINTN InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
UINTN InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
//Write to End of interrupt signal // Write to End of interrupt signal
MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId); MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
} }
// Ensure all GIC interrupts are Non-Secure // Ensure all GIC interrupts are Non-Secure
MmioWrite32(GicDistributorBase + GIC_ICDISR, 0xffffffff); // IRQs 0-31 are Non-Secure : Private Peripheral Interrupt[31:16] & Software Generated Interrupt[15:0] MmioWrite32(GicDistributorBase + GIC_ICDISR, 0xffffffff); // IRQs 0-31 are Non-Secure : Private Peripheral Interrupt[31:16] & Software Generated Interrupt[15:0]
MmioWrite32(GicDistributorBase + GIC_ICDISR + 4, 0xffffffff); // IRQs 32-63 are Non-Secure : Shared Peripheral Interrupt MmioWrite32(GicDistributorBase + GIC_ICDISR + 4, 0xffffffff); // IRQs 32-63 are Non-Secure : Shared Peripheral Interrupt
MmioWrite32(GicDistributorBase + GIC_ICDISR + 8, 0xffffffff); // And another 32 in case we're on the testchip : Shared Peripheral Interrupt (2) MmioWrite32(GicDistributorBase + GIC_ICDISR + 8, 0xffffffff); // And another 32 in case we're on the testchip : Shared Peripheral Interrupt (2)
// Ensure all interrupts can get through the priority mask // Ensure all interrupts can get through the priority mask
MmioWrite32(GicInterruptInterfaceBase + GIC_ICCPMR, CachedPriorityMask); MmioWrite32(GicInterruptInterfaceBase + GIC_ICCPMR, CachedPriorityMask);
} }
VOID VOID
@ -63,12 +63,12 @@ PL390GicEnableInterruptInterface (
* Enable CPU inteface in Non-secure World * Enable CPU inteface in Non-secure World
* Signal Secure Interrupts to CPU using FIQ line * * Signal Secure Interrupts to CPU using FIQ line *
*/ */
MmioWrite32(GicInterruptInterfaceBase + GIC_ICCICR, MmioWrite32(GicInterruptInterfaceBase + GIC_ICCICR,
GIC_ICCICR_ENABLE_SECURE(1) | GIC_ICCICR_ENABLE_SECURE(1) |
GIC_ICCICR_ENABLE_NS(1) | GIC_ICCICR_ENABLE_NS(1) |
GIC_ICCICR_ACK_CTL(0) | GIC_ICCICR_ACK_CTL(0) |
GIC_ICCICR_SIGNAL_SECURE_TO_FIQ(1) | GIC_ICCICR_SIGNAL_SECURE_TO_FIQ(1) |
GIC_ICCICR_USE_SBPR(0)); GIC_ICCICR_USE_SBPR(0));
} }
VOID VOID
@ -77,7 +77,7 @@ PL390GicEnableDistributor (
IN INTN GicDistributorBase IN INTN GicDistributorBase
) )
{ {
MmioWrite32(GicDistributorBase + GIC_ICDDCR, 1); // turn on the GIC distributor MmioWrite32(GicDistributorBase + GIC_ICDDCR, 1); // turn on the GIC distributor
} }
VOID VOID
@ -98,18 +98,18 @@ PL390GicAcknowledgeSgiFrom (
IN INTN CoreId IN INTN CoreId
) )
{ {
INTN InterruptId; INTN InterruptId;
InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR); InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
//Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID // Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
if (((CoreId & 0x7) << 10) == (InterruptId & 0x1C00)) { if (((CoreId & 0x7) << 10) == (InterruptId & 0x1C00)) {
//Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR // Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId); MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
return 1; return 1;
} else { } else {
return 0; return 0;
} }
} }
UINT32 UINT32
@ -120,16 +120,16 @@ PL390GicAcknowledgeSgi2From (
IN INTN SgiId IN INTN SgiId
) )
{ {
INTN InterruptId; INTN InterruptId;
InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR); InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
//Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID // Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
if((((CoreId & 0x7) << 10) | (SgiId & 0x3FF)) == (InterruptId & 0x1FFF)) { if((((CoreId & 0x7) << 10) | (SgiId & 0x3FF)) == (InterruptId & 0x1FFF)) {
//Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR // Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId); MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
return 1; return 1;
} else { } else {
return 0; return 0;
} }
} }

32
ArmPkg/Include/Chipset/ArmV7.h
View File

@ -339,7 +339,7 @@ ArmGetScuBaseAddress (
UINT32 UINT32
EFIAPI EFIAPI
ArmIsScuEnable( ArmIsScuEnable (
VOID VOID
); );
@ -370,35 +370,35 @@ ArmSetupSmpNonSecure (
UINTN UINTN
EFIAPI EFIAPI
ArmReadCbar( ArmReadCbar (
VOID VOID
); );
VOID VOID
EFIAPI EFIAPI
ArmInvalidateInstructionAndDataTlb( ArmInvalidateInstructionAndDataTlb (
VOID VOID
); );
UINTN UINTN
EFIAPI EFIAPI
ArmReadMpidr( ArmReadMpidr (
VOID VOID
); );
UINTN UINTN
EFIAPI EFIAPI
ArmReadTpidrurw( ArmReadTpidrurw (
VOID VOID
); );
VOID VOID
EFIAPI EFIAPI
ArmWriteTpidrurw( ArmWriteTpidrurw (
UINTN Value UINTN Value
); );
#endif // __ARM_V7_H__ #endif // __ARM_V7_H__

486
ArmPlatformPkg/Library/EblCmdLib/EblCmdMmu.c
View File

@ -67,247 +67,285 @@
typedef enum { Level0, Level1,Level2 } MMU_LEVEL; typedef enum { Level0, Level1,Level2 } MMU_LEVEL;
typedef struct { typedef struct {
MMU_LEVEL Level; MMU_LEVEL Level;
UINT32 Value; UINT32 Value;
UINT32 Index; UINT32 Index;
UINT32* Table; UINT32* Table;
} MMU_ENTRY; } MMU_ENTRY;
MMU_ENTRY MmuEntryCreate(MMU_LEVEL Level,UINT32* Table,UINT32 Index) { MMU_ENTRY
MMU_ENTRY Entry; MmuEntryCreate (
Entry.Level = Level; IN MMU_LEVEL Level,
Entry.Value = Table[Index]; IN UINT32* Table,
Entry.Table = Table; IN UINT32 Index
Entry.Index = Index; )
return Entry; {
MMU_ENTRY Entry;
Entry.Level = Level;
Entry.Value = Table[Index];
Entry.Table = Table;
Entry.Index = Index;
return Entry;
} }
UINT32 MmuEntryIsValidAddress(MMU_LEVEL Level, UINT32 Entry) { UINT32
if (Level == Level0) { MmuEntryIsValidAddress (
return 0; IN MMU_LEVEL Level,
} else if (Level == Level1) { IN UINT32 Entry
if ((Entry & 0x3) == 0) { // Ignored )
return 0; {
} else if ((Entry & 0x3) == 2) { // Section Type if (Level == Level0) {
return 1; return 0;
} else { // Page Type } else if (Level == Level1) {
return 0; if ((Entry & 0x3) == 0) { // Ignored
} return 0;
} else if (Level == Level2){ } else if ((Entry & 0x3) == 2) { // Section Type
if ((Entry & 0x3) == 0) { // Ignored return 1;
return 0; } else { // Page Type
} else { // Page Type return 0;
return 1;
}
} else {
DEBUG((EFI_D_ERROR,"MmuEntryIsValidAddress: Level:%d Entry:0x%X\n",(UINT32)Level,(UINT32)Entry));
ASSERT(0);
return 0;
} }
} } else if (Level == Level2){
if ((Entry & 0x3) == 0) { // Ignored
UINT32 MmuEntryGetAddress(MMU_ENTRY Entry) { return 0;
if (Entry.Level == Level1) { } else { // Page Type
if ((Entry.Value & 0x3) == 0) { return 1;
return 0;
} else if ((Entry.Value & 0x3) == 2) { // Section Type
return Entry.Value & TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK;
} else if ((Entry.Value & 0x3) == 1) { // Level2 Table
MMU_ENTRY Entry = MmuEntryCreate(Level2,(UINT32*)(Entry.Value & 0xFFFFC000),0);
return MmuEntryGetAddress(Entry);
} else { // Page Type
return 0;
}
} else if (Entry.Level == Level2) {
if ((Entry.Value & 0x3) == 0) { // Ignored
return 0;
} else if ((Entry.Value & 0x3) == 1) { // Large Page
return Entry.Value & 0xFFFF0000;
} else if ((Entry.Value & 0x2) == 2) { // Small Page
return Entry.Value & 0xFFFFF000;
} else {
return 0;
}
} else {
ASSERT(0);
return 0;
} }
} else {
DEBUG((EFI_D_ERROR,"MmuEntryIsValidAddress: Level:%d Entry:0x%X\n",(UINT32)Level,(UINT32)Entry));
ASSERT(0);
return 0;
}
} }
UINT32 MmuEntryGetSize(MMU_ENTRY Entry) { UINT32
if (Entry.Level == Level1) { MmuEntryGetAddress (
if ((Entry.Value & 0x3) == 0) { IN MMU_ENTRY Entry
return 0; )
} else if ((Entry.Value & 0x3) == 2) { {
if (Entry.Value & (1 << 18)) if (Entry.Level == Level1) {
return 16*SIZE_1MB; if ((Entry.Value & 0x3) == 0) {
else return 0;
return SIZE_1MB; } else if ((Entry.Value & 0x3) == 2) { // Section Type
} else if ((Entry.Value & 0x3) == 1) { // Level2 Table split 1MB section return Entry.Value & TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK;
return SIZE_1MB; } else if ((Entry.Value & 0x3) == 1) { // Level2 Table
} else { MMU_ENTRY Entry = MmuEntryCreate(Level2,(UINT32*)(Entry.Value & 0xFFFFC000),0);
DEBUG((EFI_D_ERROR, "MmuEntryGetSize: Value:0x%X",Entry.Value)); return MmuEntryGetAddress(Entry);
ASSERT(0); } else { // Page Type
return 0; return 0;
}
} else if (Entry.Level == Level2) {
if ((Entry.Value & 0x3) == 0) { // Ignored
return 0;
} else if ((Entry.Value & 0x3) == 1) { // Large Page
return SIZE_64KB;
} else if ((Entry.Value & 0x2) == 2) { // Small Page
return SIZE_4KB;
} else {
ASSERT(0);
return 0;
}
} else {
ASSERT(0);
return 0;
} }
} } else if (Entry.Level == Level2) {
if ((Entry.Value & 0x3) == 0) { // Ignored
CONST CHAR8* MmuEntryGetAttributesName(MMU_ENTRY Entry) { return 0;
if (Entry.Level == Level1) { } else if ((Entry.Value & 0x3) == 1) { // Large Page
if (GET_TT_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_SECTION_WRITE_BACK(0)) return Entry.Value & 0xFFFF0000;
return "TT_DESCRIPTOR_SECTION_WRITE_BACK"; } else if ((Entry.Value & 0x2) == 2) { // Small Page
else if (GET_TT_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0)) return Entry.Value & 0xFFFFF000;
return "TT_DESCRIPTOR_SECTION_WRITE_THROUGH";
else if (GET_TT_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_SECTION_DEVICE(0))
return "TT_DESCRIPTOR_SECTION_DEVICE";
else if (GET_TT_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_SECTION_UNCACHED(0))
return "TT_DESCRIPTOR_SECTION_UNCACHED";
else if (GET_TT_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_SECTION_STRONGLY_ORDER)
return "TT_DESCRIPTOR_SECTION_STRONGLY_ORDERED";
else {
return "SectionUnknown";
}
} else if ((Entry.Level == Level2) && ((Entry.Value & 0x2) == 2)) { //Small Page
if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_WRITE_BACK)
return "TT_DESCRIPTOR_PAGE_WRITE_BACK";
else if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_WRITE_THROUGH)
return "TT_DESCRIPTOR_PAGE_WRITE_THROUGH";
else if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_DEVICE)
return "TT_DESCRIPTOR_PAGE_DEVICE";
else if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_UNCACHED)
return "TT_DESCRIPTOR_PAGE_UNCACHED";
else if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_STRONGLY_ORDER)
return "TT_DESCRIPTOR_PAGE_STRONGLY_ORDERED";
else {
return "PageUnknown";
}
} else if ((Entry.Level == Level2) && ((Entry.Value & 0x3) == 1)) { //Large Page
if (GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_LARGEPAGE_WRITE_BACK)
return "TT_DESCRIPTOR_LARGEPAGE_WRITE_BACK";
else if (GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_LARGEPAGE_WRITE_THROUGH)
return "TT_DESCRIPTOR_LARGEPAGE_WRITE_THROUGH";
else if (GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_LARGEPAGE_DEVICE)
return "TT_DESCRIPTOR_LARGEPAGE_DEVICE";
else if (GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_LARGEPAGE_UNCACHED)
return "TT_DESCRIPTOR_LARGEPAGE_UNCACHED";
else {
return "LargePageUnknown";
}
} else { } else {
ASSERT(0); return 0;
return "";
} }
} else {
ASSERT(0);
return 0;
}
} }
UINT32 MmuEntryGetAttributes(MMU_ENTRY Entry) { UINT32
if (Entry.Level == Level1) { MmuEntryGetSize (
if ((Entry.Value & 0x3) == 0) { IN MMU_ENTRY Entry
return 0; )
} else if ((Entry.Value & 0x3) == 2) { {
return GET_TT_ATTRIBUTES(Entry.Value); if (Entry.Level == Level1) {
} else { if ((Entry.Value & 0x3) == 0) {
return 0; return 0;
} } else if ((Entry.Value & 0x3) == 2) {
} else if ((Entry.Level == Level2) && ((Entry.Value & 0x2) == 2)) { //Small Page if (Entry.Value & (1 << 18))
if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_WRITE_BACK) return 16*SIZE_1MB;
return TT_DESCRIPTOR_SECTION_WRITE_BACK(0); else
else if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_WRITE_THROUGH) return SIZE_1MB;
return TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0); } else if ((Entry.Value & 0x3) == 1) { // Level2 Table split 1MB section
else if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_DEVICE) return SIZE_1MB;
return TT_DESCRIPTOR_SECTION_DEVICE(0);
else if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_UNCACHED)
return TT_DESCRIPTOR_SECTION_UNCACHED(0);
else if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_STRONGLY_ORDER)
return TT_DESCRIPTOR_SECTION_STRONGLY_ORDER;
else {
return 0;
}
} else if ((Entry.Level == Level2) && ((Entry.Value & 0x3) == 1)) { //Large Page
if (GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_LARGEPAGE_WRITE_BACK)
return TT_DESCRIPTOR_SECTION_WRITE_BACK(0);
else if (GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_LARGEPAGE_WRITE_THROUGH)
return TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0);
else if (GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_LARGEPAGE_DEVICE)
return TT_DESCRIPTOR_SECTION_DEVICE(0);
else if (GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_LARGEPAGE_UNCACHED)
return TT_DESCRIPTOR_SECTION_UNCACHED(0);
else {
return 0;
}
} else { } else {
return 0; DEBUG((EFI_D_ERROR, "MmuEntryGetSize: Value:0x%X",Entry.Value));
ASSERT(0);
return 0;
} }
} else if (Entry.Level == Level2) {
if ((Entry.Value & 0x3) == 0) { // Ignored
return 0;
} else if ((Entry.Value & 0x3) == 1) { // Large Page
return SIZE_64KB;
} else if ((Entry.Value & 0x2) == 2) { // Small Page
return SIZE_4KB;
} else {
ASSERT(0);
return 0;
}
} else {
ASSERT(0);
return 0;
}
}
CONST CHAR8*
MmuEntryGetAttributesName (
IN MMU_ENTRY Entry
)
{
UINT32 Value;
if (Entry.Level == Level1) {
Value = GET_TT_ATTRIBUTES(Entry.Value) | TT_DESCRIPTOR_SECTION_NS_MASK;
if (Value == TT_DESCRIPTOR_SECTION_WRITE_BACK(0))
return "TT_DESCRIPTOR_SECTION_WRITE_BACK";
else if (Value == TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0))
return "TT_DESCRIPTOR_SECTION_WRITE_THROUGH";
else if (Value == TT_DESCRIPTOR_SECTION_DEVICE(0))
return "TT_DESCRIPTOR_SECTION_DEVICE";
else if (Value == TT_DESCRIPTOR_SECTION_UNCACHED(0))
return "TT_DESCRIPTOR_SECTION_UNCACHED";
else if (Value == TT_DESCRIPTOR_SECTION_STRONGLY_ORDER)
return "TT_DESCRIPTOR_SECTION_STRONGLY_ORDERED";
else {
return "SectionUnknown";
}
} else if ((Entry.Level == Level2) && ((Entry.Value & 0x2) == 2)) { //Small Page
Value = GET_TT_PAGE_ATTRIBUTES(Entry.Value);
if (Value == TT_DESCRIPTOR_PAGE_WRITE_BACK)
return "TT_DESCRIPTOR_PAGE_WRITE_BACK";
else if (Value == TT_DESCRIPTOR_PAGE_WRITE_THROUGH)
return "TT_DESCRIPTOR_PAGE_WRITE_THROUGH";
else if (Value == TT_DESCRIPTOR_PAGE_DEVICE)
return "TT_DESCRIPTOR_PAGE_DEVICE";
else if (Value == TT_DESCRIPTOR_PAGE_UNCACHED)
return "TT_DESCRIPTOR_PAGE_UNCACHED";
else if (Value == TT_DESCRIPTOR_PAGE_STRONGLY_ORDER)
return "TT_DESCRIPTOR_PAGE_STRONGLY_ORDERED";
else {
return "PageUnknown";
}
} else if ((Entry.Level == Level2) && ((Entry.Value & 0x3) == 1)) { //Large Page
Value = GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value);
if (Value == TT_DESCRIPTOR_LARGEPAGE_WRITE_BACK)
return "TT_DESCRIPTOR_LARGEPAGE_WRITE_BACK";
else if (Value == TT_DESCRIPTOR_LARGEPAGE_WRITE_THROUGH)
return "TT_DESCRIPTOR_LARGEPAGE_WRITE_THROUGH";
else if (Value == TT_DESCRIPTOR_LARGEPAGE_DEVICE)
return "TT_DESCRIPTOR_LARGEPAGE_DEVICE";
else if (Value == TT_DESCRIPTOR_LARGEPAGE_UNCACHED)
return "TT_DESCRIPTOR_LARGEPAGE_UNCACHED";
else {
return "LargePageUnknown";
}
} else {
ASSERT(0);
return "";
}
}
UINT32
MmuEntryGetAttributes (
IN MMU_ENTRY Entry
)
{
if (Entry.Level == Level1) {
if ((Entry.Value & 0x3) == 0) {
return 0;
} else if ((Entry.Value & 0x3) == 2) {
return GET_TT_ATTRIBUTES(Entry.Value);
} else {
return 0;
}
} else if ((Entry.Level == Level2) && ((Entry.Value & 0x2) == 2)) { //Small Page
if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_WRITE_BACK)
return TT_DESCRIPTOR_SECTION_WRITE_BACK(0);
else if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_WRITE_THROUGH)
return TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0);
else if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_DEVICE)
return TT_DESCRIPTOR_SECTION_DEVICE(0);
else if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_UNCACHED)
return TT_DESCRIPTOR_SECTION_UNCACHED(0);
else if (GET_TT_PAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_PAGE_STRONGLY_ORDER)
return TT_DESCRIPTOR_SECTION_STRONGLY_ORDER;
else {
return 0;
}
} else if ((Entry.Level == Level2) && ((Entry.Value & 0x3) == 1)) { //Large Page
if (GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_LARGEPAGE_WRITE_BACK)
return TT_DESCRIPTOR_SECTION_WRITE_BACK(0);
else if (GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_LARGEPAGE_WRITE_THROUGH)
return TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0);
else if (GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_LARGEPAGE_DEVICE)
return TT_DESCRIPTOR_SECTION_DEVICE(0);
else if (GET_TT_LARGEPAGE_ATTRIBUTES(Entry.Value) == TT_DESCRIPTOR_LARGEPAGE_UNCACHED)
return TT_DESCRIPTOR_SECTION_UNCACHED(0);
else {
return 0;
}
} else {
return 0;
}
} }
MMU_ENTRY DumpMmuLevel(MMU_LEVEL Level, UINT32* Table, MMU_ENTRY PreviousEntry) { MMU_ENTRY
UINT32 Index = 0, Count; DumpMmuLevel (
MMU_ENTRY LastEntry, Entry; IN MMU_LEVEL Level,
IN UINT32* Table,
IN MMU_ENTRY PreviousEntry
)
{
UINT32 Index = 0, Count;
MMU_ENTRY LastEntry, Entry;
ASSERT((Level == Level1) || (Level == Level2)); ASSERT((Level == Level1) || (Level == Level2));
if (Level == Level1) Count = 4096; if (Level == Level1) Count = 4096;
else Count = 256; else Count = 256;
// At Level1, we will get into this function because PreviousEntry is not valid // At Level1, we will get into this function because PreviousEntry is not valid
if (!MmuEntryIsValidAddress((MMU_LEVEL)(Level-1),PreviousEntry.Value)) { if (!MmuEntryIsValidAddress((MMU_LEVEL)(Level-1),PreviousEntry.Value)) {
// Find the first valid address // Find the first valid address
for (; (Index < Count) && (!MmuEntryIsValidAddress(Level,Table[Index])); Index++); for (; (Index < Count) && (!MmuEntryIsValidAddress(Level,Table[Index])); Index++);
LastEntry = MmuEntryCreate(Level,Table,Index); LastEntry = MmuEntryCreate(Level,Table,Index);
Index++; Index++;
} else {
LastEntry = PreviousEntry;
}
for (; Index < Count; Index++) {
Entry = MmuEntryCreate(Level,Table,Index);
if ((Level == Level1) && ((Entry.Value & 0x3) == 1)) { // We have got a Level2 table redirection
LastEntry = DumpMmuLevel(Level2,(UINT32*)(Entry.Value & 0xFFFFFC00),LastEntry);
} else if (!MmuEntryIsValidAddress(Level,Table[Index])) {
if (MmuEntryIsValidAddress(LastEntry.Level,LastEntry.Value)) {
AsciiPrint("0x%08X-0x%08X\t%a\n",
MmuEntryGetAddress(LastEntry),MmuEntryGetAddress(PreviousEntry)+MmuEntryGetSize(PreviousEntry)-1,
MmuEntryGetAttributesName(LastEntry));
}
LastEntry = Entry;
} else { } else {
LastEntry = PreviousEntry; if (MmuEntryGetAttributes(LastEntry) != MmuEntryGetAttributes(Entry)) {
if (MmuEntryIsValidAddress(Level,LastEntry.Value)) {
AsciiPrint("0x%08X-0x%08X\t%a\n",
MmuEntryGetAddress(LastEntry),MmuEntryGetAddress(PreviousEntry)+MmuEntryGetSize(PreviousEntry)-1,
MmuEntryGetAttributesName(LastEntry));
}
LastEntry = Entry;
} else {
ASSERT(LastEntry.Value != 0);
}
} }
PreviousEntry = Entry;
}
for (; Index < Count; Index++) { if ((Level == Level1) && (LastEntry.Index != Index) && MmuEntryIsValidAddress(Level,LastEntry.Value)) {
Entry = MmuEntryCreate(Level,Table,Index); AsciiPrint("0x%08X-0x%08X\t%a\n",
if ((Level == Level1) && ((Entry.Value & 0x3) == 1)) { // We have got a Level2 table redirection MmuEntryGetAddress(LastEntry),MmuEntryGetAddress(PreviousEntry)+MmuEntryGetSize(PreviousEntry)-1,
LastEntry = DumpMmuLevel(Level2,(UINT32*)(Entry.Value & 0xFFFFFC00),LastEntry); MmuEntryGetAttributesName(LastEntry));
} else if (!MmuEntryIsValidAddress(Level,Table[Index])) { }
if (MmuEntryIsValidAddress(LastEntry.Level,LastEntry.Value)) {
AsciiPrint("0x%08X-0x%08X\t%a\n",
MmuEntryGetAddress(LastEntry),MmuEntryGetAddress(PreviousEntry)+MmuEntryGetSize(PreviousEntry)-1,
MmuEntryGetAttributesName(LastEntry));
}
LastEntry = Entry;
} else {
if (MmuEntryGetAttributes(LastEntry) != MmuEntryGetAttributes(Entry)) {
if (MmuEntryIsValidAddress(Level,LastEntry.Value)) {
AsciiPrint("0x%08X-0x%08X\t%a\n",
MmuEntryGetAddress(LastEntry),MmuEntryGetAddress(PreviousEntry)+MmuEntryGetSize(PreviousEntry)-1,
MmuEntryGetAttributesName(LastEntry));
}
LastEntry = Entry;
} else {
ASSERT(LastEntry.Value != 0);
}
}
PreviousEntry = Entry;
}
if ((Level == Level1) && (LastEntry.Index != Index) && MmuEntryIsValidAddress(Level,LastEntry.Value)) { return LastEntry;
AsciiPrint("0x%08X-0x%08X\t%a\n",
MmuEntryGetAddress(LastEntry),MmuEntryGetAddress(PreviousEntry)+MmuEntryGetSize(PreviousEntry)-1,
MmuEntryGetAttributesName(LastEntry));
}
return LastEntry;
} }
@ -317,17 +355,17 @@ EblDumpMmu (
IN CHAR8 **Argv IN CHAR8 **Argv
) )
{ {
UINT32 *TTEntry; UINT32 *TTEntry;
MMU_ENTRY NoEntry; MMU_ENTRY NoEntry;
TTEntry = ArmGetTTBR0BaseAddress(); TTEntry = ArmGetTTBR0BaseAddress();
AsciiPrint ("\nTranslation Table:0x%X\n",TTEntry); AsciiPrint ("\nTranslation Table:0x%X\n",TTEntry);
AsciiPrint ("Address Range\t\tAttributes\n"); AsciiPrint ("Address Range\t\tAttributes\n");
AsciiPrint ("____________________________________________________\n"); AsciiPrint ("____________________________________________________\n");
NoEntry.Level = (MMU_LEVEL)200;
DumpMmuLevel(Level1,TTEntry,NoEntry);
return EFI_SUCCESS; NoEntry.Level = (MMU_LEVEL)200;
DumpMmuLevel(Level1,TTEntry,NoEntry);
return EFI_SUCCESS;
} }