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UefiCpuPkg SecCore: Adjust PeiTemporaryRamBase&Size to be 8byte aligned 

As HOB which has 8byte aligned requirement will be built based on them
in PEI phase.

Cc: Liming Gao <liming.gao@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
This commit is contained in:
Star Zeng 2017-07-28 22:13:00 +08:00
parent 884200f95f
commit 9e9ca2100f
1 changed files with 7 additions and 1 deletions
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8
UefiCpuPkg/SecCore/SecMain.c
View File

@ -1,7 +1,7 @@
/** @file
C functions in SEC
Copyright (c) 2008 - 2016, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2008 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -230,6 +230,12 @@ SecStartupPhase2(
ASSERT (SecCoreData->PeiTemporaryRamSize > Index * sizeof (EFI_PEI_PPI_DESCRIPTOR));
SecCoreData->PeiTemporaryRamBase = (VOID *)((UINTN) SecCoreData->PeiTemporaryRamBase + Index * sizeof (EFI_PEI_PPI_DESCRIPTOR));
SecCoreData->PeiTemporaryRamSize = SecCoreData->PeiTemporaryRamSize - Index * sizeof (EFI_PEI_PPI_DESCRIPTOR);
//
// Adjust the Base and Size to be 8-byte aligned as HOB which has 8byte aligned requirement
// will be built based on them in PEI phase.
//
SecCoreData->PeiTemporaryRamBase = (VOID *)(((UINTN)SecCoreData->PeiTemporaryRamBase + 7) & ~0x07);
SecCoreData->PeiTemporaryRamSize &= ~0x07;
} else {
//
// No addition PPI, PpiList directly point to the common PPI list.