mirror of https://github.com/acidanthera/audk.git
Vlv2TbltDevicePkg: Sync the branch changes to Trunk,
Add Microcode, and Change Flash size from 3M to 4M. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Shifei Lu <shifeix.a.lu@intel.com> Reviewed-by: David Wei <david.wei@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18780 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
parent
0c9a522f28
commit
9ea2d90187
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@ -1,6 +1,6 @@
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/** @file
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/** @file
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Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials are licensed and made available under
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This program and the accompanying materials are licensed and made available under
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@ -1,6 +1,6 @@
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/** @file
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/** @file
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Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2007 - 2015, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials are licensed and made available under
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This program and the accompanying materials are licensed and made available under
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the terms and conditions of the BSD License that accompanies this distribution.
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the terms and conditions of the BSD License that accompanies this distribution.
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@ -25,8 +25,8 @@ EFI_HII_HANDLE HiiHandle;
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//00000000 007FFFFF 00800000 Flash Image
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//00000000 007FFFFF 00800000 Flash Image
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//
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//
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//00000000 00000FFF 00001000 Descriptor Region
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//00000000 00000FFF 00001000 Descriptor Region
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//00001000 004FFFFF 004FF000 TXE Region
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//00001000 003FFFFF 003FF000 TXE Region
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//00500000 007FFFFF 00300000 BIOS Region
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//00500000 007FFFFF 00400000 BIOS Region
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//
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//
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FV_REGION_INFO mRegionInfo[] = {
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FV_REGION_INFO mRegionInfo[] = {
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{FixedPcdGet32 (PcdFlashDescriptorBase), FixedPcdGet32 (PcdFlashDescriptorSize), TRUE},
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{FixedPcdGet32 (PcdFlashDescriptorBase), FixedPcdGet32 (PcdFlashDescriptorSize), TRUE},
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@ -26,5 +26,5 @@ OEM_ID = I32
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BUILD_TYPE = D
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BUILD_TYPE = D
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BOARD_ID = BLAKCRB
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BOARD_ID = BLAKCRB
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VERSION_MAJOR = 0083
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VERSION_MAJOR = 0084
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VERSION_MINOR = 01
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VERSION_MINOR = 01
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@ -26,5 +26,5 @@ OEM_ID = I32
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BUILD_TYPE = R
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BUILD_TYPE = R
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BOARD_ID = BLAKCRB
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BOARD_ID = BLAKCRB
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VERSION_MAJOR = 0083
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VERSION_MAJOR = 0084
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VERSION_MINOR = 01
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VERSION_MINOR = 01
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@ -25,6 +25,6 @@ BOARD_REV = 1
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OEM_ID = X64
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OEM_ID = X64
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BUILD_TYPE = D
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BUILD_TYPE = D
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VERSION_MAJOR = 0083
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VERSION_MAJOR = 0084
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VERSION_MINOR = 01
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VERSION_MINOR = 01
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BOARD_ID = BBAYCRB
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BOARD_ID = BBAYCRB
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@ -25,6 +25,6 @@ BOARD_REV = 1
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OEM_ID = X64
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OEM_ID = X64
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BUILD_TYPE = R
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BUILD_TYPE = R
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VERSION_MAJOR = 0083
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VERSION_MAJOR = 0084
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VERSION_MINOR = 01
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VERSION_MINOR = 01
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BOARD_ID = BBAYCRB
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BOARD_ID = BBAYCRB
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@ -1,6 +1,6 @@
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/*++
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/*++
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Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials are licensed and made available under
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This program and the accompanying materials are licensed and made available under
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@ -2,7 +2,7 @@
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# Platform Package
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# Platform Package
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#
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#
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# This package provides platform specific modules.
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# This package provides platform specific modules.
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# Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.<BR>
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# Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>
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#
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#
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# This program and the accompanying materials are licensed and made available under
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# This program and the accompanying materials are licensed and made available under
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# the terms and conditions of the BSD License that accompanies this distribution.
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# the terms and conditions of the BSD License that accompanies this distribution.
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@ -152,9 +152,9 @@
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gPlatformModuleTokenSpaceGuid.PcdFlashDescriptorBase|0xFF800000|UINT32|0x40000003
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gPlatformModuleTokenSpaceGuid.PcdFlashDescriptorBase|0xFF800000|UINT32|0x40000003
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gPlatformModuleTokenSpaceGuid.PcdFlashDescriptorSize|0x00001000|UINT32|0x40000004
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gPlatformModuleTokenSpaceGuid.PcdFlashDescriptorSize|0x00001000|UINT32|0x40000004
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gPlatformModuleTokenSpaceGuid.PcdTxeRomBase|0xFF801000|UINT32|0x40000009
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gPlatformModuleTokenSpaceGuid.PcdTxeRomBase|0xFF801000|UINT32|0x40000009
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gPlatformModuleTokenSpaceGuid.PcdTxeRomSize|0x004FF000|UINT32|0x4000000A
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gPlatformModuleTokenSpaceGuid.PcdTxeRomSize|0x003FF000|UINT32|0x4000000A
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gPlatformModuleTokenSpaceGuid.PcdBiosRomBase|0xFFD00000|UINT32|0x4000000B
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gPlatformModuleTokenSpaceGuid.PcdBiosRomBase|0xFFC00000|UINT32|0x4000000B
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gPlatformModuleTokenSpaceGuid.PcdBiosRomSize|0x00300000|UINT32|0x4000000C
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gPlatformModuleTokenSpaceGuid.PcdBiosRomSize|0x00400000|UINT32|0x4000000C
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[PcdsFeatureFlag]
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[PcdsFeatureFlag]
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## This PCD specifies whether StatusCode is reported via ISA Serial port.
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## This PCD specifies whether StatusCode is reported via ISA Serial port.
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@ -15,45 +15,45 @@
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#**/
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#**/
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[Defines]
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[Defines]
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DEFINE FLASH_BASE = 0xFFD00000 #The base address of the 3Mb FLASH Device.
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DEFINE FLASH_BASE = 0xFFC00000 #The base address of the 4Mb FLASH Device.
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DEFINE FLASH_SIZE = 0x00300000 #The flash size in bytes of the 3Mb FLASH Device.
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DEFINE FLASH_SIZE = 0x00400000 #The flash size in bytes of the 4Mb FLASH Device.
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DEFINE FLASH_BLOCK_SIZE = 0x1000 #The block size in bytes of the 3Mb FLASH Device.
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DEFINE FLASH_BLOCK_SIZE = 0x1000 #The block size in bytes of the 4Mb FLASH Device.
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DEFINE FLASH_NUM_BLOCKS = 0x300 #The number of blocks in 3Mb FLASH Device.
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DEFINE FLASH_NUM_BLOCKS = 0x400 #The number of blocks in 4Mb FLASH Device.
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DEFINE FLASH_AREA_BASE_ADDRESS = 0xFF800000
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DEFINE FLASH_AREA_BASE_ADDRESS = 0xFF800000
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DEFINE FLASH_AREA_SIZE = 0x00800000
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DEFINE FLASH_AREA_SIZE = 0x00800000
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DEFINE FLASH_REGION_VLVMICROCODE_OFFSET = 0x00000000
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DEFINE FLASH_REGION_VLVMICROCODE_OFFSET = 0x00000000
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DEFINE FLASH_REGION_VLVMICROCODE_SIZE = 0x00030000
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DEFINE FLASH_REGION_VLVMICROCODE_SIZE = 0x00040000
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DEFINE FLASH_REGION_VLVMICROCODE_BASE = 0xFFD00000
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DEFINE FLASH_REGION_VLVMICROCODE_BASE = 0xFFC00000
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DEFINE FLASH_REGION_VPD_OFFSET = 0x00030000
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DEFINE FLASH_REGION_VPD_OFFSET = 0x00130000
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DEFINE FLASH_REGION_VPD_SIZE = 0x0003E000
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DEFINE FLASH_REGION_VPD_SIZE = 0x0003E000
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DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_OFFSET = 0x0006E000
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DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_OFFSET = 0x0016E000
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DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_SIZE = 0x00002000
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DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_SIZE = 0x00002000
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DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_OFFSET = 0x00070000
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DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_OFFSET = 0x00170000
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DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_SIZE = 0x00040000
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DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_SIZE = 0x00040000
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!if $(MINNOW2_FSP_BUILD) == TRUE
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!if $(MINNOW2_FSP_BUILD) == TRUE
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DEFINE FLASH_REGION_FSPBIN_OFFSET = 0x000B0000
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DEFINE FLASH_REGION_FSPBIN_OFFSET = 0x001B0000
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DEFINE FLASH_REGION_FSPBIN_SIZE = 0x00048000
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DEFINE FLASH_REGION_FSPBIN_SIZE = 0x00048000
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DEFINE FLASH_REGION_FSPBIN_BASE = 0xFFDB0000
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DEFINE FLASH_REGION_FSPBIN_BASE = 0xFFDB0000
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DEFINE FLASH_REGION_AZALIABIN_OFFSET = 0x000F8000
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DEFINE FLASH_REGION_AZALIABIN_OFFSET = 0x001F8000
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DEFINE FLASH_REGION_AZALIABIN_SIZE = 0x00008000
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DEFINE FLASH_REGION_AZALIABIN_SIZE = 0x00008000
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DEFINE FLASH_REGION_AZALIABIN_BASE = 0xFFDF8000
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DEFINE FLASH_REGION_AZALIABIN_BASE = 0xFFDF8000
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!endif
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!endif
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DEFINE FLASH_REGION_FVMAIN_OFFSET = 0x00100000
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DEFINE FLASH_REGION_FVMAIN_OFFSET = 0x00200000
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DEFINE FLASH_REGION_FVMAIN_SIZE = 0x001A5000
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DEFINE FLASH_REGION_FVMAIN_SIZE = 0x001A5000
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DEFINE FLASH_REGION_FV_RECOVERY2_OFFSET = 0x002A5000
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DEFINE FLASH_REGION_FV_RECOVERY2_OFFSET = 0x003A5000
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DEFINE FLASH_REGION_FV_RECOVERY2_SIZE = 0x0002B000
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DEFINE FLASH_REGION_FV_RECOVERY2_SIZE = 0x0002B000
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DEFINE FLASH_REGION_FV_RECOVERY_OFFSET = 0x002D0000
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DEFINE FLASH_REGION_FV_RECOVERY_OFFSET = 0x003D0000
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DEFINE FLASH_REGION_FV_RECOVERY_SIZE = 0x00030000
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DEFINE FLASH_REGION_FV_RECOVERY_SIZE = 0x00030000
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################################################################################
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################################################################################
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#**/
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#**/
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[Defines]
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[Defines]
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DEFINE FLASH_BASE = 0xFFD00000 #The base address of the 3Mb FLASH Device.
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DEFINE FLASH_BASE = 0xFFC00000 #The base address of the 4Mb FLASH Device.
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DEFINE FLASH_SIZE = 0x00300000 #The flash size in bytes of the 3Mb FLASH Device.
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DEFINE FLASH_SIZE = 0x00400000 #The flash size in bytes of the 4Mb FLASH Device.
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DEFINE FLASH_BLOCK_SIZE = 0x1000 #The block size in bytes of the 3Mb FLASH Device.
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DEFINE FLASH_BLOCK_SIZE = 0x1000 #The block size in bytes of the 4Mb FLASH Device.
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DEFINE FLASH_NUM_BLOCKS = 0x300 #The number of blocks in 3Mb FLASH Device.
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DEFINE FLASH_NUM_BLOCKS = 0x400 #The number of blocks in 4Mb FLASH Device.
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DEFINE FLASH_AREA_BASE_ADDRESS = 0xFF800000
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DEFINE FLASH_AREA_BASE_ADDRESS = 0xFF800000
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DEFINE FLASH_AREA_SIZE = 0x00800000
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DEFINE FLASH_AREA_SIZE = 0x00800000
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DEFINE FLASH_REGION_VLVMICROCODE_OFFSET = 0x00000000
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DEFINE FLASH_REGION_VLVMICROCODE_OFFSET = 0x00000000
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DEFINE FLASH_REGION_VLVMICROCODE_SIZE = 0x00030000
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DEFINE FLASH_REGION_VLVMICROCODE_SIZE = 0x00040000
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DEFINE FLASH_REGION_VLVMICROCODE_BASE = 0xFFD00000
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DEFINE FLASH_REGION_VLVMICROCODE_BASE = 0xFFC00000
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DEFINE FLASH_REGION_VPD_OFFSET = 0x00030000
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DEFINE FLASH_REGION_VPD_OFFSET = 0x00130000
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DEFINE FLASH_REGION_VPD_SIZE = 0x0003E000
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DEFINE FLASH_REGION_VPD_SIZE = 0x0003E000
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DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_OFFSET = 0x0006E000
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DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_OFFSET = 0x0016E000
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DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_SIZE = 0x00002000
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DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_SIZE = 0x00002000
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DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_OFFSET = 0x00070000
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DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_OFFSET = 0x00170000
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DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_SIZE = 0x00040000
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DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_SIZE = 0x00040000
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!if $(MINNOW2_FSP_BUILD) == TRUE
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!if $(MINNOW2_FSP_BUILD) == TRUE
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DEFINE FLASH_REGION_FSPBIN_OFFSET = 0x000B0000
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DEFINE FLASH_REGION_FSPBIN_OFFSET = 0x001B0000
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DEFINE FLASH_REGION_FSPBIN_SIZE = 0x00048000
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DEFINE FLASH_REGION_FSPBIN_SIZE = 0x00048000
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DEFINE FLASH_REGION_FSPBIN_BASE = 0xFFDB0000
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DEFINE FLASH_REGION_FSPBIN_BASE = 0xFFDB0000
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DEFINE FLASH_REGION_AZALIABIN_OFFSET = 0x000F8000
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DEFINE FLASH_REGION_AZALIABIN_OFFSET = 0x001F8000
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DEFINE FLASH_REGION_AZALIABIN_SIZE = 0x00008000
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DEFINE FLASH_REGION_AZALIABIN_SIZE = 0x00008000
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DEFINE FLASH_REGION_AZALIABIN_BASE = 0xFFDF8000
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DEFINE FLASH_REGION_AZALIABIN_BASE = 0xFFDF8000
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!endif
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!endif
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DEFINE FLASH_REGION_FVMAIN_OFFSET = 0x00100000
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DEFINE FLASH_REGION_FVMAIN_OFFSET = 0x00200000
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DEFINE FLASH_REGION_FVMAIN_SIZE = 0x00196000
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DEFINE FLASH_REGION_FVMAIN_SIZE = 0x00196000
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DEFINE FLASH_REGION_FV_RECOVERY2_OFFSET = 0x00396000
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DEFINE FLASH_REGION_FV_RECOVERY2_OFFSET = 0x00296000
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DEFINE FLASH_REGION_FV_RECOVERY2_SIZE = 0x0002C000
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DEFINE FLASH_REGION_FV_RECOVERY2_SIZE = 0x0002C000
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DEFINE FLASH_REGION_FV_RECOVERY_OFFSET = 0x002C2000
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DEFINE FLASH_REGION_FV_RECOVERY_OFFSET = 0x003C2000
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DEFINE FLASH_REGION_FV_RECOVERY_SIZE = 0x0003E000
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DEFINE FLASH_REGION_FV_RECOVERY_SIZE = 0x0003E000
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################################################################################
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################################################################################
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[PcdsFixedAtBuild.common]
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[PcdsFixedAtBuild.common]
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!if $(MINNOW2_FSP_BUILD) == TRUE
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!if $(MINNOW2_FSP_BUILD) == TRUE
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# $(FLASH_REGION_VLVMICROCODE_BASE)
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# $(FLASH_REGION_VLVMICROCODE_BASE)
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gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0xFFD00000
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gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0xFFC00000
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# $(FLASH_REGION_VLVMICROCODE_SIZE)
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# $(FLASH_REGION_VLVMICROCODE_SIZE)
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gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x00030000
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gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x00040000
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gFspWrapperTokenSpaceGuid.PcdFlashMicroCodeOffset|0x60
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gFspWrapperTokenSpaceGuid.PcdFlashMicroCodeOffset|0x60
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# $(FLASH_AREA_BASE_ADDRESS)
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# $(FLASH_AREA_BASE_ADDRESS)
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gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheAddress|0xFF800000
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gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheAddress|0xFF800000
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[PcdsFixedAtBuild.common]
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[PcdsFixedAtBuild.common]
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!if $(MINNOW2_FSP_BUILD) == TRUE
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!if $(MINNOW2_FSP_BUILD) == TRUE
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# $(FLASH_REGION_VLVMICROCODE_BASE)
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# $(FLASH_REGION_VLVMICROCODE_BASE)
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gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0xFFD00000
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gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0xFFC00000
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# $(FLASH_REGION_VLVMICROCODE_SIZE)
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# $(FLASH_REGION_VLVMICROCODE_SIZE)
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gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x00030000
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gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x00040000
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||||||
gFspWrapperTokenSpaceGuid.PcdFlashMicroCodeOffset|0x60
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gFspWrapperTokenSpaceGuid.PcdFlashMicroCodeOffset|0x60
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# $(FLASH_AREA_BASE_ADDRESS)
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# $(FLASH_AREA_BASE_ADDRESS)
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gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheAddress|0xFF800000
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gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheAddress|0xFF800000
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|
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[PcdsFixedAtBuild.common]
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[PcdsFixedAtBuild.common]
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!if $(MINNOW2_FSP_BUILD) == TRUE
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!if $(MINNOW2_FSP_BUILD) == TRUE
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||||||
# $(FLASH_REGION_VLVMICROCODE_BASE)
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# $(FLASH_REGION_VLVMICROCODE_BASE)
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||||||
gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0xFFD00000
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gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0xFFC00000
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# $(FLASH_REGION_VLVMICROCODE_SIZE)
|
# $(FLASH_REGION_VLVMICROCODE_SIZE)
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gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x00030000
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gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x00040000
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gFspWrapperTokenSpaceGuid.PcdFlashMicroCodeOffset|0x60
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gFspWrapperTokenSpaceGuid.PcdFlashMicroCodeOffset|0x60
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# $(FLASH_AREA_BASE_ADDRESS)
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# $(FLASH_AREA_BASE_ADDRESS)
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gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheAddress|0xFF800000
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gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheAddress|0xFF800000
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//
|
//
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||||||
//
|
//
|
||||||
// Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
|
// Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
|
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//
|
//
|
||||||
// This program and the accompanying materials are licensed and made available under
|
// This program and the accompanying materials are licensed and made available under
|
||||||
// the terms and conditions of the BSD License that accompanies this distribution.
|
// the terms and conditions of the BSD License that accompanies this distribution.
|
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|
|
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@ -12,5 +12,5 @@
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#
|
#
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||||||
|
|
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HEADER=IFWI_HEADER
|
HEADER=IFWI_HEADER
|
||||||
SEC_VERSION=1.0.2.1067
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SEC_VERSION=1.0.2.1060v5
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|
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@ -233,7 +233,7 @@ BOARD_ID=$(grep '^BOARD_ID' Conf/BiosId.env | cut -d ' ' -f 3 | cut -c 1-7)
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BIOS_Name="$BOARD_ID"_"$Arch"_"$BUILD_TYPE"_"$VERSION_MAJOR"_"$VERSION_MINOR".ROM
|
BIOS_Name="$BOARD_ID"_"$Arch"_"$BUILD_TYPE"_"$VERSION_MAJOR"_"$VERSION_MINOR".ROM
|
||||||
BIOS_ID="$BOARD_ID"_"$Arch"_"$BUILD_TYPE"_"$VERSION_MAJOR"_"$VERSION_MINOR"_GCC.bin
|
BIOS_ID="$BOARD_ID"_"$Arch"_"$BUILD_TYPE"_"$VERSION_MAJOR"_"$VERSION_MINOR"_GCC.bin
|
||||||
cp -f $BUILD_PATH/FV/VLV.fd $WORKSPACE/$BIOS_Name
|
cp -f $BUILD_PATH/FV/VLV.fd $WORKSPACE/$BIOS_Name
|
||||||
SEC_VERSION=1.0.2.1067
|
SEC_VERSION=1.0.2.1060v5
|
||||||
cat $IFWI_HEADER_FILE ./Vlv2MiscBinariesPkg/SEC/$SEC_VERSION/VLV_SEC_REGION.bin ./Vlv2MiscBinariesPkg/SEC/$SEC_VERSION/Vacant.bin $BIOS_Name > ./$PLATFORM_PACKAGE/Stitch/$BIOS_ID
|
cat $IFWI_HEADER_FILE ./Vlv2MiscBinariesPkg/SEC/$SEC_VERSION/VLV_SEC_REGION.bin ./Vlv2MiscBinariesPkg/SEC/$SEC_VERSION/Vacant.bin $BIOS_Name > ./$PLATFORM_PACKAGE/Stitch/$BIOS_ID
|
||||||
|
|
||||||
|
|
||||||
|
|
Loading…
Reference in New Issue