Vlv2TbltDevicePkg: Sync the branch changes to Trunk,

Add Microcode, and Change Flash size from 3M to 4M.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Shifei Lu <shifeix.a.lu@intel.com>
Reviewed-by: David Wei <david.wei@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18780 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Shifei Lu 2015-11-13 02:38:08 +00:00 committed by timhe
parent 0c9a522f28
commit 9ea2d90187
18 changed files with 51 additions and 52 deletions

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@ -1,6 +1,6 @@
/** @file /** @file
Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR> Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under This program and the accompanying materials are licensed and made available under

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@ -1,6 +1,6 @@
/** @file /** @file
Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR> Copyright (c) 2007 - 2015, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution. the terms and conditions of the BSD License that accompanies this distribution.
@ -25,8 +25,8 @@ EFI_HII_HANDLE HiiHandle;
//00000000 007FFFFF 00800000 Flash Image //00000000 007FFFFF 00800000 Flash Image
// //
//00000000 00000FFF 00001000 Descriptor Region //00000000 00000FFF 00001000 Descriptor Region
//00001000 004FFFFF 004FF000 TXE Region //00001000 003FFFFF 003FF000 TXE Region
//00500000 007FFFFF 00300000 BIOS Region //00500000 007FFFFF 00400000 BIOS Region
// //
FV_REGION_INFO mRegionInfo[] = { FV_REGION_INFO mRegionInfo[] = {
{FixedPcdGet32 (PcdFlashDescriptorBase), FixedPcdGet32 (PcdFlashDescriptorSize), TRUE}, {FixedPcdGet32 (PcdFlashDescriptorBase), FixedPcdGet32 (PcdFlashDescriptorSize), TRUE},

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@ -26,5 +26,5 @@ OEM_ID = I32
BUILD_TYPE = D BUILD_TYPE = D
BOARD_ID = BLAKCRB BOARD_ID = BLAKCRB
VERSION_MAJOR = 0083 VERSION_MAJOR = 0084
VERSION_MINOR = 01 VERSION_MINOR = 01

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@ -26,5 +26,5 @@ OEM_ID = I32
BUILD_TYPE = R BUILD_TYPE = R
BOARD_ID = BLAKCRB BOARD_ID = BLAKCRB
VERSION_MAJOR = 0083 VERSION_MAJOR = 0084
VERSION_MINOR = 01 VERSION_MINOR = 01

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@ -25,6 +25,6 @@ BOARD_REV = 1
OEM_ID = X64 OEM_ID = X64
BUILD_TYPE = D BUILD_TYPE = D
VERSION_MAJOR = 0083 VERSION_MAJOR = 0084
VERSION_MINOR = 01 VERSION_MINOR = 01
BOARD_ID = BBAYCRB BOARD_ID = BBAYCRB

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@ -25,6 +25,6 @@ BOARD_REV = 1
OEM_ID = X64 OEM_ID = X64
BUILD_TYPE = R BUILD_TYPE = R
VERSION_MAJOR = 0083 VERSION_MAJOR = 0084
VERSION_MINOR = 01 VERSION_MINOR = 01
BOARD_ID = BBAYCRB BOARD_ID = BBAYCRB

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@ -1,6 +1,6 @@
/*++ /*++
Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR> Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under This program and the accompanying materials are licensed and made available under

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@ -2,7 +2,7 @@
# Platform Package # Platform Package
# #
# This package provides platform specific modules. # This package provides platform specific modules.
# Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.<BR> # Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>
# #
# This program and the accompanying materials are licensed and made available under # This program and the accompanying materials are licensed and made available under
# the terms and conditions of the BSD License that accompanies this distribution. # the terms and conditions of the BSD License that accompanies this distribution.
@ -152,9 +152,9 @@
gPlatformModuleTokenSpaceGuid.PcdFlashDescriptorBase|0xFF800000|UINT32|0x40000003 gPlatformModuleTokenSpaceGuid.PcdFlashDescriptorBase|0xFF800000|UINT32|0x40000003
gPlatformModuleTokenSpaceGuid.PcdFlashDescriptorSize|0x00001000|UINT32|0x40000004 gPlatformModuleTokenSpaceGuid.PcdFlashDescriptorSize|0x00001000|UINT32|0x40000004
gPlatformModuleTokenSpaceGuid.PcdTxeRomBase|0xFF801000|UINT32|0x40000009 gPlatformModuleTokenSpaceGuid.PcdTxeRomBase|0xFF801000|UINT32|0x40000009
gPlatformModuleTokenSpaceGuid.PcdTxeRomSize|0x004FF000|UINT32|0x4000000A gPlatformModuleTokenSpaceGuid.PcdTxeRomSize|0x003FF000|UINT32|0x4000000A
gPlatformModuleTokenSpaceGuid.PcdBiosRomBase|0xFFD00000|UINT32|0x4000000B gPlatformModuleTokenSpaceGuid.PcdBiosRomBase|0xFFC00000|UINT32|0x4000000B
gPlatformModuleTokenSpaceGuid.PcdBiosRomSize|0x00300000|UINT32|0x4000000C gPlatformModuleTokenSpaceGuid.PcdBiosRomSize|0x00400000|UINT32|0x4000000C
[PcdsFeatureFlag] [PcdsFeatureFlag]
## This PCD specifies whether StatusCode is reported via ISA Serial port. ## This PCD specifies whether StatusCode is reported via ISA Serial port.

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@ -15,45 +15,45 @@
#**/ #**/
[Defines] [Defines]
DEFINE FLASH_BASE = 0xFFD00000 #The base address of the 3Mb FLASH Device. DEFINE FLASH_BASE = 0xFFC00000 #The base address of the 4Mb FLASH Device.
DEFINE FLASH_SIZE = 0x00300000 #The flash size in bytes of the 3Mb FLASH Device. DEFINE FLASH_SIZE = 0x00400000 #The flash size in bytes of the 4Mb FLASH Device.
DEFINE FLASH_BLOCK_SIZE = 0x1000 #The block size in bytes of the 3Mb FLASH Device. DEFINE FLASH_BLOCK_SIZE = 0x1000 #The block size in bytes of the 4Mb FLASH Device.
DEFINE FLASH_NUM_BLOCKS = 0x300 #The number of blocks in 3Mb FLASH Device. DEFINE FLASH_NUM_BLOCKS = 0x400 #The number of blocks in 4Mb FLASH Device.
DEFINE FLASH_AREA_BASE_ADDRESS = 0xFF800000 DEFINE FLASH_AREA_BASE_ADDRESS = 0xFF800000
DEFINE FLASH_AREA_SIZE = 0x00800000 DEFINE FLASH_AREA_SIZE = 0x00800000
DEFINE FLASH_REGION_VLVMICROCODE_OFFSET = 0x00000000 DEFINE FLASH_REGION_VLVMICROCODE_OFFSET = 0x00000000
DEFINE FLASH_REGION_VLVMICROCODE_SIZE = 0x00030000 DEFINE FLASH_REGION_VLVMICROCODE_SIZE = 0x00040000
DEFINE FLASH_REGION_VLVMICROCODE_BASE = 0xFFD00000 DEFINE FLASH_REGION_VLVMICROCODE_BASE = 0xFFC00000
DEFINE FLASH_REGION_VPD_OFFSET = 0x00030000 DEFINE FLASH_REGION_VPD_OFFSET = 0x00130000
DEFINE FLASH_REGION_VPD_SIZE = 0x0003E000 DEFINE FLASH_REGION_VPD_SIZE = 0x0003E000
DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_OFFSET = 0x0006E000 DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_OFFSET = 0x0016E000
DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_SIZE = 0x00002000 DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_SIZE = 0x00002000
DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_OFFSET = 0x00070000 DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_OFFSET = 0x00170000
DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_SIZE = 0x00040000 DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_SIZE = 0x00040000
!if $(MINNOW2_FSP_BUILD) == TRUE !if $(MINNOW2_FSP_BUILD) == TRUE
DEFINE FLASH_REGION_FSPBIN_OFFSET = 0x000B0000 DEFINE FLASH_REGION_FSPBIN_OFFSET = 0x001B0000
DEFINE FLASH_REGION_FSPBIN_SIZE = 0x00048000 DEFINE FLASH_REGION_FSPBIN_SIZE = 0x00048000
DEFINE FLASH_REGION_FSPBIN_BASE = 0xFFDB0000 DEFINE FLASH_REGION_FSPBIN_BASE = 0xFFDB0000
DEFINE FLASH_REGION_AZALIABIN_OFFSET = 0x000F8000 DEFINE FLASH_REGION_AZALIABIN_OFFSET = 0x001F8000
DEFINE FLASH_REGION_AZALIABIN_SIZE = 0x00008000 DEFINE FLASH_REGION_AZALIABIN_SIZE = 0x00008000
DEFINE FLASH_REGION_AZALIABIN_BASE = 0xFFDF8000 DEFINE FLASH_REGION_AZALIABIN_BASE = 0xFFDF8000
!endif !endif
DEFINE FLASH_REGION_FVMAIN_OFFSET = 0x00100000 DEFINE FLASH_REGION_FVMAIN_OFFSET = 0x00200000
DEFINE FLASH_REGION_FVMAIN_SIZE = 0x001A5000 DEFINE FLASH_REGION_FVMAIN_SIZE = 0x001A5000
DEFINE FLASH_REGION_FV_RECOVERY2_OFFSET = 0x002A5000 DEFINE FLASH_REGION_FV_RECOVERY2_OFFSET = 0x003A5000
DEFINE FLASH_REGION_FV_RECOVERY2_SIZE = 0x0002B000 DEFINE FLASH_REGION_FV_RECOVERY2_SIZE = 0x0002B000
DEFINE FLASH_REGION_FV_RECOVERY_OFFSET = 0x002D0000 DEFINE FLASH_REGION_FV_RECOVERY_OFFSET = 0x003D0000
DEFINE FLASH_REGION_FV_RECOVERY_SIZE = 0x00030000 DEFINE FLASH_REGION_FV_RECOVERY_SIZE = 0x00030000
################################################################################ ################################################################################

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@ -15,46 +15,45 @@
#**/ #**/
[Defines] [Defines]
DEFINE FLASH_BASE = 0xFFD00000 #The base address of the 3Mb FLASH Device. DEFINE FLASH_BASE = 0xFFC00000 #The base address of the 4Mb FLASH Device.
DEFINE FLASH_SIZE = 0x00300000 #The flash size in bytes of the 3Mb FLASH Device. DEFINE FLASH_SIZE = 0x00400000 #The flash size in bytes of the 4Mb FLASH Device.
DEFINE FLASH_BLOCK_SIZE = 0x1000 #The block size in bytes of the 3Mb FLASH Device. DEFINE FLASH_BLOCK_SIZE = 0x1000 #The block size in bytes of the 4Mb FLASH Device.
DEFINE FLASH_NUM_BLOCKS = 0x300 #The number of blocks in 3Mb FLASH Device. DEFINE FLASH_NUM_BLOCKS = 0x400 #The number of blocks in 4Mb FLASH Device.
DEFINE FLASH_AREA_BASE_ADDRESS = 0xFF800000 DEFINE FLASH_AREA_BASE_ADDRESS = 0xFF800000
DEFINE FLASH_AREA_SIZE = 0x00800000 DEFINE FLASH_AREA_SIZE = 0x00800000
DEFINE FLASH_REGION_VLVMICROCODE_OFFSET = 0x00000000 DEFINE FLASH_REGION_VLVMICROCODE_OFFSET = 0x00000000
DEFINE FLASH_REGION_VLVMICROCODE_SIZE = 0x00030000 DEFINE FLASH_REGION_VLVMICROCODE_SIZE = 0x00040000
DEFINE FLASH_REGION_VLVMICROCODE_BASE = 0xFFD00000 DEFINE FLASH_REGION_VLVMICROCODE_BASE = 0xFFC00000
DEFINE FLASH_REGION_VPD_OFFSET = 0x00030000 DEFINE FLASH_REGION_VPD_OFFSET = 0x00130000
DEFINE FLASH_REGION_VPD_SIZE = 0x0003E000 DEFINE FLASH_REGION_VPD_SIZE = 0x0003E000
DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_OFFSET = 0x0006E000 DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_OFFSET = 0x0016E000
DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_SIZE = 0x00002000 DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_SIZE = 0x00002000
DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_OFFSET = 0x00070000 DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_OFFSET = 0x00170000
DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_SIZE = 0x00040000 DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_SIZE = 0x00040000
!if $(MINNOW2_FSP_BUILD) == TRUE !if $(MINNOW2_FSP_BUILD) == TRUE
DEFINE FLASH_REGION_FSPBIN_OFFSET = 0x000B0000 DEFINE FLASH_REGION_FSPBIN_OFFSET = 0x001B0000
DEFINE FLASH_REGION_FSPBIN_SIZE = 0x00048000 DEFINE FLASH_REGION_FSPBIN_SIZE = 0x00048000
DEFINE FLASH_REGION_FSPBIN_BASE = 0xFFDB0000 DEFINE FLASH_REGION_FSPBIN_BASE = 0xFFDB0000
DEFINE FLASH_REGION_AZALIABIN_OFFSET = 0x000F8000 DEFINE FLASH_REGION_AZALIABIN_OFFSET = 0x001F8000
DEFINE FLASH_REGION_AZALIABIN_SIZE = 0x00008000 DEFINE FLASH_REGION_AZALIABIN_SIZE = 0x00008000
DEFINE FLASH_REGION_AZALIABIN_BASE = 0xFFDF8000 DEFINE FLASH_REGION_AZALIABIN_BASE = 0xFFDF8000
!endif !endif
DEFINE FLASH_REGION_FVMAIN_OFFSET = 0x00100000 DEFINE FLASH_REGION_FVMAIN_OFFSET = 0x00200000
DEFINE FLASH_REGION_FVMAIN_SIZE = 0x00196000 DEFINE FLASH_REGION_FVMAIN_SIZE = 0x00196000
DEFINE FLASH_REGION_FV_RECOVERY2_OFFSET = 0x00396000
DEFINE FLASH_REGION_FV_RECOVERY2_OFFSET = 0x00296000
DEFINE FLASH_REGION_FV_RECOVERY2_SIZE = 0x0002C000 DEFINE FLASH_REGION_FV_RECOVERY2_SIZE = 0x0002C000
DEFINE FLASH_REGION_FV_RECOVERY_OFFSET = 0x002C2000 DEFINE FLASH_REGION_FV_RECOVERY_OFFSET = 0x003C2000
DEFINE FLASH_REGION_FV_RECOVERY_SIZE = 0x0003E000 DEFINE FLASH_REGION_FV_RECOVERY_SIZE = 0x0003E000
################################################################################ ################################################################################

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@ -604,9 +604,9 @@
[PcdsFixedAtBuild.common] [PcdsFixedAtBuild.common]
!if $(MINNOW2_FSP_BUILD) == TRUE !if $(MINNOW2_FSP_BUILD) == TRUE
# $(FLASH_REGION_VLVMICROCODE_BASE) # $(FLASH_REGION_VLVMICROCODE_BASE)
gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0xFFD00000 gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0xFFC00000
# $(FLASH_REGION_VLVMICROCODE_SIZE) # $(FLASH_REGION_VLVMICROCODE_SIZE)
gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x00030000 gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x00040000
gFspWrapperTokenSpaceGuid.PcdFlashMicroCodeOffset|0x60 gFspWrapperTokenSpaceGuid.PcdFlashMicroCodeOffset|0x60
# $(FLASH_AREA_BASE_ADDRESS) # $(FLASH_AREA_BASE_ADDRESS)
gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheAddress|0xFF800000 gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheAddress|0xFF800000

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@ -604,9 +604,9 @@
[PcdsFixedAtBuild.common] [PcdsFixedAtBuild.common]
!if $(MINNOW2_FSP_BUILD) == TRUE !if $(MINNOW2_FSP_BUILD) == TRUE
# $(FLASH_REGION_VLVMICROCODE_BASE) # $(FLASH_REGION_VLVMICROCODE_BASE)
gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0xFFD00000 gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0xFFC00000
# $(FLASH_REGION_VLVMICROCODE_SIZE) # $(FLASH_REGION_VLVMICROCODE_SIZE)
gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x00030000 gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x00040000
gFspWrapperTokenSpaceGuid.PcdFlashMicroCodeOffset|0x60 gFspWrapperTokenSpaceGuid.PcdFlashMicroCodeOffset|0x60
# $(FLASH_AREA_BASE_ADDRESS) # $(FLASH_AREA_BASE_ADDRESS)
gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheAddress|0xFF800000 gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheAddress|0xFF800000

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@ -604,9 +604,9 @@
[PcdsFixedAtBuild.common] [PcdsFixedAtBuild.common]
!if $(MINNOW2_FSP_BUILD) == TRUE !if $(MINNOW2_FSP_BUILD) == TRUE
# $(FLASH_REGION_VLVMICROCODE_BASE) # $(FLASH_REGION_VLVMICROCODE_BASE)
gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0xFFD00000 gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0xFFC00000
# $(FLASH_REGION_VLVMICROCODE_SIZE) # $(FLASH_REGION_VLVMICROCODE_SIZE)
gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x00030000 gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x00040000
gFspWrapperTokenSpaceGuid.PcdFlashMicroCodeOffset|0x60 gFspWrapperTokenSpaceGuid.PcdFlashMicroCodeOffset|0x60
# $(FLASH_AREA_BASE_ADDRESS) # $(FLASH_AREA_BASE_ADDRESS)
gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheAddress|0xFF800000 gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheAddress|0xFF800000

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@ -1,6 +1,6 @@
// //
// //
// Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR> // Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
// //
// This program and the accompanying materials are licensed and made available under // This program and the accompanying materials are licensed and made available under
// the terms and conditions of the BSD License that accompanies this distribution. // the terms and conditions of the BSD License that accompanies this distribution.

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@ -12,5 +12,5 @@
# #
HEADER=IFWI_HEADER HEADER=IFWI_HEADER
SEC_VERSION=1.0.2.1067 SEC_VERSION=1.0.2.1060v5

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@ -233,7 +233,7 @@ BOARD_ID=$(grep '^BOARD_ID' Conf/BiosId.env | cut -d ' ' -f 3 | cut -c 1-7)
BIOS_Name="$BOARD_ID"_"$Arch"_"$BUILD_TYPE"_"$VERSION_MAJOR"_"$VERSION_MINOR".ROM BIOS_Name="$BOARD_ID"_"$Arch"_"$BUILD_TYPE"_"$VERSION_MAJOR"_"$VERSION_MINOR".ROM
BIOS_ID="$BOARD_ID"_"$Arch"_"$BUILD_TYPE"_"$VERSION_MAJOR"_"$VERSION_MINOR"_GCC.bin BIOS_ID="$BOARD_ID"_"$Arch"_"$BUILD_TYPE"_"$VERSION_MAJOR"_"$VERSION_MINOR"_GCC.bin
cp -f $BUILD_PATH/FV/VLV.fd $WORKSPACE/$BIOS_Name cp -f $BUILD_PATH/FV/VLV.fd $WORKSPACE/$BIOS_Name
SEC_VERSION=1.0.2.1067 SEC_VERSION=1.0.2.1060v5
cat $IFWI_HEADER_FILE ./Vlv2MiscBinariesPkg/SEC/$SEC_VERSION/VLV_SEC_REGION.bin ./Vlv2MiscBinariesPkg/SEC/$SEC_VERSION/Vacant.bin $BIOS_Name > ./$PLATFORM_PACKAGE/Stitch/$BIOS_ID cat $IFWI_HEADER_FILE ./Vlv2MiscBinariesPkg/SEC/$SEC_VERSION/VLV_SEC_REGION.bin ./Vlv2MiscBinariesPkg/SEC/$SEC_VERSION/Vacant.bin $BIOS_Name > ./$PLATFORM_PACKAGE/Stitch/$BIOS_ID