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ArmPlatformPkg/ArmJunoPkg: Added Juno development board support 

ARM 64bit development platform.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16249 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Olivier Martin 2014-10-27 15:28:07 +00:00 committed by oliviermartin
parent cfdab71f92
commit 9f38945fea
22 changed files with 3508 additions and 0 deletions
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40
ArmPlatformPkg/ArmJunoPkg/ArmJuno.dec Normal file
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#
# Copyright (c) 2013-2014, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
[Defines]
DEC_SPECIFICATION = 0x00010005
PACKAGE_NAME = ArmJunoPkg
PACKAGE_GUID = a1147a20-3144-4f8d-8295-b48311c8e4a4
PACKAGE_VERSION = 0.1
################################################################################
#
# Include Section - list of Include Paths that are provided by this package.
# Comments are used for Keywords and Module Types.
#
# Supported Module Types:
# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
#
################################################################################
[Includes.common]
Include # Root include for the package
[Guids.common]
gArmJunoTokenSpaceGuid = { 0xa1147a20, 0x3144, 0x4f8d, { 0x82, 0x95, 0xb4, 0x83, 0x11, 0xc8, 0xe4, 0xa4 } }
[PcdsFixedAtBuild.common]
gArmJunoTokenSpaceGuid.PcdGenericWatchdogControlBase|0x2A440000|UINT32|0x00000001
gArmJunoTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2A450000|UINT32|0x00000002
gArmJunoTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|93|UINT32|0x00000003
gArmJunoTokenSpaceGuid.PcdSynopsysUsbOhciBaseAddress|0x7FFB0000|UINT32|0x00000004
gArmJunoTokenSpaceGuid.PcdSynopsysUsbEhciBaseAddress|0x7FFC0000|UINT32|0x00000005

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ArmPlatformPkg/ArmJunoPkg/ArmJuno.dsc Normal file
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#
# Copyright (c) 2013-2014, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
################################################################################
#
# Defines Section - statements that will be processed to create a Makefile.
#
################################################################################
[Defines]
PLATFORM_NAME = ArmJuno
PLATFORM_GUID = ca0722fd-7d3d-45ea-948c-d62b2199807d
PLATFORM_VERSION = 0.1
DSC_SPECIFICATION = 0x00010005
OUTPUT_DIRECTORY = Build/ArmJuno
SUPPORTED_ARCHITECTURES = AARCH64|ARM
BUILD_TARGETS = DEBUG|RELEASE
SKUID_IDENTIFIER = DEFAULT
FLASH_DEFINITION = ArmPlatformPkg/ArmJunoPkg/ArmJuno.fdf
# On RTSM, most peripherals are VExpress Motherboard peripherals
!include ArmPlatformPkg/ArmVExpressPkg/ArmVExpress.dsc.inc
[LibraryClasses.common]
ArmPlatformLib|ArmPlatformPkg/ArmJunoPkg/Library/ArmJunoLib/ArmJunoLib.inf
ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf
NorFlashPlatformLib|ArmPlatformPkg/ArmJunoPkg/Library/NorFlashJunoLib/NorFlashJunoLib.inf
EfiResetSystemLib|ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.inf
TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
# USB Requirements
UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
[LibraryClasses.ARM]
ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf
[LibraryClasses.AARCH64]
ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64Lib.inf
[LibraryClasses.common.SEC]
PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf
LzmaDecompressLib|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf
HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf
PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf
PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf
[BuildOptions]
GCC:*_*_*_PLATFORM_FLAGS == -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmJunoPkg/Include
################################################################################
#
# Pcd Section - list of all EDK II PCD Entries defined by this Platform
#
################################################################################
[PcdsFeatureFlag.common]
gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|TRUE
## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
# It could be set FALSE to save size.
gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE
[PcdsFixedAtBuild.common]
gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Juno"
gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"ArmJuno"
#
# NV Storage PCDs. Use base of 0x08000000 for NOR0
#
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0x0BFC0000
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00010000
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0x0BFD0000
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00010000
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x0BFE0000
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00010000
# System Memory (2GB - 16MB of Trusted DRAM at the top of the 32bit address space)
gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000
gArmTokenSpaceGuid.PcdSystemMemorySize|0x7F000000
# Juno Dual-Cluster profile
gArmPlatformTokenSpaceGuid.PcdCoreCount|6
gArmPlatformTokenSpaceGuid.PcdClusterCount|2
gArmTokenSpaceGuid.PcdVFPEnabled|1
#
# ARM PrimeCell
#
## PL011 - Serial Terminal
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x7FF80000
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
gArmPlatformTokenSpaceGuid.PL011UartInteger|4
gArmPlatformTokenSpaceGuid.PL011UartFractional|0
## PL031 RealTimeClock
gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x1C170000
# LAN9118 Ethernet Driver
gEmbeddedTokenSpaceGuid.PcdLan9118DxeBaseAddress|0x18000000
gEmbeddedTokenSpaceGuid.PcdLan9118DefaultMacAddress|0x1215161822242628
#
# ARM General Interrupt Controller
#
gArmTokenSpaceGuid.PcdGicDistributorBase|0x2C010000
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x2C02F000
# List of Device Paths that support BootMonFs
gArmPlatformTokenSpaceGuid.PcdBootMonFsSupportedDevicePaths|L"VenHw(E7223039-5836-41E1-B542-D7EC736C5E59)"
#
# ARM OS Loader
#
gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Linux from NOR Flash"
gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(E7223039-5836-41E1-B542-D7EC736C5E59)/Image"
gArmPlatformTokenSpaceGuid.PcdFdtDevicePath|L"VenHw(E7223039-5836-41E1-B542-D7EC736C5E59)/juno.dtb"
gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|"console=ttyAMA0,115200 earlyprintk=pl011,0x7ff80000 root=/dev/sda1 rootwait verbose debug"
gArmPlatformTokenSpaceGuid.PcdDefaultBootType|2
# Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut)
gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi();VenHw(CE660500-824D-11E0-AC72-0002A5D5C51B)"
gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi()"
#
# ARM Architectural Timer Frequency
#
gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|50000000
gEmbeddedTokenSpaceGuid.PcdMetronomeTickPeriod|1000
[PcdsPatchableInModule]
# Console Resolution (Full HD)
gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|1920
gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|1080
################################################################################
#
# Components Section - list of all EDK II Modules needed by this Platform
#
################################################################################
[Components.common]
#
# PEI Phase modules
#
ArmPlatformPkg/PrePi/PeiMPCore.inf {
<LibraryClasses>
ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/PrePi/PrePiArmPlatformGlobalVariableLib.inf
}
#
# DXE
#
MdeModulePkg/Core/Dxe/DxeMain.inf {
<LibraryClasses>
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
}
#
# Architectural Protocols
#
ArmPkg/Drivers/CpuDxe/CpuDxe.inf
MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
EmbeddedPkg/SerialDxe/SerialDxe.inf
MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf
ArmPkg/Drivers/TimerDxe/TimerDxe.inf
ArmPlatformPkg/ArmJunoPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf
#
# Semi-hosting filesystem
#
ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
#
# FAT filesystem + GPT/MBR partitioning
#
MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
# Networking stack
EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118Dxe.inf
#
# Usb Support
#
MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
#
# Juno platform driver
#
ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.inf
#
# Bds
#
MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
ArmPlatformPkg/Bds/Bds.inf

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ArmPlatformPkg/ArmJunoPkg/ArmJuno.fdf Normal file
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#
# Copyright (c) 2013-2014, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
################################################################################
#
# FD Section
# The [FD] Section is made up of the definition statements and a
# description of what goes into the Flash Device Image. Each FD section
# defines one flash "device" image. A flash device image may be one of
# the following: Removable media bootable image (like a boot floppy
# image,) an Option ROM image (that would be "flashed" into an add-in
# card,) a System "Flash" image (that would be burned into a system's
# flash) or an Update ("Capsule") image that will be used to update and
# existing system flash.
#
################################################################################
[FD.BL33_AP_UEFI]
BaseAddress = 0xE0000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash.
Size = 0x000F0000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device
ErasePolarity = 1
# This one is tricky, it must be: BlockSize * NumBlocks = Size
BlockSize = 0x00001000
NumBlocks = 0xF0
################################################################################
#
# Following are lists of FD Region layout which correspond to the locations of different
# images within the flash device.
#
# Regions must be defined in ascending order and may not overlap.
#
# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
# the pipe "|" character, followed by the size of the region, also in hex with the leading
# "0x" characters. Like:
# Offset|Size
# PcdOffsetCName|PcdSizeCName
# RegionType <FV, DATA, or FILE>
#
################################################################################
0x00000000|0x000F0000
gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
FV = FVMAIN_COMPACT
################################################################################
#
# FV Section
#
# [FV] section is used to define what components or modules are placed within a flash
# device file. This section also defines order the components and modules are positioned
# within the image. The [FV] section consists of define statements, set statements and
# module statements.
#
################################################################################
[FV.FvMain]
BlockSize = 0x40
NumBlocks = 0 # This FV gets compressed so make it just big enough
FvAlignment = 8 # FV alignment and FV attributes setting.
ERASE_POLARITY = 1
MEMORY_MAPPED = TRUE
STICKY_WRITE = TRUE
LOCK_CAP = TRUE
LOCK_STATUS = TRUE
WRITE_DISABLED_CAP = TRUE
WRITE_ENABLED_CAP = TRUE
WRITE_STATUS = TRUE
WRITE_LOCK_CAP = TRUE
WRITE_LOCK_STATUS = TRUE
READ_DISABLED_CAP = TRUE
READ_ENABLED_CAP = TRUE
READ_STATUS = TRUE
READ_LOCK_CAP = TRUE
READ_LOCK_STATUS = TRUE
INF MdeModulePkg/Core/Dxe/DxeMain.inf
#
# PI DXE Drivers producing Architectural Protocols (EFI Services)
#
INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
#
# Multiple Console IO support
#
INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
INF EmbeddedPkg/SerialDxe/SerialDxe.inf
INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
INF ArmPlatformPkg/ArmJunoPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf
# NOR Flash driver
INF ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf
# Versatile Express FileSystem
INF ArmPlatformPkg/FileSystem/BootMonFs/BootMonFs.inf
#
# FAT filesystem + GPT/MBR partitioning
#
INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
INF FatBinPkg/EnhancedFatDxe/Fat.inf
INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
#
# Usb Support
#
INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
#
# Networking stack
#
INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
INF MdeModulePkg/Universal/Network/Ip4ConfigDxe/Ip4ConfigDxe.inf
INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
INF EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118Dxe.inf
#
# UEFI applications
#
INF ShellBinPkg/UefiShell/UefiShell.inf
#
# Juno platform driver
#
INF ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.inf
#
# Bds
#
INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
INF ArmPlatformPkg/Bds/Bds.inf
[FV.FVMAIN_COMPACT]
FvAlignment = 8
ERASE_POLARITY = 1
MEMORY_MAPPED = TRUE
STICKY_WRITE = TRUE
LOCK_CAP = TRUE
LOCK_STATUS = TRUE
WRITE_DISABLED_CAP = TRUE
WRITE_ENABLED_CAP = TRUE
WRITE_STATUS = TRUE
WRITE_LOCK_CAP = TRUE
WRITE_LOCK_STATUS = TRUE
READ_DISABLED_CAP = TRUE
READ_ENABLED_CAP = TRUE
READ_STATUS = TRUE
READ_LOCK_CAP = TRUE
READ_LOCK_STATUS = TRUE
INF ArmPlatformPkg/PrePi/PeiMPCore.inf
FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
SECTION FV_IMAGE = FVMAIN
}
}
################################################################################
#
# Rules are use with the [FV] section's module INF type to define
# how an FFS file is created for a given INF file. The following Rule are the default
# rules for the different module type. User can add the customized rules to define the
# content of the FFS file.
#
################################################################################
############################################################################
# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section #
############################################################################
#
#[Rule.Common.DXE_DRIVER]
# FILE DRIVER = $(NAMED_GUID) {
# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
# COMPRESS PI_STD {
# GUIDED {
# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
# UI STRING="$(MODULE_NAME)" Optional
# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
# }
# }
# }
#
############################################################################
#
# These SEC rules are used for ArmPlatformPkg/PrePi module.
# ArmPlatformPkg/PrePi is declared as a SEC module to make GenFv patch the
# UEFI Firmware to jump to ArmPlatformPkg/PrePi entrypoint
#
[Rule.ARM.SEC]
FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
TE TE Align = 32 $(INF_OUTPUT)/$(MODULE_NAME).efi
}
[Rule.AARCH64.SEC]
FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
TE TE Align = 4K $(INF_OUTPUT)/$(MODULE_NAME).efi
}
# A shim specific rule is required to ensure the alignment is 4K.
# Otherwise BaseTools pick up the AArch32 alignment (ie: 32)
[Rule.ARM.SEC.SHIM]
FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
TE TE Align = 4K $(INF_OUTPUT)/$(MODULE_NAME).efi
}
[Rule.Common.PEI_CORE]
FILE PEI_CORE = $(NAMED_GUID) {
TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING ="$(MODULE_NAME)" Optional
}
[Rule.Common.PEIM]
FILE PEIM = $(NAMED_GUID) {
PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING="$(MODULE_NAME)" Optional
}
[Rule.Common.PEIM.TIANOCOMPRESSED]
FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING="$(MODULE_NAME)" Optional
}
}
[Rule.Common.DXE_CORE]
FILE DXE_CORE = $(NAMED_GUID) {
PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING="$(MODULE_NAME)" Optional
}
[Rule.Common.UEFI_DRIVER]
FILE DRIVER = $(NAMED_GUID) {
DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING="$(MODULE_NAME)" Optional
}
[Rule.Common.DXE_DRIVER]
FILE DRIVER = $(NAMED_GUID) {
DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING="$(MODULE_NAME)" Optional
}
[Rule.Common.DXE_RUNTIME_DRIVER]
FILE DRIVER = $(NAMED_GUID) {
DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING="$(MODULE_NAME)" Optional
}
[Rule.Common.UEFI_APPLICATION]
FILE APPLICATION = $(NAMED_GUID) {
UI STRING ="$(MODULE_NAME)" Optional
PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
}
[Rule.Common.UEFI_DRIVER.BINARY]
FILE DRIVER = $(NAMED_GUID) {
DXE_DEPEX DXE_DEPEX Optional |.depex
PE32 PE32 |.efi
UI STRING="$(MODULE_NAME)" Optional
VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
}
[Rule.Common.UEFI_APPLICATION.BINARY]
FILE APPLICATION = $(NAMED_GUID) {
PE32 PE32 |.efi
UI STRING="$(MODULE_NAME)" Optional
VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
}

81
ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.c Normal file
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/** @file
*
* Copyright (c) 2013-2014, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#include "ArmJunoDxeInternal.h"
#include <Library/ArmShellCmdLib.h>
EFI_STATUS
EFIAPI
ArmJunoEntryPoint (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
EFI_PHYSICAL_ADDRESS HypBase;
Status = PciEmulationEntryPoint ();
if (EFI_ERROR (Status)) {
return Status;
}
//
// If a hypervisor has been declared then we need to make sure its region is protected at runtime
//
// Note: This code is only a workaround for our dummy hypervisor (ArmPkg/Extra/AArch64ToAArch32Shim/)
// that does not set up (yet) the stage 2 translation table to hide its own memory to EL1.
//
if (FixedPcdGet32 (PcdHypFvSize) != 0) {
// Ensure the hypervisor region is strictly contained into a EFI_PAGE_SIZE-aligned region.
// The memory must be a multiple of EFI_PAGE_SIZE to ensure we do not reserve more memory than the hypervisor itself.
// A UEFI Runtime region size granularity cannot be smaller than EFI_PAGE_SIZE. If the hypervisor size is not rounded
// to this size then there is a risk some non-runtime memory could be visible to the OS view.
if (((FixedPcdGet32 (PcdHypFvSize) & EFI_PAGE_MASK) == 0) && ((FixedPcdGet32 (PcdHypFvBaseAddress) & EFI_PAGE_MASK) == 0)) {
// The memory needs to be declared because the DXE core marked it as reserved and removed it from the memory space
// as it contains the Firmware.
Status = gDS->AddMemorySpace (
EfiGcdMemoryTypeSystemMemory,
FixedPcdGet32 (PcdHypFvBaseAddress), FixedPcdGet32 (PcdHypFvSize),
EFI_MEMORY_WB | EFI_MEMORY_RUNTIME
);
if (!EFI_ERROR (Status)) {
// We allocate the memory to ensure it is marked as runtime memory
HypBase = FixedPcdGet32 (PcdHypFvBaseAddress);
Status = gBS->AllocatePages (AllocateAddress, EfiRuntimeServicesCode,
EFI_SIZE_TO_PAGES (FixedPcdGet32 (PcdHypFvSize)), &HypBase);
}
} else {
// The hypervisor must be contained into a EFI_PAGE_SIZE-aligned region and its size must also be aligned
// on a EFI_PAGE_SIZE boundary (ie: 4KB).
Status = EFI_UNSUPPORTED;
ASSERT_EFI_ERROR (Status);
}
if (EFI_ERROR (Status)) {
return Status;
}
}
// Install dynamic Shell command to run baremetal binaries.
Status = ShellDynCmdRunAxfInstall (ImageHandle);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "ArmJunoDxe: Failed to install ShellDynCmdRunAxf\n"));
}
// Try to install the Flat Device Tree (FDT). This function actually installs the
// UEFI Driver Binding Protocol.
Status = JunoFdtInstall (ImageHandle);
return Status;
}

76
ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.inf Normal file
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#
# Copyright (c) 2013-2014, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = ArmJunoDxe
FILE_GUID = 1484ebe8-2681-45f1-a2e5-12ecad893b62
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
ENTRY_POINT = ArmJunoEntryPoint
[Sources.common]
ArmJunoDxe.c
InstallFdt.c
PciEmulation.c
PciRootBridgeIo.c
[Packages]
ArmPkg/ArmPkg.dec
ArmPlatformPkg/ArmPlatformPkg.dec
ArmPlatformPkg/ArmJunoPkg/ArmJuno.dec
EmbeddedPkg/EmbeddedPkg.dec
MdePkg/MdePkg.dec
[LibraryClasses]
ArmShellCmdRunAxfLib
BaseMemoryLib
BdsLib
DebugLib
DmaLib
DxeServicesTableLib
FdtLib
IoLib
PcdLib
PrintLib
SerialPortLib
UefiBootServicesTableLib
UefiRuntimeServicesTableLib
UefiLib
UefiDriverEntryPoint
[Guids]
gArmGlobalVariableGuid
gEfiEndOfDxeEventGroupGuid
gEfiFileInfoGuid
gFdtTableGuid
[Protocols]
gEfiBlockIoProtocolGuid
gEfiDevicePathFromTextProtocolGuid
gEfiPciIoProtocolGuid
gEfiSimpleFileSystemProtocolGuid
[FixedPcd]
gArmTokenSpaceGuid.PcdSystemMemoryBase
gArmTokenSpaceGuid.PcdSystemMemorySize
gArmTokenSpaceGuid.PcdHypFvBaseAddress
gArmTokenSpaceGuid.PcdHypFvSize
gArmJunoTokenSpaceGuid.PcdSynopsysUsbEhciBaseAddress
gArmJunoTokenSpaceGuid.PcdSynopsysUsbOhciBaseAddress
gArmPlatformTokenSpaceGuid.PcdFdtDevicePath
[Depex]
TRUE

36
ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxeInternal.h Normal file
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/** @file
*
* Copyright (c) 2013-2014, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#ifndef __ARM_JUNO_DXE_INTERNAL_H__
#define __ARM_JUNO_DXE_INTERNAL_H__
#include <Uefi.h>
#include <Library/DebugLib.h>
#include <Library/DxeServicesTableLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <IndustryStandard/Acpi.h>
EFI_STATUS
PciEmulationEntryPoint (
VOID
);
EFI_STATUS
JunoFdtInstall (
IN EFI_HANDLE ImageHandle
);
#endif // __ARM_JUNO_DXE_INTERNAL_H__

423
ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/InstallFdt.c Normal file
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/** @file
*
* Copyright (c) 2014, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#include "ArmJunoDxeInternal.h"
#include <Protocol/BlockIo.h>
#include <Protocol/DevicePathFromText.h>
#include <Protocol/DriverBinding.h>
#include <Protocol/SimpleFileSystem.h>
#include <Library/BaseMemoryLib.h>
#include <Library/BdsLib.h>
#include <Library/DevicePathLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/PrintLib.h>
#include <Library/SerialPortLib.h>
#include <Library/UefiRuntimeServicesTableLib.h>
#include <Guid/ArmGlobalVariableHob.h>
#include <Guid/EventGroup.h>
#include <Guid/Fdt.h>
#include <Guid/FileInfo.h>
#include <libfdt.h>
#define FDT_DEFAULT_FILENAME L"juno"
#define IS_DEVICE_PATH_NODE(node,type,subtype) (((node)->Type == (type)) && ((node)->SubType == (subtype)))
// Hardware Vendor Device Path node for the Juno NOR Flash. We use the Juno NOR Flash if the user
// has not specified another filesystem location into the UEFI Variable 'Fdt'.
// The Juno NOR Flash has its own filesystem format (supported by ArmPlatformPkg/FileSystem/BootMonFs).
STATIC CONST struct {
VENDOR_DEVICE_PATH NorGuid;
EFI_DEVICE_PATH End;
} mJunoNorFlashDevicePath = {
{
{ HARDWARE_DEVICE_PATH, HW_VENDOR_DP, { sizeof (VENDOR_DEVICE_PATH), 0 } },
{0xE7223039, 0x5836, 0x41E1, { 0xB5, 0x42, 0xD7, 0xEC, 0x73, 0x6C, 0x5E, 0x59} }
},
{ END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, { sizeof (EFI_DEVICE_PATH_PROTOCOL), 0 } }
};
STATIC EFI_DEVICE_PATH* mFdtFileSystemDevicePath = NULL;
STATIC CHAR16* mFdtFileName = NULL;
STATIC BOOLEAN mFdtTableInstalled = FALSE;
/**
See definition EFI_DRIVER_BINDING_PROTOCOL.Supported()
**/
EFI_STATUS
EFIAPI
JunoFdtSupported (
IN EFI_DRIVER_BINDING_PROTOCOL *DriverBinding,
IN EFI_HANDLE ControllerHandle,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath OPTIONAL
)
{
EFI_STATUS Status;
EFI_DEVICE_PATH_PROTOCOL *DevicePath;
//
// Check if the Handle support the Simple File System Protocol
//
Status = gBS->OpenProtocol (
ControllerHandle,
&gEfiSimpleFileSystemProtocolGuid,
NULL,
gImageHandle,
ControllerHandle,
EFI_OPEN_PROTOCOL_TEST_PROTOCOL
);
if (EFI_ERROR (Status)) {
return Status;
}
// Check if a DevicePath is attached to the handle
Status = gBS->OpenProtocol (
ControllerHandle,
&gEfiDevicePathProtocolGuid,
(VOID **)&DevicePath,
gImageHandle,
ControllerHandle,
EFI_OPEN_PROTOCOL_BY_DRIVER
);
if (EFI_ERROR (Status)) {
return Status;
}
// Check if the Device Path is the one from the NOR Flash
if (CompareMem (mFdtFileSystemDevicePath, DevicePath, GetDevicePathSize (mFdtFileSystemDevicePath)) != 0) {
return EFI_NOT_FOUND;
}
gBS->CloseProtocol (ControllerHandle, &gEfiDevicePathProtocolGuid, gImageHandle, ControllerHandle);
return Status;
}
/**
This function is used to print messages back to the user.
We use the Serial terminal for these messages as the gST->ConOut might not be initialized at this stage.
@param Message Message to display to the user
**/
STATIC
VOID
PrintMessage (
IN CHAR8* Message,
...
)
{
UINTN CharCount;
CHAR8 Buffer[100];
VA_LIST Marker;
VA_START (Marker, Message);
CharCount = AsciiVSPrint (Buffer, sizeof (Buffer), Message, Marker);
VA_END (Marker);
SerialPortWrite ((UINT8*)Buffer, CharCount);
}
/**
See definition EFI_DRIVER_BINDING_PROTOCOL.Start ()
**/
EFI_STATUS
EFIAPI
JunoFdtStart (
IN EFI_DRIVER_BINDING_PROTOCOL *DriverBinding,
IN EFI_HANDLE ControllerHandle,
IN EFI_DEVICE_PATH_PROTOCOL *DevicePath OPTIONAL
)
{
EFI_STATUS Status;
EFI_SIMPLE_FILE_SYSTEM_PROTOCOL *BootMonFs;
EFI_FILE_PROTOCOL *Fs;
EFI_FILE_PROTOCOL *File;
UINTN Size;
EFI_PHYSICAL_ADDRESS FdtBlob;
EFI_FILE_INFO *FileInfo;
if (mFdtTableInstalled) {
return EFI_ALREADY_STARTED;
}
Status = gBS->OpenProtocol (
ControllerHandle,
&gEfiSimpleFileSystemProtocolGuid,
(VOID**)&BootMonFs,
gImageHandle,
ControllerHandle,
EFI_OPEN_PROTOCOL_BY_DRIVER
);
if (EFI_ERROR (Status)) {
return Status;
}
// Try to Open the volume and get root directory
Status = BootMonFs->OpenVolume (BootMonFs, &Fs);
if (EFI_ERROR (Status)) {
PrintMessage ("Warning: Fail to open file system that should contain FDT file.\n");
goto UNLOAD_PROTOCOL;
}
File = NULL;
Status = Fs->Open (Fs, &File, mFdtFileName, EFI_FILE_MODE_READ, 0);
if (EFI_ERROR (Status)) {
PrintMessage ("Warning: Fail to load FDT file '%s'.\n", mFdtFileName);
goto UNLOAD_PROTOCOL;
}
Size = 0;
File->GetInfo (File, &gEfiFileInfoGuid, &Size, NULL);
FileInfo = AllocatePool (Size);
Status = File->GetInfo (File, &gEfiFileInfoGuid, &Size, FileInfo);
if (EFI_ERROR (Status)) {
goto UNLOAD_PROTOCOL;
}
// Get the file size
Size = FileInfo->FileSize;
FreePool (FileInfo);
// The FDT blob is attached to the Configuration Table. It is better to load it as Runtime Service Data
// to prevent the kernel to overwrite its data
Status = gBS->AllocatePages (AllocateAnyPages, EfiRuntimeServicesData, EFI_SIZE_TO_PAGES (Size), &FdtBlob);
if (!EFI_ERROR (Status)) {
Status = File->Read (File, &Size, (VOID*)(UINTN)(FdtBlob));
if (EFI_ERROR (Status)) {
gBS->FreePages (FdtBlob, EFI_SIZE_TO_PAGES (Size));
} else {
// Check the FDT header is valid. We only make this check in DEBUG mode in case the FDT header change on
// production device and this ASSERT() becomes not valid.
ASSERT (fdt_check_header ((VOID*)(UINTN)(FdtBlob)) == 0);
// Ensure the Size of the Device Tree is smaller than the size of the read file
ASSERT ((UINTN)fdt_totalsize ((VOID*)(UINTN)FdtBlob) <= Size);
// Install the FDT into the Configuration Table
Status = gBS->InstallConfigurationTable (&gFdtTableGuid, (VOID*)(UINTN)(FdtBlob));
if (!EFI_ERROR (Status)) {
mFdtTableInstalled = TRUE;
}
}
}
UNLOAD_PROTOCOL:
// We do not need the FileSystem protocol
gBS->CloseProtocol (
ControllerHandle,
&gEfiSimpleFileSystemProtocolGuid,
DriverBinding->ImageHandle,
ControllerHandle);
return Status;
}
/**
See definition EFI_DRIVER_BINDING_PROTOCOL.Stop()
**/
EFI_STATUS
EFIAPI
JunoFdtStop (
IN EFI_DRIVER_BINDING_PROTOCOL *DriverBinding,
IN EFI_HANDLE ControllerHandle,
IN UINTN NumberOfChildren,
IN EFI_HANDLE *ChildHandleBuffer OPTIONAL
)
{
UINTN Index;
VOID* FdtBlob;
UINTN FdtSize;
// Look for FDT Table
for (Index = 0; Index < gST->NumberOfTableEntries; Index++) {
// Check for correct GUID type
if (CompareGuid (&gFdtTableGuid, &(gST->ConfigurationTable[Index].VendorGuid))) {
FdtBlob = gST->ConfigurationTable[Index].VendorTable;
FdtSize = (UINTN)fdt_totalsize (FdtBlob);
// Uninstall the FDT Configuration Table
gBS->InstallConfigurationTable (&gFdtTableGuid, NULL);
// Free the memory
gBS->FreePages ((EFI_PHYSICAL_ADDRESS)(UINTN)FdtBlob, EFI_SIZE_TO_PAGES (FdtSize));
return EFI_SUCCESS;
}
}
return EFI_NOT_FOUND;
}
//
// Driver Binding Protocol for Juno FDT support
//
EFI_DRIVER_BINDING_PROTOCOL mJunoFdtBinding = {
JunoFdtSupported,
JunoFdtStart,
JunoFdtStop,
0xa,
NULL,
NULL
};
/**
Notification function of EFI_END_OF_DXE_EVENT_GROUP_GUID event group.
This is a notification function registered on EFI_END_OF_DXE_EVENT_GROUP_GUID event group.
@param Event Event whose notification function is being invoked.
@param Context Pointer to the notification function's context.
**/
STATIC
VOID
EFIAPI
OnEndOfDxe (
EFI_EVENT Event,
VOID *Context
)
{
EFI_DEVICE_PATH *DevicePathNode;
EFI_HANDLE Handle;
EFI_STATUS Status;
UINTN VariableSize;
CHAR16* FdtDevicePathStr;
EFI_DEVICE_PATH_FROM_TEXT_PROTOCOL *EfiDevicePathFromTextProtocol;
//
// Read the 'FDT' UEFI Variable to know where we should we read the blob from.
// The 'Fdt' variable contains either the full device path or only the filename of the FDT.
// If 'Fdt' only contains the filename then we assume its location is on the NOR Flash.
//
VariableSize = 0;
Status = gRT->GetVariable (L"Fdt", &gArmGlobalVariableGuid, NULL, &VariableSize, mFdtFileSystemDevicePath);
if (Status == EFI_BUFFER_TOO_SMALL) {
// Get the environment variable value
mFdtFileSystemDevicePath = AllocatePool (VariableSize);
if (mFdtFileSystemDevicePath != NULL) {
Status = gRT->GetVariable (L"Fdt", &gArmGlobalVariableGuid, NULL, &VariableSize, mFdtFileSystemDevicePath);
if (EFI_ERROR (Status)) {
FreePool (mFdtFileSystemDevicePath);
ASSERT_EFI_ERROR (Status);
return;
}
} else {
ASSERT_EFI_ERROR (EFI_OUT_OF_RESOURCES);
return;
}
} else if (Status == EFI_NOT_FOUND) {
// If the 'Fdt' variable does not exist then we get the FDT location from the PCD
FdtDevicePathStr = (CHAR16*)PcdGetPtr (PcdFdtDevicePath);
Status = gBS->LocateProtocol (&gEfiDevicePathFromTextProtocolGuid, NULL, (VOID **)&EfiDevicePathFromTextProtocol);
if (EFI_ERROR (Status)) {
ASSERT_EFI_ERROR (Status);
return;
}
// Conversion of the Device Path string into EFI Device Path
mFdtFileSystemDevicePath = EfiDevicePathFromTextProtocol->ConvertTextToDevicePath (FdtDevicePathStr);
}
if (mFdtFileSystemDevicePath != NULL) {
// Look for the FDT filename that should be contained into the FilePath device path node
DevicePathNode = mFdtFileSystemDevicePath;
while (!IsDevicePathEnd (DevicePathNode)) {
if (IS_DEVICE_PATH_NODE (DevicePathNode, MEDIA_DEVICE_PATH, MEDIA_FILEPATH_DP)) {
// Extract the name from the File Path Node. The name of the Filename is the size of the
// device path node minus the size of the device path node header.
mFdtFileName = AllocateCopyPool (
DevicePathNodeLength (DevicePathNode) - sizeof(EFI_DEVICE_PATH_PROTOCOL),
((FILEPATH_DEVICE_PATH*)DevicePathNode)->PathName);
if (mFdtFileName == NULL) {
ASSERT_EFI_ERROR (EFI_OUT_OF_RESOURCES);
return;
}
// We remove the FilePath device path node from the FileSystem Device Path
// because it will never match a device path installed by the FileSystem driver
SetDevicePathEndNode (DevicePathNode);
break;
}
DevicePathNode = NextDevicePathNode (DevicePathNode);
}
// The UEFI Variable might just contain the FDT filename. In this case we assume the FileSystem is
// the NOR Flash based one (ie: BootMonFs).
// If it was only containing the FilePath device node then the previous condition should have
// replaced it by the End Device Path Node.
if (IsDevicePathEndType (mFdtFileSystemDevicePath)) {
mFdtFileSystemDevicePath = (EFI_DEVICE_PATH*)&mJunoNorFlashDevicePath;
}
} else {
// Fallback on the NOR Flash filesystem
mFdtFileSystemDevicePath = (EFI_DEVICE_PATH*)&mJunoNorFlashDevicePath;
}
// If the FDT FileName has been provided during the FileSystem identification
if (mFdtFileName == NULL) {
mFdtFileName = AllocateCopyPool (StrSize (FDT_DEFAULT_FILENAME), FDT_DEFAULT_FILENAME);
if (mFdtFileName == NULL) {
ASSERT_EFI_ERROR (Status);
return;
}
}
// Install the Binding protocol to verify when the FileSystem that contains the FDT has been installed
Status = gBS->InstallMultipleProtocolInterfaces (
&gImageHandle,
&gEfiDriverBindingProtocolGuid, &mJunoFdtBinding,
NULL
);
if (EFI_ERROR (Status)) {
ASSERT_EFI_ERROR (Status);
return;
}
//
// Force to connect the FileSystem that contains the FDT
//
BdsConnectDevicePath (mFdtFileSystemDevicePath, &Handle, NULL);
}
EFI_STATUS
JunoFdtInstall (
IN EFI_HANDLE ImageHandle
)
{
EFI_STATUS Status;
EFI_EVENT EndOfDxeEvent;
// Register the event handling function to set the End Of DXE flag.
// We wait until the end of the DXE phase to load the FDT to make sure
// all the required drivers (NOR Flash, UEFI Variable, BootMonFs) are dispatched
Status = gBS->CreateEventEx (
EVT_NOTIFY_SIGNAL,
TPL_CALLBACK,
OnEndOfDxe,
NULL,
&gEfiEndOfDxeEventGroupGuid,
&EndOfDxeEvent
);
ASSERT_EFI_ERROR (Status);
return Status;
}

486
ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/PciEmulation.c Normal file
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/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
Copyright (c) 2013 - 2014, ARM Ltd. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "PciEmulation.h"
#define HOST_CONTROLLER_OPERATION_REG_SIZE 0x44
typedef struct {
ACPI_HID_DEVICE_PATH AcpiDevicePath;
PCI_DEVICE_PATH PciDevicePath;
EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
} EFI_PCI_IO_DEVICE_PATH;
typedef struct {
UINT32 Signature;
EFI_PCI_IO_DEVICE_PATH DevicePath;
EFI_PCI_IO_PROTOCOL PciIoProtocol;
PCI_TYPE00 *ConfigSpace;
PCI_ROOT_BRIDGE RootBridge;
UINTN Segment;
} EFI_PCI_IO_PRIVATE_DATA;
#define EFI_PCI_IO_PRIVATE_DATA_SIGNATURE SIGNATURE_32('p', 'c', 'i', 'o')
#define EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(a) CR (a, EFI_PCI_IO_PRIVATE_DATA, PciIoProtocol, EFI_PCI_IO_PRIVATE_DATA_SIGNATURE)
EFI_PCI_IO_DEVICE_PATH PciIoDevicePathTemplate =
{
{
{ ACPI_DEVICE_PATH, ACPI_DP, { sizeof (ACPI_HID_DEVICE_PATH), 0 } },
EISA_PNP_ID(0x0A03), // HID
0 // UID
},
{
{ HARDWARE_DEVICE_PATH, HW_PCI_DP, { sizeof (PCI_DEVICE_PATH), 0 } },
0,
0
},
{ END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, { sizeof (EFI_DEVICE_PATH_PROTOCOL), 0} }
};
STATIC
VOID
ConfigureUSBHost (
VOID
)
{
}
EFI_STATUS
PciIoPollMem (
IN EFI_PCI_IO_PROTOCOL *This,
IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
IN UINT8 BarIndex,
IN UINT64 Offset,
IN UINT64 Mask,
IN UINT64 Value,
IN UINT64 Delay,
OUT UINT64 *Result
)
{
ASSERT (FALSE);
return EFI_UNSUPPORTED;
}
EFI_STATUS
PciIoPollIo (
IN EFI_PCI_IO_PROTOCOL *This,
IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
IN UINT8 BarIndex,
IN UINT64 Offset,
IN UINT64 Mask,
IN UINT64 Value,
IN UINT64 Delay,
OUT UINT64 *Result
)
{
ASSERT (FALSE);
return EFI_UNSUPPORTED;
}
EFI_STATUS
PciIoMemRead (
IN EFI_PCI_IO_PROTOCOL *This,
IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
IN UINT8 BarIndex,
IN UINT64 Offset,
IN UINTN Count,
IN OUT VOID *Buffer
)
{
EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS (This);
return PciRootBridgeIoMemRead (&Private->RootBridge.Io,
(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
Private->ConfigSpace->Device.Bar[BarIndex] + Offset, //Fix me ConfigSpace
Count,
Buffer
);
}
EFI_STATUS
PciIoMemWrite (
IN EFI_PCI_IO_PROTOCOL *This,
IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
IN UINT8 BarIndex,
IN UINT64 Offset,
IN UINTN Count,
IN OUT VOID *Buffer
)
{
EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS (This);
return PciRootBridgeIoMemWrite (&Private->RootBridge.Io,
(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
Private->ConfigSpace->Device.Bar[BarIndex] + Offset, //Fix me ConfigSpace
Count,
Buffer
);
}
EFI_STATUS
PciIoIoRead (
IN EFI_PCI_IO_PROTOCOL *This,
IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
IN UINT8 BarIndex,
IN UINT64 Offset,
IN UINTN Count,
IN OUT VOID *Buffer
)
{
ASSERT (FALSE);
return EFI_UNSUPPORTED;
}
EFI_STATUS
PciIoIoWrite (
IN EFI_PCI_IO_PROTOCOL *This,
IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
IN UINT8 BarIndex,
IN UINT64 Offset,
IN UINTN Count,
IN OUT VOID *Buffer
)
{
ASSERT (FALSE);
return EFI_UNSUPPORTED;
}
EFI_STATUS
PciIoPciRead (
IN EFI_PCI_IO_PROTOCOL *This,
IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
IN UINT32 Offset,
IN UINTN Count,
IN OUT VOID *Buffer
)
{
EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS (This);
EFI_STATUS Status;
Status = PciRootBridgeIoMemRW ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)Width,
Count,
TRUE,
(PTR)(UINTN)Buffer,
TRUE,
(PTR)(UINTN)(((UINT8 *)Private->ConfigSpace) + Offset) //Fix me ConfigSpace
);
return Status;
}
EFI_STATUS
PciIoPciWrite (
IN EFI_PCI_IO_PROTOCOL *This,
IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
IN UINT32 Offset,
IN UINTN Count,
IN OUT VOID *Buffer
)
{
EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS (This);
return PciRootBridgeIoMemRW ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
Count,
TRUE,
(PTR)(UINTN)(((UINT8 *)Private->ConfigSpace) + Offset), //Fix me ConfigSpace
TRUE,
(PTR)(UINTN)Buffer
);
}
EFI_STATUS
PciIoCopyMem (
IN EFI_PCI_IO_PROTOCOL *This,
IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
IN UINT8 DestBarIndex,
IN UINT64 DestOffset,
IN UINT8 SrcBarIndex,
IN UINT64 SrcOffset,
IN UINTN Count
)
{
ASSERT (FALSE);
return EFI_UNSUPPORTED;
}
EFI_STATUS
PciIoMap (
IN EFI_PCI_IO_PROTOCOL *This,
IN EFI_PCI_IO_PROTOCOL_OPERATION Operation,
IN VOID *HostAddress,
IN OUT UINTN *NumberOfBytes,
OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
OUT VOID **Mapping
)
{
DMA_MAP_OPERATION DmaOperation;
if (Operation == EfiPciIoOperationBusMasterRead) {
DmaOperation = MapOperationBusMasterRead;
} else if (Operation == EfiPciIoOperationBusMasterWrite) {
DmaOperation = MapOperationBusMasterWrite;
} else if (Operation == EfiPciIoOperationBusMasterCommonBuffer) {
DmaOperation = MapOperationBusMasterCommonBuffer;
} else {
return EFI_INVALID_PARAMETER;
}
return DmaMap (DmaOperation, HostAddress, NumberOfBytes, DeviceAddress, Mapping);
}
EFI_STATUS
PciIoUnmap (
IN EFI_PCI_IO_PROTOCOL *This,
IN VOID *Mapping
)
{
return DmaUnmap (Mapping);
}
EFI_STATUS
PciIoAllocateBuffer (
IN EFI_PCI_IO_PROTOCOL *This,
IN EFI_ALLOCATE_TYPE Type,
IN EFI_MEMORY_TYPE MemoryType,
IN UINTN Pages,
OUT VOID **HostAddress,
IN UINT64 Attributes
)
{
if (Attributes & EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER) {
// Check this
return EFI_UNSUPPORTED;
}
return DmaAllocateBuffer (MemoryType, Pages, HostAddress);
}
EFI_STATUS
PciIoFreeBuffer (
IN EFI_PCI_IO_PROTOCOL *This,
IN UINTN Pages,
IN VOID *HostAddress
)
{
return DmaFreeBuffer (Pages, HostAddress);
}
EFI_STATUS
PciIoFlush (
IN EFI_PCI_IO_PROTOCOL *This
)
{
return EFI_SUCCESS;
}
EFI_STATUS
PciIoGetLocation (
IN EFI_PCI_IO_PROTOCOL *This,
OUT UINTN *SegmentNumber,
OUT UINTN *BusNumber,
OUT UINTN *DeviceNumber,
OUT UINTN *FunctionNumber
)
{
EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS (This);
if (SegmentNumber != NULL) {
*SegmentNumber = Private->Segment;
}
if (BusNumber != NULL) {
*BusNumber = 0xff;
}
if (DeviceNumber != NULL) {
*DeviceNumber = 0;
}
if (FunctionNumber != NULL) {
*FunctionNumber = 0;
}
return EFI_SUCCESS;
}
EFI_STATUS
PciIoAttributes (
IN EFI_PCI_IO_PROTOCOL *This,
IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation,
IN UINT64 Attributes,
OUT UINT64 *Result OPTIONAL
)
{
switch (Operation) {
case EfiPciIoAttributeOperationGet:
case EfiPciIoAttributeOperationSupported:
if (Result == NULL) {
return EFI_INVALID_PARAMETER;
}
// We are not a real PCI device so just say things we kind of do
*Result = EFI_PCI_IO_ATTRIBUTE_MEMORY | EFI_PCI_IO_ATTRIBUTE_BUS_MASTER | EFI_PCI_DEVICE_ENABLE;
break;
case EfiPciIoAttributeOperationSet:
case EfiPciIoAttributeOperationEnable:
case EfiPciIoAttributeOperationDisable:
// Since we are not a real PCI device no enable/set or disable operations exist.
return EFI_SUCCESS;
default:
ASSERT (FALSE);
return EFI_INVALID_PARAMETER;
};
return EFI_SUCCESS;
}
EFI_STATUS
PciIoGetBarAttributes (
IN EFI_PCI_IO_PROTOCOL *This,
IN UINT8 BarIndex,
OUT UINT64 *Supports, OPTIONAL
OUT VOID **Resources OPTIONAL
)
{
ASSERT (FALSE);
return EFI_UNSUPPORTED;
}
EFI_STATUS
PciIoSetBarAttributes (
IN EFI_PCI_IO_PROTOCOL *This,
IN UINT64 Attributes,
IN UINT8 BarIndex,
IN OUT UINT64 *Offset,
IN OUT UINT64 *Length
)
{
ASSERT (FALSE);
return EFI_UNSUPPORTED;
}
EFI_PCI_IO_PROTOCOL PciIoTemplate =
{
PciIoPollMem,
PciIoPollIo,
{ PciIoMemRead, PciIoMemWrite },
{ PciIoIoRead, PciIoIoWrite },
{ PciIoPciRead, PciIoPciWrite },
PciIoCopyMem,
PciIoMap,
PciIoUnmap,
PciIoAllocateBuffer,
PciIoFreeBuffer,
PciIoFlush,
PciIoGetLocation,
PciIoAttributes,
PciIoGetBarAttributes,
PciIoSetBarAttributes,
0,
0
};
EFI_STATUS
PciInstallDevice (
IN UINTN DeviceId,
IN PHYSICAL_ADDRESS MemoryStart,
IN UINT64 MemorySize,
IN UINTN ClassCode1,
IN UINTN ClassCode2,
IN UINTN ClassCode3
)
{
EFI_STATUS Status;
EFI_HANDLE Handle;
EFI_PCI_IO_PRIVATE_DATA *Private;
// Configure USB host
ConfigureUSBHost ();
// Create a private structure
Private = AllocatePool (sizeof (EFI_PCI_IO_PRIVATE_DATA));
if (Private == NULL) {
Status = EFI_OUT_OF_RESOURCES;
return Status;
}
Private->Signature = EFI_PCI_IO_PRIVATE_DATA_SIGNATURE; // Fill in signature
Private->RootBridge.Signature = PCI_ROOT_BRIDGE_SIGNATURE; // Fake Root Bridge structure needs a signature too
Private->RootBridge.MemoryStart = MemoryStart; // Get the USB capability register base
Private->Segment = 0; // Default to segment zero
// Calculate the total size of the USB controller (OHCI + EHCI).
Private->RootBridge.MemorySize = MemorySize; //CapabilityLength + (HOST_CONTROLLER_OPERATION_REG_SIZE + ((4 * PhysicalPorts) - 1));
// Create fake PCI config space: OHCI + EHCI
Private->ConfigSpace = AllocateZeroPool (sizeof (PCI_TYPE00));
if (Private->ConfigSpace == NULL) {
Status = EFI_OUT_OF_RESOURCES;
FreePool (Private);
return Status;
}
//
// Configure PCI config space: OHCI + EHCI
//
Private->ConfigSpace->Hdr.VendorId = 0x3530; //TODO: Define one
Private->ConfigSpace->Hdr.DeviceId = 0x3530; //TODO: Define one
Private->ConfigSpace->Hdr.ClassCode[0] = ClassCode1;
Private->ConfigSpace->Hdr.ClassCode[1] = ClassCode2;
Private->ConfigSpace->Hdr.ClassCode[2] = ClassCode3;
Private->ConfigSpace->Device.Bar[0] = MemoryStart;
Handle = NULL;
// Unique device path.
CopyMem (&Private->DevicePath, &PciIoDevicePathTemplate, sizeof (PciIoDevicePathTemplate));
Private->DevicePath.AcpiDevicePath.UID = 0;
Private->DevicePath.PciDevicePath.Device = DeviceId;
// Copy protocol structure
CopyMem (&Private->PciIoProtocol, &PciIoTemplate, sizeof (PciIoTemplate));
Status = gBS->InstallMultipleProtocolInterfaces (&Handle,
&gEfiPciIoProtocolGuid, &Private->PciIoProtocol,
&gEfiDevicePathProtocolGuid, &Private->DevicePath,
NULL);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "PciEmulationEntryPoint InstallMultipleProtocolInterfaces () failed.\n"));
}
return Status;
}
EFI_STATUS
PciEmulationEntryPoint (
VOID
)
{
EFI_STATUS Status;
Status = PciInstallDevice (0, FixedPcdGet32 (PcdSynopsysUsbOhciBaseAddress), SIZE_64KB, PCI_IF_OHCI, PCI_CLASS_SERIAL_USB, PCI_CLASS_SERIAL);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "PciEmulation: failed to install OHCI device.\n"));
}
Status = PciInstallDevice (1, FixedPcdGet32 (PcdSynopsysUsbEhciBaseAddress), SIZE_64KB, PCI_IF_EHCI, PCI_CLASS_SERIAL_USB, PCI_CLASS_SERIAL);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "PciEmulation: failed to install EHCI device.\n"));
}
return Status;
}

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/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
Copyright (c) 2013 - 2014, ARM Ltd. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _PCI_ROOT_BRIDGE_H_
#define _PCI_ROOT_BRIDGE_H_
#include <PiDxe.h>
#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DxeServicesTableLib.h>
#include <Library/IoLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/PciLib.h>
#include <Library/UefiLib.h>
#include <Library/DmaLib.h>
#include <Protocol/EmbeddedExternalDevice.h>
#include <Protocol/DevicePath.h>
#include <Protocol/PciIo.h>
#include <Protocol/PciRootBridgeIo.h>
#include <Protocol/PciHostBridgeResourceAllocation.h>
#include <IndustryStandard/Pci23.h>
#include "ArmJunoDxeInternal.h"
#define EFI_RESOURCE_NONEXISTENT 0xFFFFFFFFFFFFFFFFULL
#define EFI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL
#define EFI_RESOURCE_SATISFIED 0x0000000000000000ULL
typedef struct {
ACPI_HID_DEVICE_PATH AcpiDevicePath;
EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
#define ACPI_CONFIG_IO 0
#define ACPI_CONFIG_MMIO 1
#define ACPI_CONFIG_BUS 2
typedef struct {
EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR Desc[3];
EFI_ACPI_END_TAG_DESCRIPTOR EndDesc;
} ACPI_CONFIG_INFO;
#define PCI_ROOT_BRIDGE_SIGNATURE SIGNATURE_32 ('P', 'c', 'i', 'F')
typedef struct {
UINT32 Signature;
EFI_HANDLE Handle;
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL Io;
EFI_PCI_ROOT_BRIDGE_DEVICE_PATH DevicePath;
UINT8 StartBus;
UINT8 EndBus;
UINT16 Type;
UINT32 MemoryStart;
UINT32 MemorySize;
UINTN IoOffset;
UINT32 IoStart;
UINT32 IoSize;
UINT64 PciAttributes;
ACPI_CONFIG_INFO *Config;
} PCI_ROOT_BRIDGE;
#define INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(a) CR (a, PCI_ROOT_BRIDGE, Io, PCI_ROOT_BRIDGE_SIGNATURE)
typedef union {
UINT8 volatile *Buffer;
UINT8 volatile *Ui8;
UINT16 volatile *Ui16;
UINT32 volatile *Ui32;
UINT64 volatile *Ui64;
UINTN volatile Ui;
} PTR;
EFI_STATUS
EFIAPI
PciRootBridgeIoPollMem (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 Address,
IN UINT64 Mask,
IN UINT64 Value,
IN UINT64 Delay,
OUT UINT64 *Result
);
EFI_STATUS
EFIAPI
PciRootBridgeIoPollIo (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 Address,
IN UINT64 Mask,
IN UINT64 Value,
IN UINT64 Delay,
OUT UINT64 *Result
);
EFI_STATUS
EFIAPI
PciRootBridgeIoMemRead (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 Address,
IN UINTN Count,
IN OUT VOID *Buffer
);
EFI_STATUS
EFIAPI
PciRootBridgeIoMemWrite (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 Address,
IN UINTN Count,
IN OUT VOID *Buffer
);
EFI_STATUS
EFIAPI
PciRootBridgeIoIoRead (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 UserAddress,
IN UINTN Count,
IN OUT VOID *UserBuffer
);
EFI_STATUS
EFIAPI
PciRootBridgeIoIoWrite (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 UserAddress,
IN UINTN Count,
IN OUT VOID *UserBuffer
);
EFI_STATUS
EFIAPI
PciRootBridgeIoCopyMem (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 DestAddress,
IN UINT64 SrcAddress,
IN UINTN Count
);
EFI_STATUS
EFIAPI
PciRootBridgeIoPciRead (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 Address,
IN UINTN Count,
IN OUT VOID *Buffer
);
EFI_STATUS
EFIAPI
PciRootBridgeIoPciWrite (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 Address,
IN UINTN Count,
IN OUT VOID *Buffer
);
EFI_STATUS
EFIAPI
PciRootBridgeIoMap (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation,
IN VOID *HostAddress,
IN OUT UINTN *NumberOfBytes,
OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
OUT VOID **Mapping
);
EFI_STATUS
EFIAPI
PciRootBridgeIoUnmap (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
IN VOID *Mapping
);
EFI_STATUS
EFIAPI
PciRootBridgeIoAllocateBuffer (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
IN EFI_ALLOCATE_TYPE Type,
IN EFI_MEMORY_TYPE MemoryType,
IN UINTN Pages,
OUT VOID **HostAddress,
IN UINT64 Attributes
);
EFI_STATUS
EFIAPI
PciRootBridgeIoFreeBuffer (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
IN UINTN Pages,
OUT VOID *HostAddress
);
EFI_STATUS
EFIAPI
PciRootBridgeIoFlush (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This
);
EFI_STATUS
EFIAPI
PciRootBridgeIoGetAttributes (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
OUT UINT64 *Supported,
OUT UINT64 *Attributes
);
EFI_STATUS
EFIAPI
PciRootBridgeIoSetAttributes (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
IN UINT64 Attributes,
IN OUT UINT64 *ResourceBase,
IN OUT UINT64 *ResourceLength
);
EFI_STATUS
EFIAPI
PciRootBridgeIoConfiguration (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
OUT VOID **Resources
);
//
// Private Function Prototypes
//
EFI_STATUS
EFIAPI
PciRootBridgeIoMemRW (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINTN Count,
IN BOOLEAN InStrideFlag,
IN PTR In,
IN BOOLEAN OutStrideFlag,
OUT PTR Out
);
BOOLEAN
PciIoMemAddressValid (
IN EFI_PCI_IO_PROTOCOL *This,
IN UINT64 Address
);
EFI_STATUS
EmulatePciIoForEhci (
INTN MvPciIfMaxIf
);
#endif

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/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "PciEmulation.h"
BOOLEAN
PciRootBridgeMemAddressValid (
IN PCI_ROOT_BRIDGE *Private,
IN UINT64 Address
)
{
if ((Address >= Private->MemoryStart) && (Address < (Private->MemoryStart + Private->MemorySize))) {
return TRUE;
}
return FALSE;
}
EFI_STATUS
PciRootBridgeIoMemRW (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINTN Count,
IN BOOLEAN InStrideFlag,
IN PTR In,
IN BOOLEAN OutStrideFlag,
OUT PTR Out
)
{
UINTN Stride;
UINTN InStride;
UINTN OutStride;
Width = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);
Stride = (UINTN)1 << Width;
InStride = InStrideFlag ? Stride : 0;
OutStride = OutStrideFlag ? Stride : 0;
//
// Loop for each iteration and move the data
//
switch (Width) {
case EfiPciWidthUint8:
for (;Count > 0; Count--, In.Buffer += InStride, Out.Buffer += OutStride) {
*In.Ui8 = *Out.Ui8;
}
break;
case EfiPciWidthUint16:
for (;Count > 0; Count--, In.Buffer += InStride, Out.Buffer += OutStride) {
*In.Ui16 = *Out.Ui16;
}
break;
case EfiPciWidthUint32:
for (;Count > 0; Count--, In.Buffer += InStride, Out.Buffer += OutStride) {
*In.Ui32 = *Out.Ui32;
}
break;
default:
return EFI_INVALID_PARAMETER;
}
return EFI_SUCCESS;
}
EFI_STATUS
PciRootBridgeIoPciRW (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
IN BOOLEAN Write,
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 UserAddress,
IN UINTN Count,
IN OUT VOID *UserBuffer
)
{
return EFI_SUCCESS;
}
/**
Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
@param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
@param Width Signifies the width of the memory operations.
@param Address The base address of the memory operations.
@param Count The number of memory operations to perform.
@param Buffer For read operations, the destination buffer to store the results. For write
operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
@retval EFI_INVALID_PARAMETER One or more parameters are invalid.
**/
EFI_STATUS
EFIAPI
PciRootBridgeIoMemRead (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 Address,
IN UINTN Count,
IN OUT VOID *Buffer
)
{
PCI_ROOT_BRIDGE *Private;
UINTN AlignMask;
PTR In;
PTR Out;
if ( Buffer == NULL ) {
return EFI_INVALID_PARAMETER;
}
Private = INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);
if (!PciRootBridgeMemAddressValid (Private, Address)) {
return EFI_INVALID_PARAMETER;
}
AlignMask = (1 << (Width & 0x03)) - 1;
if (Address & AlignMask) {
return EFI_INVALID_PARAMETER;
}
In.Buffer = Buffer;
Out.Buffer = (VOID *)(UINTN) Address;
switch (Width) {
case EfiPciWidthUint8:
case EfiPciWidthUint16:
case EfiPciWidthUint32:
case EfiPciWidthUint64:
return PciRootBridgeIoMemRW (Width, Count, TRUE, In, TRUE, Out);
case EfiPciWidthFifoUint8:
case EfiPciWidthFifoUint16:
case EfiPciWidthFifoUint32:
case EfiPciWidthFifoUint64:
return PciRootBridgeIoMemRW (Width, Count, TRUE, In, FALSE, Out);
case EfiPciWidthFillUint8:
case EfiPciWidthFillUint16:
case EfiPciWidthFillUint32:
case EfiPciWidthFillUint64:
return PciRootBridgeIoMemRW (Width, Count, FALSE, In, TRUE, Out);
default:
break;
}
return EFI_INVALID_PARAMETER;
}
/**
Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
@param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
@param Width Signifies the width of the memory operations.
@param Address The base address of the memory operations.
@param Count The number of memory operations to perform.
@param Buffer For read operations, the destination buffer to store the results. For write
operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
@retval EFI_INVALID_PARAMETER One or more parameters are invalid.
**/
EFI_STATUS
EFIAPI
PciRootBridgeIoMemWrite (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 Address,
IN UINTN Count,
IN OUT VOID *Buffer
)
{
PCI_ROOT_BRIDGE *Private;
UINTN AlignMask;
PTR In;
PTR Out;
if ( Buffer == NULL ) {
return EFI_INVALID_PARAMETER;
}
Private = INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);
if (!PciRootBridgeMemAddressValid (Private, Address)) {
return EFI_INVALID_PARAMETER;
}
AlignMask = (1 << (Width & 0x03)) - 1;
if (Address & AlignMask) {
return EFI_INVALID_PARAMETER;
}
In.Buffer = (VOID *)(UINTN) Address;
Out.Buffer = Buffer;
switch (Width) {
case EfiPciWidthUint8:
case EfiPciWidthUint16:
case EfiPciWidthUint32:
case EfiPciWidthUint64:
return PciRootBridgeIoMemRW (Width, Count, TRUE, In, TRUE, Out);
case EfiPciWidthFifoUint8:
case EfiPciWidthFifoUint16:
case EfiPciWidthFifoUint32:
case EfiPciWidthFifoUint64:
return PciRootBridgeIoMemRW (Width, Count, FALSE, In, TRUE, Out);
case EfiPciWidthFillUint8:
case EfiPciWidthFillUint16:
case EfiPciWidthFillUint32:
case EfiPciWidthFillUint64:
return PciRootBridgeIoMemRW (Width, Count, TRUE, In, FALSE, Out);
default:
break;
}
return EFI_INVALID_PARAMETER;
}
/**
Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
@param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
@param Width Signifies the width of the memory operations.
@param Address The base address of the memory operations.
@param Count The number of memory operations to perform.
@param Buffer For read operations, the destination buffer to store the results. For write
operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
@retval EFI_INVALID_PARAMETER One or more parameters are invalid.
**/
EFI_STATUS
EFIAPI
PciRootBridgeIoPciRead (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 Address,
IN UINTN Count,
IN OUT VOID *Buffer
)
{
if (Buffer == NULL) {
return EFI_INVALID_PARAMETER;
}
return PciRootBridgeIoPciRW (This, FALSE, Width, Address, Count, Buffer);
}
/**
Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
@param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
@param Width Signifies the width of the memory operations.
@param Address The base address of the memory operations.
@param Count The number of memory operations to perform.
@param Buffer For read operations, the destination buffer to store the results. For write
operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
@retval EFI_INVALID_PARAMETER One or more parameters are invalid.
**/
EFI_STATUS
EFIAPI
PciRootBridgeIoPciWrite (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 Address,
IN UINTN Count,
IN OUT VOID *Buffer
)
{
if (Buffer == NULL) {
return EFI_INVALID_PARAMETER;
}
return PciRootBridgeIoPciRW (This, TRUE, Width, Address, Count, Buffer);
}

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/** @file
*
* Copyright (c) 2013-2014, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD
* License which accompanies this distribution. The full text of the license
* may be found at http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#include <PiDxe.h>
#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
#include <Library/IoLib.h>
#include <Library/PcdLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiRuntimeServicesTableLib.h>
#include <Library/UefiLib.h>
#include <Library/ArmGenericTimerCounterLib.h>
#include <Protocol/WatchdogTimer.h>
#include <Protocol/HardwareInterrupt.h>
#include <Drivers/GenericWatchdog.h>
// The number of 100ns periods (the unit of time passed to these functions)
// in a second
#define TIME_UNITS_PER_SECOND 10000000
// Tick frequency of the generic timer that is the basis of the generic watchdog
UINTN mTimerFrequencyHz = 0;
// In cases where the compare register was set manually, information about
// how long the watchdog was asked to wait cannot be retrieved from hardware.
// It is therefore stored here. 0 means the timer is not running.
UINT64 mNumTimerTicks = 0;
EFI_HARDWARE_INTERRUPT_PROTOCOL *mInterruptProtocol;
EFI_STATUS
WatchdogWriteOffsetRegister (
UINT32 Value
)
{
return MmioWrite32 (GENERIC_WDOG_OFFSET_REG, Value);
}
EFI_STATUS
WatchdogWriteCompareRegister (
UINT64 Value
)
{
return MmioWrite64 (GENERIC_WDOG_COMPARE_VALUE_REG, Value);
}
EFI_STATUS
WatchdogEnable (
VOID
)
{
return MmioWrite32 (GENERIC_WDOG_CONTROL_STATUS_REG, GENERIC_WDOG_ENABLED);
}
EFI_STATUS
WatchdogDisable (
VOID
)
{
return MmioWrite32 (GENERIC_WDOG_CONTROL_STATUS_REG, GENERIC_WDOG_DISABLED);
}
/**
On exiting boot services we must make sure the Watchdog Timer
is stopped.
**/
VOID
EFIAPI
WatchdogExitBootServicesEvent (
IN EFI_EVENT Event,
IN VOID *Context
)
{
WatchdogDisable ();
mNumTimerTicks = 0;
}
/*
This function is called when the watchdog's first signal (WS0) goes high.
It uses the ResetSystem Runtime Service to reset the board.
*/
VOID
EFIAPI
WatchdogInterruptHandler (
IN HARDWARE_INTERRUPT_SOURCE Source,
IN EFI_SYSTEM_CONTEXT SystemContext
)
{
STATIC CONST CHAR16 ResetString[] = L"The generic watchdog timer ran out.";
WatchdogDisable ();
mInterruptProtocol->EndOfInterrupt (mInterruptProtocol, Source);
gRT->ResetSystem (
EfiResetCold,
EFI_TIMEOUT,
StrSize (ResetString),
&ResetString
);
// If we got here then the reset didn't work
ASSERT (FALSE);
}
/**
This function registers the handler NotifyFunction so it is called every time
the watchdog timer expires. It also passes the amount of time since the last
handler call to the NotifyFunction.
If NotifyFunction is not NULL and a handler is not already registered,
then the new handler is registered and EFI_SUCCESS is returned.
If NotifyFunction is NULL, and a handler is already registered,
then that handler is unregistered.
If an attempt is made to register a handler when a handler is already registered,
then EFI_ALREADY_STARTED is returned.
If an attempt is made to unregister a handler when a handler is not registered,
then EFI_INVALID_PARAMETER is returned.
@param This The EFI_TIMER_ARCH_PROTOCOL instance.
@param NotifyFunction The function to call when a timer interrupt fires.
This function executes at TPL_HIGH_LEVEL. The DXE
Core will register a handler for the timer interrupt,
so it can know how much time has passed. This
information is used to signal timer based events.
NULL will unregister the handler.
@retval EFI_SUCCESS The watchdog timer handler was registered.
@retval EFI_ALREADY_STARTED NotifyFunction is not NULL, and a handler is already
registered.
@retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a handler was not
previously registered.
**/
EFI_STATUS
EFIAPI
WatchdogRegisterHandler (
IN CONST EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This,
IN EFI_WATCHDOG_TIMER_NOTIFY NotifyFunction
)
{
// ERROR: This function is not supported.
// The watchdog will reset the board
return EFI_UNSUPPORTED;
}
/**
This function sets the amount of time to wait before firing the watchdog
timer to TimerPeriod 100 nS units. If TimerPeriod is 0, then the watchdog
timer is disabled.
@param This The EFI_WATCHDOG_TIMER_ARCH_PROTOCOL instance.
@param TimerPeriod The amount of time in 100 nS units to wait before the watchdog
timer is fired. If TimerPeriod is zero, then the watchdog
timer is disabled.
@retval EFI_SUCCESS The watchdog timer has been programmed to fire in Time
100 nS units.
@retval EFI_DEVICE_ERROR A watchdog timer could not be programmed due to a device
error.
**/
EFI_STATUS
EFIAPI
WatchdogSetTimerPeriod (
IN CONST EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This,
IN UINT64 TimerPeriod // In 100ns units
)
{
UINTN TimerVal;
EFI_STATUS Status;
// if TimerPerdiod is 0, this is a request to stop the watchdog.
if (TimerPeriod == 0) {
mNumTimerTicks = 0;
return WatchdogDisable ();
}
// Work out how many timer ticks will equate to TimerPeriod
mNumTimerTicks = (mTimerFrequencyHz * TimerPeriod) / TIME_UNITS_PER_SECOND;
//
// If the number of required ticks is greater than the max number the
// watchdog's offset register (WOR) can hold, we need to manually compute and
// set the compare register (WCV)
//
if (mNumTimerTicks > MAX_UINT32) {
//
// We need to enable the watchdog *before* writing to the compare register,
// because enabling the watchdog causes an "explicit refresh", which
// clobbers the compare register (WCV). In order to make sure this doesn't
// trigger an interrupt, set the offset to max.
//
Status = WatchdogWriteOffsetRegister (MAX_UINT32);
if (EFI_ERROR (Status)) {
return Status;
}
WatchdogEnable ();
TimerVal = ArmGenericTimerGetTimerVal ();
Status = WatchdogWriteCompareRegister (TimerVal + mNumTimerTicks);
} else {
Status = WatchdogWriteOffsetRegister ((UINT32)mNumTimerTicks);
WatchdogEnable ();
}
return Status;
}
/**
This function retrieves the period of timer interrupts in 100 ns units,
returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPeriod
is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 is
returned, then the timer is currently disabled.
@param This The EFI_TIMER_ARCH_PROTOCOL instance.
@param TimerPeriod A pointer to the timer period to retrieve in 100
ns units. If 0 is returned, then the timer is
currently disabled.
@retval EFI_SUCCESS The timer period was returned in TimerPeriod.
@retval EFI_INVALID_PARAMETER TimerPeriod is NULL.
**/
EFI_STATUS
EFIAPI
WatchdogGetTimerPeriod (
IN CONST EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This,
OUT UINT64 *TimerPeriod
)
{
if (TimerPeriod == NULL) {
return EFI_INVALID_PARAMETER;
}
*TimerPeriod = ((TIME_UNITS_PER_SECOND / mTimerFrequencyHz) * mNumTimerTicks);
return EFI_SUCCESS;
}
/**
Interface structure for the Watchdog Architectural Protocol.
@par Protocol Description:
This protocol provides a service to set the amount of time to wait
before firing the watchdog timer, and it also provides a service to
register a handler that is invoked when the watchdog timer fires.
@par When the watchdog timer fires, control will be passed to a handler
if one has been registered. If no handler has been registered,
or the registered handler returns, then the system will be
reset by calling the Runtime Service ResetSystem().
@param RegisterHandler
Registers a handler that will be called each time the
watchdogtimer interrupt fires. TimerPeriod defines the minimum
time between timer interrupts, so TimerPeriod will also
be the minimum time between calls to the registered
handler.
NOTE: If the watchdog resets the system in hardware, then
this function will not have any chance of executing.
@param SetTimerPeriod
Sets the period of the timer interrupt in 100 nS units.
This function is optional, and may return EFI_UNSUPPORTED.
If this function is supported, then the timer period will
be rounded up to the nearest supported timer period.
@param GetTimerPeriod
Retrieves the period of the timer interrupt in 100 nS units.
**/
EFI_WATCHDOG_TIMER_ARCH_PROTOCOL gWatchdogTimer = {
(EFI_WATCHDOG_TIMER_REGISTER_HANDLER) WatchdogRegisterHandler,
(EFI_WATCHDOG_TIMER_SET_TIMER_PERIOD) WatchdogSetTimerPeriod,
(EFI_WATCHDOG_TIMER_GET_TIMER_PERIOD) WatchdogGetTimerPeriod
};
EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;
EFI_STATUS
EFIAPI
GenericWatchdogEntry (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
EFI_HANDLE Handle;
//
// Make sure the Watchdog Timer Architectural Protocol has not been installed
// in the system yet.
// This will avoid conflicts with the universal watchdog
//
ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiWatchdogTimerArchProtocolGuid);
mTimerFrequencyHz = ArmGenericTimerGetTimerFreq ();
ASSERT (mTimerFrequencyHz != 0);
// Register for an ExitBootServicesEvent
Status = gBS->CreateEvent (
EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY,
WatchdogExitBootServicesEvent, NULL, &EfiExitBootServicesEvent
);
if (!EFI_ERROR (Status)) {
// Install interrupt handler
Status = gBS->LocateProtocol (
&gHardwareInterruptProtocolGuid,
NULL,
(VOID **)&mInterruptProtocol
);
if (!EFI_ERROR (Status)) {
Status = mInterruptProtocol->RegisterInterruptSource (
mInterruptProtocol,
FixedPcdGet32 (PcdGenericWatchdogEl2IntrNum),
WatchdogInterruptHandler
);
if (!EFI_ERROR (Status)) {
// Install the Timer Architectural Protocol onto a new handle
Handle = NULL;
Status = gBS->InstallMultipleProtocolInterfaces (
&Handle,
&gEfiWatchdogTimerArchProtocolGuid, &gWatchdogTimer,
NULL
);
}
}
}
if (EFI_ERROR (Status)) {
// The watchdog failed to initialize
ASSERT (FALSE);
}
mNumTimerTicks = 0;
WatchdogDisable ();
return Status;
}

54
ArmPlatformPkg/ArmJunoPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf Normal file
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#
# Copyright (c) 2013-2014, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
[Defines]
INF_VERSION = 0x00010016
BASE_NAME = GenericWatchdogDxe
FILE_GUID = 0619f5c2-4858-4caa-a86a-73a21a18df6b
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
ENTRY_POINT = GenericWatchdogEntry
[Sources.common]
GenericWatchdogDxe.c
[Packages]
MdePkg/MdePkg.dec
EmbeddedPkg/EmbeddedPkg.dec
ArmPkg/ArmPkg.dec
ArmPlatformPkg/ArmPlatformPkg.dec
ArmPlatformPkg/ArmJunoPkg/ArmJuno.dec
[LibraryClasses]
ArmGenericTimerCounterLib
BaseLib
BaseMemoryLib
DebugLib
IoLib
PcdLib
UefiLib
UefiBootServicesTableLib
UefiDriverEntryPoint
UefiRuntimeServicesTableLib
[FixedPcd]
gArmJunoTokenSpaceGuid.PcdGenericWatchdogControlBase
gArmJunoTokenSpaceGuid.PcdGenericWatchdogRefreshBase
gArmJunoTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum
[Protocols]
gEfiWatchdogTimerArchProtocolGuid
gHardwareInterruptProtocolGuid
[Depex]
gHardwareInterruptProtocolGuid

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/** @file
*
* Copyright (c) 2013-2014, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#ifndef __ARM_JUNO_H__
#define __ARM_JUNO_H__
#include <VExpressMotherBoard.h>
/***********************************************************************************
// Platform Memory Map
************************************************************************************/
// Motherboard Peripheral and On-chip peripheral
#define ARM_VE_BOARD_PERIPH_BASE 0x1C010000
// NOR Flash 0
#define ARM_VE_SMB_NOR0_BASE 0x08000000
#define ARM_VE_SMB_NOR0_SZ SIZE_64MB
// Off-Chip peripherals (USB, Ethernet, VRAM)
#define ARM_VE_SMB_PERIPH_BASE 0x18000000
#define ARM_VE_SMB_PERIPH_SZ (SIZE_64MB + SIZE_2MB)
// On-Chip non-secure ROM
#define ARM_JUNO_NON_SECURE_ROM_BASE 0x1F000000
#define ARM_JUNO_NON_SECURE_ROM_SZ SIZE_16MB
// On-Chip Peripherals
#define ARM_JUNO_PERIPHERALS_BASE 0x20000000
#define ARM_JUNO_PERIPHERALS_SZ 0x0E000000
// On-Chip non-secure SRAM
#define ARM_JUNO_NON_SECURE_SRAM_BASE 0x2E000000
#define ARM_JUNO_NON_SECURE_SRAM_SZ SIZE_16MB
// SOC peripherals (HDLCD, UART, I2C, I2S, USB, SMC-PL354, etc)
#define ARM_JUNO_SOC_PERIPHERALS_BASE 0x7FF50000
#define ARM_JUNO_SOC_PERIPHERALS_SZ (SIZE_64KB * 9)
// 6GB of DRAM from the 64bit address space
#define ARM_JUNO_EXTRA_SYSTEM_MEMORY_BASE 0x0880000000
#define ARM_JUNO_EXTRA_SYSTEM_MEMORY_SZ (SIZE_2GB + SIZE_4GB)
#endif

29
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/** @file
*
* Copyright (c) 2013-2014, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD
* License which accompanies this distribution. The full text of the license
* may be found at http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#ifndef __GENERIC_WATCHDOG_H__
#define __GENERIC_WATCHDOG_H__
// Refresh Frame:
#define GENERIC_WDOG_REFRESH_REG ((UINT32)FixedPcdGet32 (PcdGenericWatchdogRefreshBase) + 0x000)
// Control Frame:
#define GENERIC_WDOG_CONTROL_STATUS_REG ((UINT32)FixedPcdGet32 (PcdGenericWatchdogControlBase) + 0x000)
#define GENERIC_WDOG_OFFSET_REG ((UINT32)FixedPcdGet32 (PcdGenericWatchdogControlBase) + 0x008)
#define GENERIC_WDOG_COMPARE_VALUE_REG ((UINT32)FixedPcdGet32 (PcdGenericWatchdogControlBase) + 0x010)
// Values of bit 0 of the Control/Status Register
#define GENERIC_WDOG_ENABLED 1
#define GENERIC_WDOG_DISABLED 0
#endif // __GENERIC_WATCHDOG_H__

75
ArmPlatformPkg/ArmJunoPkg/Library/ArmJunoLib/AArch64/ArmJunoHelper.S Normal file
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/** @file
*
* Copyright (c) 2013-2014, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#include <AsmMacroIoLibV8.h>
#include <Library/ArmLib.h>
.text
.align 3
GCC_ASM_EXPORT(ArmPlatformPeiBootAction)
GCC_ASM_EXPORT(ArmPlatformGetCorePosition)
GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId)
GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)
GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask)
PrimaryCoreMpid: .word 0x0
//UINTN
//ArmPlatformGetCorePosition (
// IN UINTN MpId
// );
// With this function: CorePos = (ClusterId * 2) + CoreId
ASM_PFX(ArmPlatformGetCorePosition):
and x1, x0, #ARM_CORE_MASK
and x0, x0, #ARM_CLUSTER_MASK
add x0, x1, x0, LSR #7
ret
//UINTN
//ArmPlatformGetPrimaryCoreMpId (
// VOID
// );
ASM_PFX(ArmPlatformGetPrimaryCoreMpId):
ldr x0, =PrimaryCoreMpid
ldrh w0, [x0]
ret
//UINTN
//ArmPlatformIsPrimaryCore (
// IN UINTN MpId
// );
ASM_PFX(ArmPlatformIsPrimaryCore):
LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, x1)
ldrh w1, [x1]
and x0, x0, x1
ldr x1, =PrimaryCoreMpid
ldrh w1, [x1]
cmp w0, w1
mov x0, #1
mov x1, #0
csel x0, x0, x1, eq
ret
ASM_PFX(ArmPlatformPeiBootAction):
// The trusted firmware passes the primary CPU MPID through x0 register.
// Save it in a variable.
ldr x1, =PrimaryCoreMpid
str w0, [x1]
ret

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/** @file
*
* Copyright (c) 2013-2014, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#include <AsmMacroIoLibV8.h>
#include <Library/ArmLib.h>
.text
.align 3
GCC_ASM_EXPORT(ArmPlatformPeiBootAction)
GCC_ASM_EXPORT(ArmPlatformGetCorePosition)
GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId)
GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)
GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask)
PrimaryCoreMpid: .word 0x0
//
// Return the core position from the value of its MpId register
//
// This function returns the core position from the position 0 in the processor.
// This function might be called from assembler before any stack is set.
//
// @return Return the core position
//
//UINTN
//ArmPlatformGetCorePosition (
// IN UINTN MpId
// );
// With this function: CorePos = (ClusterId * 2) + CoreId
ASM_PFX(ArmPlatformGetCorePosition):
and r1, r0, #ARM_CORE_MASK
and r0, r0, #ARM_CLUSTER_MASK
add r0, r1, r0, LSR #7
bx lr
//
// Return the MpId of the primary core
//
// This function returns the MpId of the primary core.
// This function might be called from assembler before any stack is set.
//
// @return Return the MpId of the primary core
//
//UINTN
//ArmPlatformGetPrimaryCoreMpId (
// VOID
// );
ASM_PFX(ArmPlatformGetPrimaryCoreMpId):
ldr r0, =PrimaryCoreMpid
ldr r0, [r0]
bx lr
//
// Return a non-zero value if the callee is the primary core
//
// This function returns a non-zero value if the callee is the primary core.
// The primary core is the core responsible to initialize the hardware and run UEFI.
// This function might be called from assembler before any stack is set.
//
// @return Return a non-zero value if the callee is the primary core.
//
//UINTN
//ArmPlatformIsPrimaryCore (
// IN UINTN MpId
// );
ASM_PFX(ArmPlatformIsPrimaryCore):
LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, r1)
ldr r1, [r1]
and r0, r0, r1
ldr r1, =PrimaryCoreMpid
ldr r1, [r1]
cmp r0, r1
moveq r0, #1
movne r0, #0
bx lr
//
// First platform specific function to be called in the PEI phase
//
// This function is actually the first function called by the PrePi
// or PrePeiCore modules. It allows to retrieve arguments passed to
// the UEFI firmware through the CPU registers.
//
ASM_PFX(ArmPlatformPeiBootAction):
// The trusted firmware passes the primary CPU MPID through r0 register.
// Save it in a variable.
ldr r1, =PrimaryCoreMpid
str r0, [r1]
bx lr

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/** @file
*
* Copyright (c) 2013-2014, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#include <Library/IoLib.h>
#include <Library/ArmPlatformLib.h>
#include <Library/DebugLib.h>
#include <Library/PcdLib.h>
#include <Ppi/ArmMpCoreInfo.h>
#include <ArmPlatform.h>
ARM_CORE_INFO mJunoInfoTable[] = {
{
// Cluster 0, Core 0
0x0, 0x0,
// MP Core MailBox Set/Get/Clear Addresses and Clear Value
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
(UINT64)0xFFFFFFFF
},
{
// Cluster 0, Core 1
0x0, 0x1,
// MP Core MailBox Set/Get/Clear Addresses and Clear Value
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
(UINT64)0xFFFFFFFF
},
{
// Cluster 1, Core 0
0x1, 0x0,
// MP Core MailBox Set/Get/Clear Addresses and Clear Value
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
(UINT64)0xFFFFFFFF
},
{
// Cluster 1, Core 1
0x1, 0x1,
// MP Core MailBox Set/Get/Clear Addresses and Clear Value
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
(UINT64)0xFFFFFFFF
},
{
// Cluster 1, Core 2
0x1, 0x2,
// MP Core MailBox Set/Get/Clear Addresses and Clear Value
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
(UINT64)0xFFFFFFFF
},
{
// Cluster 1, Core 3
0x1, 0x3,
// MP Core MailBox Set/Get/Clear Addresses and Clear Value
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
(UINT64)0xFFFFFFFF
}
};
/**
Return the current Boot Mode
This function returns the boot reason on the platform
@return Return the current Boot Mode of the platform
**/
EFI_BOOT_MODE
ArmPlatformGetBootMode (
VOID
)
{
return BOOT_WITH_FULL_CONFIGURATION;
}
/**
Initialize controllers that must setup in the normal world
This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim
in the PEI phase.
**/
RETURN_STATUS
ArmPlatformInitialize (
IN UINTN MpId
)
{
return RETURN_SUCCESS;
}
/**
Initialize the system (or sometimes called permanent) memory
This memory is generally represented by the DRAM.
**/
VOID
ArmPlatformInitializeSystemMemory (
VOID
)
{
}
EFI_STATUS
PrePeiCoreGetMpCoreInfo (
OUT UINTN *CoreCount,
OUT ARM_CORE_INFO **ArmCoreTable
)
{
// Only support one cluster
*CoreCount = sizeof(mJunoInfoTable) / sizeof(ARM_CORE_INFO);
*ArmCoreTable = mJunoInfoTable;
return EFI_SUCCESS;
}
// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore
EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID;
ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
{
EFI_PEI_PPI_DESCRIPTOR_PPI,
&mArmMpCoreInfoPpiGuid,
&mMpCoreInfoPpi
}
};
VOID
ArmPlatformGetPlatformPpiList (
OUT UINTN *PpiListSize,
OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
)
{
*PpiListSize = sizeof(gPlatformPpiTable);
*PpiList = gPlatformPpiTable;
}

54
ArmPlatformPkg/ArmJunoPkg/Library/ArmJunoLib/ArmJunoLib.inf Normal file
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#
# Copyright (c) 2013-2014, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = ArmJunoLib
FILE_GUID = 87c525cd-e1a2-469e-994c-c28cd0c7bd0d
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = ArmPlatformLib
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
EmbeddedPkg/EmbeddedPkg.dec
ArmPkg/ArmPkg.dec
ArmPlatformPkg/ArmPlatformPkg.dec
ArmPlatformPkg/ArmJunoPkg/ArmJuno.dec
[LibraryClasses]
IoLib
ArmLib
HobLib
MemoryAllocationLib
SerialPortLib
[Sources.common]
ArmJuno.c
ArmJunoMem.c
[Sources.AARCH64]
AArch64/ArmJunoHelper.S | GCC
[Sources.ARM]
Arm/ArmJunoHelper.S | GCC
[FeaturePcd]
gEmbeddedTokenSpaceGuid.PcdCacheEnable
[FixedPcd]
gArmTokenSpaceGuid.PcdSystemMemoryBase
gArmTokenSpaceGuid.PcdSystemMemorySize
gArmTokenSpaceGuid.PcdFvBaseAddress
gArmTokenSpaceGuid.PcdArmPrimaryCoreMask

144
ArmPlatformPkg/ArmJunoPkg/Library/ArmJunoLib/ArmJunoMem.c Normal file
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/** @file
*
* Copyright (c) 2013-2014, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#include <Library/ArmPlatformLib.h>
#include <Library/DebugLib.h>
#include <Library/HobLib.h>
#include <Library/PcdLib.h>
#include <Library/IoLib.h>
#include <Library/MemoryAllocationLib.h>
#include <ArmPlatform.h>
// The total number of descriptors, including the final "end-of-table" descriptor.
#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 12
// DDR attributes
#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
/**
Return the Virtual Memory Map of your platform
This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
@param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
Virtual Memory mapping. This array must be ended by a zero-filled
entry
**/
VOID
ArmPlatformGetVirtualMemoryMap (
IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
)
{
ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes;
UINTN Index = 0;
ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;
ASSERT (VirtualMemoryMap != NULL);
//
// Declared the additional 6GB of memory
//
ResourceAttributes =
EFI_RESOURCE_ATTRIBUTE_PRESENT |
EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
EFI_RESOURCE_ATTRIBUTE_TESTED;
BuildResourceDescriptorHob (
EFI_RESOURCE_SYSTEM_MEMORY,
ResourceAttributes,
ARM_JUNO_EXTRA_SYSTEM_MEMORY_BASE,
ARM_JUNO_EXTRA_SYSTEM_MEMORY_SZ);
VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
if (VirtualMemoryTable == NULL) {
return;
}
if (FeaturePcdGet(PcdCacheEnable) == TRUE) {
CacheAttributes = DDR_ATTRIBUTES_CACHED;
} else {
CacheAttributes = DDR_ATTRIBUTES_UNCACHED;
}
// SMB CS0 - NOR0 Flash
VirtualMemoryTable[Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE;
VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR0_BASE;
VirtualMemoryTable[Index].Length = SIZE_256KB * 255;
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
// Environment Variables region
VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE + (SIZE_256KB * 255);
VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR0_BASE + (SIZE_256KB * 255);
VirtualMemoryTable[Index].Length = SIZE_64KB * 4;
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
// SMB CS2 & CS3 - Off-chip (motherboard) peripherals
VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_PERIPH_BASE;
VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_PERIPH_BASE;
VirtualMemoryTable[Index].Length = ARM_VE_SMB_PERIPH_SZ;
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
// Juno OnChip non-secure ROM
VirtualMemoryTable[++Index].PhysicalBase = ARM_JUNO_NON_SECURE_ROM_BASE;
VirtualMemoryTable[Index].VirtualBase = ARM_JUNO_NON_SECURE_ROM_BASE;
VirtualMemoryTable[Index].Length = ARM_JUNO_NON_SECURE_ROM_SZ;
VirtualMemoryTable[Index].Attributes = CacheAttributes;
// Juno OnChip peripherals
VirtualMemoryTable[++Index].PhysicalBase = ARM_JUNO_PERIPHERALS_BASE;
VirtualMemoryTable[Index].VirtualBase = ARM_JUNO_PERIPHERALS_BASE;
VirtualMemoryTable[Index].Length = ARM_JUNO_PERIPHERALS_SZ;
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
// Juno OnChip non-secure SRAM
VirtualMemoryTable[++Index].PhysicalBase = ARM_JUNO_NON_SECURE_SRAM_BASE;
VirtualMemoryTable[Index].VirtualBase = ARM_JUNO_NON_SECURE_SRAM_BASE;
VirtualMemoryTable[Index].Length = ARM_JUNO_NON_SECURE_SRAM_SZ;
VirtualMemoryTable[Index].Attributes = CacheAttributes;
// Juno SOC peripherals
VirtualMemoryTable[++Index].PhysicalBase = ARM_JUNO_SOC_PERIPHERALS_BASE;
VirtualMemoryTable[Index].VirtualBase = ARM_JUNO_SOC_PERIPHERALS_BASE;
VirtualMemoryTable[Index].Length = ARM_JUNO_SOC_PERIPHERALS_SZ;
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
// DDR - 2GB
VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase);
VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemMemoryBase);
VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemorySize);
VirtualMemoryTable[Index].Attributes = CacheAttributes;
// DDR - 6GB
VirtualMemoryTable[++Index].PhysicalBase = ARM_JUNO_EXTRA_SYSTEM_MEMORY_BASE;
VirtualMemoryTable[Index].VirtualBase = ARM_JUNO_EXTRA_SYSTEM_MEMORY_BASE;
VirtualMemoryTable[Index].Length = ARM_JUNO_EXTRA_SYSTEM_MEMORY_SZ;
VirtualMemoryTable[Index].Attributes = CacheAttributes;
// End of Table
VirtualMemoryTable[++Index].PhysicalBase = 0;
VirtualMemoryTable[Index].VirtualBase = 0;
VirtualMemoryTable[Index].Length = 0;
VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
ASSERT((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
*VirtualMemoryMap = VirtualMemoryTable;
}

68
ArmPlatformPkg/ArmJunoPkg/Library/NorFlashJunoLib/NorFlashJuno.c Normal file
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/** @file
Copyright (c) 2011-2014, ARM Ltd. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <PiDxe.h>
#include <Library/DebugLib.h>
#include <Library/IoLib.h>
#include <Library/NorFlashPlatformLib.h>
#include <ArmPlatform.h>
NOR_FLASH_DESCRIPTION mNorFlashDevices[] = {
{
ARM_VE_SMB_NOR0_BASE,
ARM_VE_SMB_NOR0_BASE,
SIZE_256KB * 255,
SIZE_256KB,
{0xE7223039, 0x5836, 0x41E1, { 0xB5, 0x42, 0xD7, 0xEC, 0x73, 0x6C, 0x5E, 0x59} }
},
{
ARM_VE_SMB_NOR0_BASE,
ARM_VE_SMB_NOR0_BASE + SIZE_256KB * 255,
SIZE_64KB * 4,
SIZE_64KB,
{0x02118005, 0x9DA7, 0x443A, { 0x92, 0xD5, 0x78, 0x1F, 0x02, 0x2A, 0xED, 0xBB } }
},
};
EFI_STATUS
NorFlashPlatformInitialization (
VOID
)
{
// Everything seems ok so far, so now we need to disable the platform-specific
// flash write protection for Versatile Express
if ((MmioRead32 (ARM_VE_SYS_FLASH) & 0x1) == 0) {
// Writing to NOR FLASH is disabled, so enable it
MmioWrite32 (ARM_VE_SYS_FLASH, 1);
DEBUG((DEBUG_BLKIO, "NorFlashPlatformInitialization: informational - Had to enable HSYS_FLASH flag.\n" ));
}
return EFI_SUCCESS;
}
EFI_STATUS
NorFlashPlatformGetDevices (
OUT NOR_FLASH_DESCRIPTION **NorFlashDevices,
OUT UINT32 *Count
)
{
if ((NorFlashDevices == NULL) || (Count == NULL)) {
return EFI_INVALID_PARAMETER;
}
*NorFlashDevices = mNorFlashDevices;
*Count = sizeof (mNorFlashDevices) / sizeof (NOR_FLASH_DESCRIPTION);
return EFI_SUCCESS;
}

32
ArmPlatformPkg/ArmJunoPkg/Library/NorFlashJunoLib/NorFlashJunoLib.inf Normal file
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#/** @file
#
# Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = NorFlashJunoLib
FILE_GUID = 3eb6cbc4-ce95-11e2-b1bd-00241d0c1ba8
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
LIBRARY_CLASS = NorFlashPlatformLib
[Sources.common]
NorFlashJuno.c
[Packages]
MdePkg/MdePkg.dec
ArmPlatformPkg/ArmPlatformPkg.dec
[LibraryClasses]
BaseLib
DebugLib
IoLib

89
ArmPlatformPkg/ArmJunoPkg/Makefile Normal file
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#
# Copyright (c) 2013-2014, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
# Define the following variables to specify an alternative toolchain to the one located in your PATH:
# - RVCT_TOOLS_PATH: for RVCT and RVCTLINUX toolchains
# - ARMGCC_TOOLS_PATH: for ARMGCC toolchain
# - ARMLINUXGCC_TOOLS_PATH: for ARMLINUXGCC
EDK2_TOOLCHAIN ?= GCC49
GCC49_AARCH64_PREFIX ?= aarch64-none-elf-
EDK2_ARCH ?= AARCH64
EDK2_BUILD ?= DEBUG
EDK2_DSC = ArmPlatformPkg/ArmJunoPkg/ArmJuno.dsc
DEST_BIN_ROOT ?=
ifeq ($(EDK2_DSC),"")
$(error The Makefile macro 'EDK2_DSC' must be defined with an EDK2 DSC file.)
endif
ifeq ("$(OS)","Windows_NT")
export WORKSPACE?=$(PWD)
export EDK_TOOLS_PATH ?= $(WORKSPACE)\BaseTools
else
export WORKSPACE?=$(PWD)
endif
# Define the destination of the Firmware Image Package (FIP) if not defined
ifndef JUNO_FIP
ifdef DEST_BIN_ROOT
JUNO_FIP=$(DEST_BIN_ROOT)/fip.bin
else
JUNO_FIP=fip.bin
endif
endif
SHELL := /bin/bash
SILENT ?= @
ECHO ?= echo
MAKE ?= make -i -k
RM ?= rm -f
CP ?= cp
.PHONY: all clean
EDK2_CONF = Conf/BuildEnv.sh Conf/build_rule.txt Conf/target.txt Conf/tools_def.txt
all: $(EDK2_CONF)
ifeq ("$(OS)","Windows_NT")
build -a $(EDK2_ARCH) -p $(EDK2_DSC) -t $(EDK2_TOOLCHAIN) -b $(EDK2_BUILD) $(EDK2_MACROS)
else
. ./edksetup.sh; GCC49_AARCH64_PREFIX=$(GCC49_AARCH64_PREFIX) build -a $(EDK2_ARCH) -p $(EDK2_DSC) -t $(EDK2_TOOLCHAIN) -b $(EDK2_BUILD) $(EDK2_MACROS)
endif
ifeq ("$(OS)","Windows_NT")
$(SILENT)$(ECHO) "Warning: The UEFI Firmware must be added to the Firmware Image Package (FIP)."
else
$(SILENT)which fip_create ; \
if [ $$? -ne 0 ]; then \
$(ECHO) "Warning: 'fip_create' tool is not in the PATH. The UEFI binary will not be added in the Firmware Image Package (FIP)."; \
else \
fip_create --bl33 $(WORKSPACE)/Build/ArmJuno/$(EDK2_BUILD)_$(EDK2_TOOLCHAIN)/FV/BL33_AP_UEFI.fd --dump $(JUNO_FIP); \
fi
endif
$(EDK2_CONF):
ifeq ("$(OS)","Windows_NT")
copy $(EDK_TOOLS_PATH)\Conf\build_rule.template Conf\build_rule.txt
copy $(EDK_TOOLS_PATH)\Conf\FrameworkDatabase.template Conf\FrameworkDatabase.txt
copy $(EDK_TOOLS_PATH)\Conf\target.template Conf\target.txt
copy $(EDK_TOOLS_PATH)\Conf\tools_def.template Conf\tools_def.txt
else
. ./edksetup.sh; $(MAKE) -C BaseTools
endif
clean:
ifeq ("$(OS)","Windows_NT")
build -a $(EDK2_ARCH) -p $(EDK2_DSC) -t $(EDK2_TOOLCHAIN) -b $(EDK2_BUILD) $(EDK2_MACROS) cleanall
else
. ./edksetup.sh; build -a $(EDK2_ARCH) -p $(EDK2_DSC) -t $(EDK2_TOOLCHAIN) -b $(EDK2_BUILD) $(EDK2_MACROS) cleanall; \
rm -Rf $(EDK2_CONF) Conf/.cache
endif