mirror of https://github.com/acidanthera/audk.git
Add PCD setting for Timer, default is 10 times a second. You need the timer to detect a media change event. Also coded up DMA, but have not debugged it yet and it is not turned on.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10478 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
andrewfish
parent
c16f9cc33d
commit
9f6b977f66
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@ -88,6 +88,8 @@ EnableDmaChannel (
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Turn of DMA channel configured by EnableDma().
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@param Channel DMA Channel to configure
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@param SuccesMask Bits in DMA4_CSR register indicate EFI_SUCCESS
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@param ErrorMask Bits in DMA4_CSR register indicate EFI_DEVICE_ERROR
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@retval EFI_SUCCESS DMA hardware disabled
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@retval EFI_INVALID_PARAMETER Channel is not valid
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@ -97,7 +99,9 @@ EnableDmaChannel (
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EFI_STATUS
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EFIAPI
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DisableDmaChannel (
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IN UINTN Channel
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IN UINTN Channel,
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IN UINT32 SuccessMask,
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IN UINT32 ErrorMask
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);
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@ -22,6 +22,7 @@
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#define DMA4_CCR(_i) (0x48056080 + (0x60*(_i)))
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#define DMA4_CICR(_i) (0x48056088 + (0x60*(_i)))
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#define DMA4_CSR(_i) (0x4805608c + (0x60*(_i)))
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#define DMA4_CSDP(_i) (0x48056090 + (0x60*(_i)))
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#define DMA4_CEN(_i) (0x48056094 + (0x60*(_i)))
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#define DMA4_CFN(_i) (0x48056098 + (0x60*(_i)))
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@ -106,5 +107,24 @@
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#define DMA4_CCR_SEL_SRC_DEST_SYNC_SOURCE BIT24
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#define DMA4_CSR_DROP BIT1
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#define DMA4_CSR_HALF BIT2
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#define DMA4_CSR_FRAME BIT3
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#define DMA4_CSR_LAST BIT4
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#define DMA4_CSR_BLOCK BIT5
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#define DMA4_CSR_SYNC BIT6
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#define DMA4_CSR_PKT BIT7
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#define DMA4_CSR_TRANS_ERR BIT8
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#define DMA4_CSR_SECURE_ERR BIT9
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#define DMA4_CSR_SUPERVISOR_ERR BIT10
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#define DMA4_CSR_MISALIGNED_ADRS_ERR BIT11
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#define DMA4_CSR_DRAIN_END BIT12
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#define DMA4_CSR_RESET 0x1FE
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#define DMA4_CSR_ERR (DMA4_CSR_TRANS_ERR | DMA4_CSR_SECURE_ERR | DMA4_CSR_SUPERVISOR_ERR | DMA4_CSR_MISALIGNED_ADRS_ERR)
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// same mapping as CSR except for SYNC. Enable all since we are polling
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#define DMA4_CICR_ENABLE_ALL 0x1FBE
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#endif
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@ -126,10 +126,16 @@ EnableDmaChannel (
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/* - Set the destination frame index CDFI[31:0]*/
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MmioWrite32 (DMA4_CDFI (Channel), DMA4->DestinationFrameIndex);
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MmioWrite32 (DMA4_CDFI (Channel), DMA4->DestinationFrameIndex);
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// Enable all the status bits since we are polling
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MmioWrite32 (DMA4_CICR (Channel), DMA4_CICR_ENABLE_ALL);
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MmioWrite32 (DMA4_CSR (Channel), DMA4_CSR_RESET);
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/* 2) Start the DMA transfer by Setting the enable bit CCR[7]=1 */
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/*--------------------------------------------------------------*/
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//write enable bit
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MmioOr32 (DMA4_CCR(0), DMA4_CCR_ENABLE); //Launch transfer
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MmioOr32 (DMA4_CCR(Channel), DMA4_CCR_ENABLE); //Launch transfer
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return EFI_SUCCESS;
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}
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@ -138,6 +144,8 @@ EnableDmaChannel (
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Turn of DMA channel configured by EnableDma().
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@param Channel DMA Channel to configure
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@param SuccesMask Bits in DMA4_CSR register indicate EFI_SUCCESS
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@param ErrorMask Bits in DMA4_CSR register indicate EFI_DEVICE_ERROR
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@retval EFI_SUCCESS DMA hardware disabled
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@retval EFI_INVALID_PARAMETER Channel is not valid
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@ -147,16 +155,38 @@ EnableDmaChannel (
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EFI_STATUS
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EFIAPI
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DisableDmaChannel (
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IN UINTN Channel
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IN UINTN Channel,
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IN UINT32 SuccessMask,
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IN UINT32 ErrorMask
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)
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{
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EFI_STATUS Status = EFI_SUCCESS;
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UINT32 Reg;
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if (Channel > DMA4_MAX_CHANNEL) {
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return EFI_INVALID_PARAMETER;
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}
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MmioAnd32 (DMA4_CCR(0), ~(DMA4_CCR_ENABLE | DMA4_CCR_RD_ACTIVE | DMA4_CCR_WR_ACTIVE));
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return EFI_SUCCESS;
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do {
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Reg = MmioRead32 (DMA4_CSR(Channel));
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if ((Reg & ErrorMask) != 0) {
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Status = EFI_DEVICE_ERROR;
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DEBUG ((EFI_D_ERROR, "DMA Error (%d) %x\n", Channel, Reg));
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break;
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}
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} while ((Reg & SuccessMask) != SuccessMask);
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// Disable all status bits and clear them
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MmioWrite32 (DMA4_CICR (Channel), 0);
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MmioWrite32 (DMA4_CSR (Channel), DMA4_CSR_RESET);
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MmioAnd32 (DMA4_CCR(0), ~(DMA4_CCR_ENABLE | DMA4_CCR_RD_ACTIVE | DMA4_CCR_WR_ACTIVE));
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return Status;
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}
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/**
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Provides the DMA controller-specific addresses needed to access system memory.
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@ -740,7 +740,7 @@ DmaBlocks (
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)
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{
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EFI_STATUS Status;
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UINTN RetryCount = 0;
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UINTN DmaSize = 0;
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UINTN Cmd = 0;
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UINTN CmdInterruptEnable;
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UINTN CmdArgument;
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@ -749,66 +749,73 @@ DmaBlocks (
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OMAP_DMA4 Dma4;
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DMA_MAP_OPERATION DmaOperation;
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CpuDeadLoop ();
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// Map passed in buffer for DMA xfer
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DmaSize = BlockCount * This->Media->BlockSize;
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Status = DmaMap (DmaOperation, Buffer, &DmaSize, &BufferAddress, &BufferMap);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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ZeroMem (&DmaOperation, sizeof (DMA_MAP_OPERATION));
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Dma4.DataType = 2; // DMA4_CSDPi[1:0] 32-bit elements from MMCHS_DATA
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Dma4.SourceEndiansim = 0; // DMA4_CSDPi[21]
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Dma4.DestinationEndianism = 0; // DMA4_CSDPi[19]
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Dma4.SourcePacked = 0; // DMA4_CSDPi[6]
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Dma4.DestinationPacked = 0; // DMA4_CSDPi[13]
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Dma4.NumberOfElementPerFrame = This->Media->BlockSize/4; // DMA4_CENi (TRM 4K is optimum value)
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Dma4.NumberOfFramePerTransferBlock = BlockCount; // DMA4_CFNi
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Dma4.ReadPriority = 0; // DMA4_CCRi[6] Low priority read
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Dma4.WritePriority = 0; // DMA4_CCRi[23] Prefetech disabled
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//Populate the command information based on the operation type.
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if (OperationType == READ) {
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Cmd = CMD18; //Multiple block read
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CmdInterruptEnable = CMD18_INT_EN;
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DmaOperation = MapOperationBusMasterCommonBuffer;
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Dma4.ReadPortAccessType =0 ; // DMA4_CSDPi[8:7] Can not burst MMCHS_DATA reg
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Dma4.WritePortAccessType = 3; // DMA4_CSDPi[15:14] Memory burst 16x32
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Dma4.WriteMode = 1; // DMA4_CSDPi[17:16] Write posted
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Dma4.SourceStartAddress = MMCHS_DATA; // DMA4_CSSAi
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Dma4.DestinationStartAddress = (UINT32)BufferAddress; // DMA4_CDSAi
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Dma4.SourceElementIndex = 1; // DMA4_CSEi
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Dma4.SourceFrameIndex = 0x200; // DMA4_CSFi
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Dma4.DestinationElementIndex = 1; // DMA4_CDEi
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Dma4.DestinationFrameIndex = 0; // DMA4_CDFi
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Dma4.ReadPortAccessMode = 0; // DMA4_CCRi[13:12] Always read MMCHS_DATA
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Dma4.WritePortAccessMode = 1; // DMA4_CCRi[15:14] Post increment memory address
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Dma4.ReadRequestNumber = 0x1e; // DMA4_CCRi[4:0] Syncro with MMCA_DMA_RX (61)
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Dma4.WriteRequestNumber = 1; // DMA4_CCRi[20:19] Syncro upper 0x3e == 62 (one based)
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} else if (OperationType == WRITE) {
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Cmd = CMD25; //Multiple block write
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CmdInterruptEnable = CMD25_INT_EN;
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DmaOperation = MapOperationBusMasterRead;
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Dma4.ReadPortAccessType = 3; // DMA4_CSDPi[8:7] Memory burst 16x32
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Dma4.WritePortAccessType = 0; // DMA4_CSDPi[15:14] Can not burst MMCHS_DATA reg
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Dma4.WriteMode = 1; // DMA4_CSDPi[17:16] Write posted ???
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Dma4.SourceStartAddress = (UINT32)BufferAddress; // DMA4_CSSAi
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Dma4.DestinationStartAddress = MMCHS_DATA; // DMA4_CDSAi
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Dma4.SourceElementIndex = 1; // DMA4_CSEi
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Dma4.SourceFrameIndex = 0x200; // DMA4_CSFi
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Dma4.DestinationElementIndex = 1; // DMA4_CDEi
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Dma4.DestinationFrameIndex = 0; // DMA4_CDFi
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Dma4.ReadPortAccessMode = 1; // DMA4_CCRi[13:12] Post increment memory address
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Dma4.WritePortAccessMode = 0; // DMA4_CCRi[15:14] Always write MMCHS_DATA
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Dma4.ReadRequestNumber = 0x1d; // DMA4_CCRi[4:0] Syncro with MMCA_DMA_TX (60)
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Dma4.WriteRequestNumber = 1; // DMA4_CCRi[20:19] Syncro upper 0x3d == 61 (one based)
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} else {
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return EFI_INVALID_PARAMETER;
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}
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// Map passed in buffer for DMA xfer
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RetryCount = BlockCount * This->Media->BlockSize;
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Status = DmaMap (DmaOperation, Buffer, &RetryCount, &BufferAddress, &BufferMap);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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#if 0
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MmioWrite32 (DMA4_CSDP(0), DMA4_CSDP_DATA_TYPE32 | DMA4_CSDP_SRC_BURST_EN64 | DMA4_CSDP_WRITE_MODE_POSTED);
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MmioWrite32 (DMA4_CEN(0), 0x4096); // Channel Element number
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MmioWrite32 (DMA4_CFN(0), 0x1); // Channel Frame number
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if () {
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MmioWrite32 (DMA4_CCR(0), X | DMA4_CCR_FS_PACKET | DMA4_CCR_RD_ACTIVE | DMA4_CCR_WR_ACTIVE | DMA4_CCR_DST_AMODE_POST_INC | DMA4_CCR_SEL_SRC_DEST_SYNC_SOURCE);
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MmioWrite32 (DMA4_CSSA(0), MMCHS_DATA); // Src is SD Card
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MmioWrite32 (DMA4_CDSA(0), (UINT32)BufferAddress); // Dst memory
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} else {
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MmioWrite32 (DMA4_CCR(0), X | DMA4_CCR_FS_PACKET | DMA4_CCR_RD_ACTIVE | DMA4_CCR_WR_ACTIVE | DMA4_CCR_SRC_AMODE_POST_INC);
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MmioWrite32 (DMA4_CSSA(0), (UINT32)BufferAddress); // Src memory
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MmioWrite32 (DMA4_CDSA(0), MMCHS_DATA); // Dst SD Card
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}
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MmioWrite32 (DMA4_CSE(0), 1);
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MmioWrite32 (DMA4_CSF(0), This->Media->BlockSize);
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MmioWrite32 (DMA4_CDE(0), 1);
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#endif
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Dma4.DataType = 0; // DMA4_CSDPi[1:0]
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Dma4.ReadPortAccessType =0; // DMA4_CSDPi[8:7]
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Dma4.WritePortAccessType =0; // DMA4_CSDPi[15:14]
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Dma4.SourceEndiansim = 0; // DMA4_CSDPi[21]
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Dma4.DestinationEndianism = 0; // DMA4_CSDPi[19]
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Dma4.WriteMode = 0; // DMA4_CSDPi[17:16]
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Dma4.SourcePacked = 0; // DMA4_CSDPi[6]
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Dma4.DestinationPacked = 0; // DMA4_CSDPi[13]
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Dma4.NumberOfElementPerFrame = 0; // DMA4_CENi
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Dma4.NumberOfFramePerTransferBlock = 0; // DMA4_CFNi
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Dma4.SourceStartAddress = 0; // DMA4_CSSAi
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Dma4.DestinationStartAddress = 0; // DMA4_CDSAi
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Dma4.SourceElementIndex = 0; // DMA4_CSEi
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Dma4.SourceFrameIndex = 0; // DMA4_CSFi
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Dma4.DestinationElementIndex = 0; // DMA4_CDEi
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Dma4.DestinationFrameIndex = 0; // DMA4_CDFi
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Dma4.ReadPortAccessMode = 0; // DMA4_CCRi[13:12]
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Dma4.WritePortAccessMode = 0; // DMA4_CCRi[15:14]
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Dma4.ReadPriority = 0; // DMA4_CCRi[6]
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Dma4.WritePriority = 0; // DMA4_CCRi[23]
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Dma4.ReadRequestNumber = 0; // DMA4_CCRi[4:0]
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Dma4.WriteRequestNumber = 0; // DMA4_CCRi[20:19]
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EnableDmaChannel (2, &Dma4);
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@ -827,7 +834,7 @@ DmaBlocks (
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return Status;
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}
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DisableDmaChannel (2);
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DisableDmaChannel (2, DMA4_CSR_BLOCK, DMA4_CSR_ERR);
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Status = DmaUnmap (BufferMap);
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return Status;
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@ -1029,6 +1036,7 @@ DetectCard (
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return Status;
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}
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#define MAX_MMCHS_TRANSFER_SIZE 0x4000
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EFI_STATUS
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SdReadWrite (
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@ -1042,7 +1050,7 @@ SdReadWrite (
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EFI_STATUS Status = EFI_SUCCESS;
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UINTN RetryCount = 0;
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UINTN BlockCount;
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UINTN BytesToBeTranferedThisPass;
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UINTN BytesToBeTranferedThisPass = 0;
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UINTN BytesRemainingToBeTransfered;
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EFI_TPL OldTpl;
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BOOLEAN Update;
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@ -1323,7 +1331,7 @@ MMCHSInitialize (
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Status = gBS->CreateEvent (EVT_TIMER | EVT_NOTIFY_SIGNAL, TPL_CALLBACK, TimerCallback, NULL, &gTimerEvent);
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ASSERT_EFI_ERROR (Status);
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Status = gBS->SetTimer (gTimerEvent, TimerPeriodic, 1000000ULL); // make me a PCD
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Status = gBS->SetTimer (gTimerEvent, TimerPeriodic, FixedPcdGet32 (PcdMmchsTimerFreq100NanoSeconds));
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ASSERT_EFI_ERROR (Status);
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//Publish BlockIO.
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@ -47,6 +47,7 @@
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[Pcd]
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gOmap35xxTokenSpaceGuid.PcdOmap35xxMMCHS1Base
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gOmap35xxTokenSpaceGuid.PcdMmchsTimerFreq100NanoSeconds
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[depex]
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gEmbeddedExternalDeviceProtocolGuid
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@ -54,4 +54,5 @@
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gOmap35xxTokenSpaceGuid.PcdOmap35xxFreeTimer|4|UINT32|0x00000206
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gOmap35xxTokenSpaceGuid.PcdOmap35xxDebugAgentTimer|5|UINT32|0x00000207
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gOmap35xxTokenSpaceGuid.PcdDebugAgentTimerFreqNanoSeconds|77|UINT32|0x00000208
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gOmap35xxTokenSpaceGuid.PcdMmchsTimerFreq100NanoSeconds|1000000|UINT32|0x00000209
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