mirror of https://github.com/acidanthera/audk.git
ShellPkg: add the last PCIe extended capability decodings
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jaben Carsey <jaben.carsey@intel.com> Reviewed-by: Erik Bjorge <erik.c.bjorge@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15097 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Jaben Carsey
jcarsey
parent
e1c9edd6b6
commit
9f7f0697b7
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@ -5042,6 +5042,220 @@ PrintInterpretedExtendedCompatibilityAer (
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return (EFI_SUCCESS);
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}
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/**
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Function to interpret and print out the multicast structure
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@param[in] HeaderAddress The Address of this capability header.
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@param[in] HeadersBaseAddress The address of all the extended capability headers.
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@param[in] PciExpressCapPtr The address of the PCIe capabilities structure.
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**/
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EFI_STATUS
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EFIAPI
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PrintInterpretedExtendedCompatibilityMulticast (
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IN CONST PCI_EXP_EXT_HDR *HeaderAddress,
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IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress,
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IN CONST PCIE_CAP_STURCTURE *PciExpressCapPtr
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)
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{
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CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST *Header;
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Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST*)HeaderAddress;
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ShellPrintHiiEx(
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-1, -1, NULL,
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STRING_TOKEN (STR_PCI_EXT_CAP_MULTICAST),
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gShellDebug1HiiHandle,
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Header->MultiCastCapability,
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Header->MulticastControl,
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Header->McBaseAddress,
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Header->McReceiveAddress,
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Header->McBlockAll,
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Header->McBlockUntranslated,
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Header->McOverlayBar
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);
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DumpHex (
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4,
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EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),
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sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST),
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(VOID *) (HeaderAddress)
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);
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return (EFI_SUCCESS);
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}
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/**
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Function to interpret and print out the virtual channel and multi virtual channel structure
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@param[in] HeaderAddress The Address of this capability header.
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@param[in] HeadersBaseAddress The address of all the extended capability headers.
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**/
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EFI_STATUS
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EFIAPI
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PrintInterpretedExtendedCompatibilityVirtualChannel (
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IN CONST PCI_EXP_EXT_HDR *HeaderAddress,
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IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress
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)
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{
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CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY *Header;
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CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC *CapabilityItem;
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UINT32 ItemCount;
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Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY*)HeaderAddress;
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ShellPrintHiiEx(
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-1, -1, NULL,
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STRING_TOKEN (STR_PCI_EXT_CAP_VC_BASE),
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gShellDebug1HiiHandle,
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Header->ExtendedVcCount,
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Header->PortVcCapability1,
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Header->PortVcCapability2,
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Header->VcArbTableOffset,
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Header->PortVcControl,
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Header->PortVcStatus
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);
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for (ItemCount = 0 ; ItemCount < Header->ExtendedVcCount ; ItemCount++) {
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CapabilityItem = &Header->Capability[ItemCount];
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ShellPrintHiiEx(
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-1, -1, NULL,
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STRING_TOKEN (STR_PCI_EXT_CAP_VC_ITEM),
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gShellDebug1HiiHandle,
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ItemCount+1,
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CapabilityItem->VcResourceCapability,
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CapabilityItem->PortArbTableOffset,
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CapabilityItem->VcResourceControl,
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CapabilityItem->VcResourceStatus
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);
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}
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DumpHex (
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4,
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EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),
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sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC) + (Header->ExtendedVcCount - 1) * sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY),
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(VOID *) (HeaderAddress)
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);
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return (EFI_SUCCESS);
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}
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/**
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Function to interpret and print out the resizeable bar structure
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@param[in] HeaderAddress The Address of this capability header.
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@param[in] HeadersBaseAddress The address of all the extended capability headers.
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**/
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EFI_STATUS
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EFIAPI
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PrintInterpretedExtendedCompatibilityResizeableBar (
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IN CONST PCI_EXP_EXT_HDR *HeaderAddress,
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IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress
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)
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{
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CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR *Header;
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UINT32 ItemCount;
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Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR*)HeaderAddress;
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for (ItemCount = 0 ; ItemCount < (UINT32)GET_NUMBER_RESIZABLE_BARS(Header) ; ItemCount++) {
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ShellPrintHiiEx(
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-1, -1, NULL,
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STRING_TOKEN (STR_PCI_EXT_CAP_RESIZE_BAR),
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gShellDebug1HiiHandle,
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ItemCount+1,
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Header->Capability[ItemCount].ResizableBarCapability,
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Header->Capability[ItemCount].ResizableBarControl
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);
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}
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DumpHex (
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4,
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EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),
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(UINT32)GET_NUMBER_RESIZABLE_BARS(Header) * sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY),
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(VOID *) (HeaderAddress)
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);
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return (EFI_SUCCESS);
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}
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/**
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Function to interpret and print out the TPH structure
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@param[in] HeaderAddress The Address of this capability header.
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@param[in] HeadersBaseAddress The address of all the extended capability headers.
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**/
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EFI_STATUS
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EFIAPI
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PrintInterpretedExtendedCompatibilityTph (
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IN CONST PCI_EXP_EXT_HDR *HeaderAddress,
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IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress
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)
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{
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CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH *Header;
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Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH*)HeaderAddress;
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ShellPrintHiiEx(
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-1, -1, NULL,
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STRING_TOKEN (STR_PCI_EXT_CAP_TPH),
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gShellDebug1HiiHandle,
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Header->TphRequesterCapability,
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Header->TphRequesterControl
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);
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DumpHex (
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8,
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EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)Header->TphStTable - (UINT8*)HeadersBaseAddress),
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GET_TPH_TABLE_SIZE(Header),
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(VOID *)Header->TphStTable
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);
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DumpHex (
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4,
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EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),
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sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH) + GET_TPH_TABLE_SIZE(Header) - sizeof(UINT16),
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(VOID *) (HeaderAddress)
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);
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return (EFI_SUCCESS);
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}
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/**
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Function to interpret and print out the secondary PCIe capability structure
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@param[in] HeaderAddress The Address of this capability header.
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@param[in] HeadersBaseAddress The address of all the extended capability headers.
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@param[in] PciExpressCapPtr The address of the PCIe capabilities structure.
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**/
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EFI_STATUS
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EFIAPI
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PrintInterpretedExtendedCompatibilitySecondary (
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IN CONST PCI_EXP_EXT_HDR *HeaderAddress,
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IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress,
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IN CONST PCIE_CAP_STURCTURE *PciExpressCapPtr
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)
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{
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CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE *Header;
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Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE*)HeaderAddress;
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ShellPrintHiiEx(
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-1, -1, NULL,
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STRING_TOKEN (STR_PCI_EXT_CAP_SECONDARY),
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gShellDebug1HiiHandle,
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Header->LinkControl3,
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Header->LaneErrorStatus
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);
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DumpHex (
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8,
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EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)Header->EqualizationControl - (UINT8*)HeadersBaseAddress),
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PCIE_CAP_MAX_LINK_WIDTH(PciExpressCapPtr->LinkCap),
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(VOID *)Header->EqualizationControl
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);
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DumpHex (
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4,
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EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),
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sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH) - sizeof(Header->EqualizationControl) + PCIE_CAP_MAX_LINK_WIDTH(PciExpressCapPtr->LinkCap),
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(VOID *) (HeaderAddress)
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);
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return (EFI_SUCCESS);
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}
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/**
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Display Pcie extended capability details
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@ -5094,26 +5308,25 @@ PrintPciExtendedCapabilityDetails(
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case PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_ID:
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return PrintInterpretedExtendedCompatibilityECEA(HeaderAddress, HeadersBaseAddress);
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break;
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/**
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case PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_ID:
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case PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_ID:
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ASSERT(FALSE);
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return PrintInterpretedExtendedCompatibilityVirtualChannel(HeaderAddress, HeadersBaseAddress);
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break;
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case PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_ID:
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// use PCIE_CAP_DEVICEPORT_TYPE(PciExpressCapPtr->PcieCapReg) == 0100b, 0101b, or 0110b
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ASSERT(FALSE);
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//
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// should only be present if PCIE_CAP_DEVICEPORT_TYPE(PciExpressCapPtr->PcieCapReg) == 0100b, 0101b, or 0110b
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//
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return PrintInterpretedExtendedCompatibilityMulticast(HeaderAddress, HeadersBaseAddress, PciExpressCapPtr);
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break;
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case PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID:
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ASSERT(FALSE);
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return PrintInterpretedExtendedCompatibilityResizeableBar(HeaderAddress, HeadersBaseAddress);
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break;
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case PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_ID:
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ASSERT(FALSE);
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return PrintInterpretedExtendedCompatibilityTph(HeaderAddress, HeadersBaseAddress);
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break;
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case PCI_EXPRESS_EXTENDED_CAPABILITY_SECONDARY_PCIE_ID:
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// use PciExpressCapPtr link capabilities register
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ASSERT(FALSE);
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return PrintInterpretedExtendedCompatibilitySecondary(HeaderAddress, HeadersBaseAddress, PciExpressCapPtr);
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break;
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//**/
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default:
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ShellPrintEx (-1, -1,
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L"Unknown PCIe extended capability ID (%04xh). No interpretation available.\r\n",
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