mirror of https://github.com/acidanthera/audk.git
BaseCacheMaintenanceLib has now been completed on all architectures.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@183 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
parent
98fc92fcbd
commit
9f84a60982
|
@ -34,6 +34,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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<LibraryClassDefinitions>
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<LibraryClass Usage="ALWAYS_PRODUCED">CacheMaintenanceLib</LibraryClass>
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<LibraryClass Usage="ALWAYS_CONSUMED">BaseLib</LibraryClass>
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<LibraryClass Usage="ALWAYS_CONSUMED">DebugLib</LibraryClass>
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</LibraryClassDefinitions>
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<SourceFiles>
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<Arch ArchType="IA32">
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@ -12,6 +12,14 @@
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**/
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/**
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Invalidates the entire instruction cache in cache coherency domain of the
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calling CPU.
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Invalidates the entire instruction cache in cache coherency domain of the
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calling CPU.
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**/
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VOID
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EFIAPI
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InvalidateInstructionCache (
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@ -20,6 +28,31 @@ InvalidateInstructionCache (
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{
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}
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/**
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Invalidates a range of instruction cache lines in the cache coherency domain
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of the calling CPU.
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Invalidates the instruction cache lines specified by Address and Length. If
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Address is not aligned on a cache line boundary, then entire instruction
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cache line containing Address is invalidated. If Address + Length is not
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aligned on a cache line boundary, then the entire instruction cache line
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containing Address + Length -1 is invalidated. This function may choose to
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invalidate the entire instruction cache if that is more efficient than
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invalidating the specified range. If Length is 0, the no instruction cache
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lines are invalidated. Address is returned.
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If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
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@param Address The base address of the instruction cache lines to
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invalidate. If the CPU is in a physical addressing mode, then
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Address is a physical address. If the CPU is in a virtual
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addressing mode, then Address is a virtual address.
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@param Length The number of bytes to invalidate from the instruction cache.
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@return Address
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**/
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VOID *
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EFIAPI
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InvalidateInstructionCacheRange (
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@ -27,9 +60,20 @@ InvalidateInstructionCacheRange (
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IN UINTN Length
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)
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{
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ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
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return Address;
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}
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/**
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Writes Back and Invalidates the entire data cache in cache coherency domain
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of the calling CPU.
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Writes Back and Invalidates the entire data cache in cache coherency domain
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of the calling CPU. This function guarantees that all dirty cache lines are
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written back to system memory, and also invalidates all the data cache lines
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in the cache coherency domain of the calling CPU.
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**/
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VOID
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EFIAPI
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WriteBackInvalidateDataCache (
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@ -38,6 +82,32 @@ WriteBackInvalidateDataCache (
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{
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}
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/**
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Writes Back and Invalidates a range of data cache lines in the cache
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coherency domain of the calling CPU.
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Writes Back and Invalidate the data cache lines specified by Address and
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Length. If Address is not aligned on a cache line boundary, then entire data
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cache line containing Address is written back and invalidated. If Address +
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Length is not aligned on a cache line boundary, then the entire data cache
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line containing Address + Length -1 is written back and invalidated. This
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function may choose to write back and invalidate the entire data cache if
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that is more efficient than writing back and invalidating the specified
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range. If Length is 0, the no data cache lines are written back and
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invalidated. Address is returned.
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If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
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@param Address The base address of the data cache lines to write back and
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invalidate. If the CPU is in a physical addressing mode, then
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Address is a physical address. If the CPU is in a virtual
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addressing mode, then Address is a virtual address.
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@param Length The number of bytes to write back and invalidate from the
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data cache.
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@return Address
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**/
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VOID *
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EFIAPI
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WriteBackInvalidateDataCacheRange (
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@ -45,9 +115,20 @@ WriteBackInvalidateDataCacheRange (
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IN UINTN Length
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)
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{
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ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
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return Address;
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}
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/**
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Writes Back the entire data cache in cache coherency domain of the calling
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CPU.
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Writes Back the entire data cache in cache coherency domain of the calling
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CPU. This function guarantees that all dirty cache lines are written back to
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system memory. This function may also invalidate all the data cache lines in
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the cache coherency domain of the calling CPU.
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**/
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VOID
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EFIAPI
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WriteBackDataCache (
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@ -56,6 +137,31 @@ WriteBackDataCache (
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{
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}
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/**
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Writes Back a range of data cache lines in the cache coherency domain of the
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calling CPU.
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Writes Back the data cache lines specified by Address and Length. If Address
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is not aligned on a cache line boundary, then entire data cache line
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containing Address is written back. If Address + Length is not aligned on a
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cache line boundary, then the entire data cache line containing Address +
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Length -1 is written back. This function may choose to write back the entire
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data cache if that is more efficient than writing back the specified range.
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If Length is 0, the no data cache lines are written back. This function may
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also invalidate all the data cache lines in the specified range of the cache
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coherency domain of the calling CPU. Address is returned.
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If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
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@param Address The base address of the data cache lines to write back. If
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the CPU is in a physical addressing mode, then Address is a
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physical address. If the CPU is in a virtual addressing
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mode, then Address is a virtual address.
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@param Length The number of bytes to write back from the data cache.
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@return Address
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**/
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VOID *
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EFIAPI
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WriteBackDataCacheRange (
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@ -63,9 +169,21 @@ WriteBackDataCacheRange (
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IN UINTN Length
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)
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{
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ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
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return Address;
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}
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/**
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Invalidates the entire data cache in cache coherency domain of the calling
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CPU.
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Invalidates the entire data cache in cache coherency domain of the calling
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CPU. This function must be used with care because dirty cache lines are not
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written back to system memory. It is typically used for cache diagnostics. If
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the CPU does not support invalidation of the entire data cache, then a write
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back and invalidate operation should be performed on the entire data cache.
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**/
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VOID
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EFIAPI
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InvalidateDataCache (
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@ -74,6 +192,33 @@ InvalidateDataCache (
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{
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}
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/**
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Invalidates a range of data cache lines in the cache coherency domain of the
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calling CPU.
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Invalidates the data cache lines specified by Address and Length. If Address
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is not aligned on a cache line boundary, then entire data cache line
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containing Address is invalidated. If Address + Length is not aligned on a
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cache line boundary, then the entire data cache line containing Address +
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Length -1 is invalidated. This function must never invalidate any cache lines
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outside the specified range. If Length is 0, the no data cache lines are
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invalidated. Address is returned. This function must be used with care
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because dirty cache lines are not written back to system memory. It is
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typically used for cache diagnostics. If the CPU does not support
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invalidation of a data cache range, then a write back and invalidate
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operation should be performed on the data cache range.
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If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
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@param Address The base address of the data cache lines to invalidate. If
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the CPU is in a physical addressing mode, then Address is a
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physical address. If the CPU is in a virtual addressing mode,
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then Address is a virtual address.
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@param Length The number of bytes to invalidate from the data cache.
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@return Address
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**/
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VOID *
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EFIAPI
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InvalidateDataCacheRange (
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@ -81,5 +226,6 @@ InvalidateDataCacheRange (
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IN UINTN Length
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)
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{
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ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
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return Address;
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}
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@ -27,6 +27,14 @@ CallPalProcStatic (
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IN UINT64 Arg4
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);
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/**
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Invalidates the entire instruction cache in cache coherency domain of the
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calling CPU.
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Invalidates the entire instruction cache in cache coherency domain of the
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calling CPU.
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**/
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VOID
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EFIAPI
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InvalidateInstructionCache (
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@ -36,6 +44,56 @@ InvalidateInstructionCache (
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CallPalProcStatic (1, 1, 1, 0);
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}
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/**
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Invalidates a range of instruction cache lines in the cache coherency domain
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of the calling CPU.
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Invalidates the instruction cache lines specified by Address and Length. If
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Address is not aligned on a cache line boundary, then entire instruction
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cache line containing Address is invalidated. If Address + Length is not
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aligned on a cache line boundary, then the entire instruction cache line
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containing Address + Length -1 is invalidated. This function may choose to
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invalidate the entire instruction cache if that is more efficient than
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invalidating the specified range. If Length is 0, the no instruction cache
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lines are invalidated. Address is returned.
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If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
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@param Address The base address of the instruction cache lines to
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invalidate. If the CPU is in a physical addressing mode, then
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Address is a physical address. If the CPU is in a virtual
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addressing mode, then Address is a virtual address.
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@param Length The number of bytes to invalidate from the instruction cache.
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@return Address
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**/
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VOID*
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EFIAPI
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InvalidateInstructionCacheRange (
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IN VOID *Address,
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IN UINTN Length
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)
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{
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ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
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if (Length > 0) {
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InvalidateInstructionCache ();
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}
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return Address;
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}
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/**
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Writes Back and Invalidates the entire data cache in cache coherency domain
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of the calling CPU.
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Writes Back and Invalidates the entire data cache in cache coherency domain
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of the calling CPU. This function guarantees that all dirty cache lines are
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written back to system memory, and also invalidates all the data cache lines
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in the cache coherency domain of the calling CPU.
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**/
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VOID
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EFIAPI
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WriteBackInvalidateDataCache (
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@ -45,6 +103,32 @@ WriteBackInvalidateDataCache (
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CallPalProcStatic (1, 2, 1, 0);
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}
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/**
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Writes Back and Invalidates a range of data cache lines in the cache
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coherency domain of the calling CPU.
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Writes Back and Invalidate the data cache lines specified by Address and
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Length. If Address is not aligned on a cache line boundary, then entire data
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cache line containing Address is written back and invalidated. If Address +
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Length is not aligned on a cache line boundary, then the entire data cache
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line containing Address + Length -1 is written back and invalidated. This
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function may choose to write back and invalidate the entire data cache if
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that is more efficient than writing back and invalidating the specified
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range. If Length is 0, the no data cache lines are written back and
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invalidated. Address is returned.
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If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
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@param Address The base address of the data cache lines to write back and
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invalidate. If the CPU is in a physical addressing mode, then
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Address is a physical address. If the CPU is in a virtual
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addressing mode, then Address is a virtual address.
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@param Length The number of bytes to write back and invalidate from the
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data cache.
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@return Address
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**/
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VOID *
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EFIAPI
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WriteBackInvalidateDataCacheRange (
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@ -52,10 +136,24 @@ WriteBackInvalidateDataCacheRange (
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IN UINTN Length
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)
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{
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ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
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if (Length > 0) {
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WriteBackInvalidateDataCache ();
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}
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return Address;
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}
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/**
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Writes Back the entire data cache in cache coherency domain of the calling
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CPU.
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Writes Back the entire data cache in cache coherency domain of the calling
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CPU. This function guarantees that all dirty cache lines are written back to
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system memory. This function may also invalidate all the data cache lines in
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the cache coherency domain of the calling CPU.
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**/
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VOID
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EFIAPI
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WriteBackDataCache (
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@ -65,6 +163,31 @@ WriteBackDataCache (
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CallPalProcStatic (1, 2, 0, 0);
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}
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/**
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Writes Back a range of data cache lines in the cache coherency domain of the
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calling CPU.
|
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|
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Writes Back the data cache lines specified by Address and Length. If Address
|
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is not aligned on a cache line boundary, then entire data cache line
|
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containing Address is written back. If Address + Length is not aligned on a
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cache line boundary, then the entire data cache line containing Address +
|
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Length -1 is written back. This function may choose to write back the entire
|
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data cache if that is more efficient than writing back the specified range.
|
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If Length is 0, the no data cache lines are written back. This function may
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also invalidate all the data cache lines in the specified range of the cache
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coherency domain of the calling CPU. Address is returned.
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If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
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@param Address The base address of the data cache lines to write back. If
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the CPU is in a physical addressing mode, then Address is a
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physical address. If the CPU is in a virtual addressing
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mode, then Address is a virtual address.
|
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@param Length The number of bytes to write back from the data cache.
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@return Address
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**/
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VOID *
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EFIAPI
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WriteBackDataCacheRange (
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|
@ -72,18 +195,61 @@ WriteBackDataCacheRange (
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IN UINTN Length
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)
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{
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ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
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if (Length > 0) {
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WriteBackDataCache ();
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}
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return Address;
|
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}
|
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|
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/**
|
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Invalidates the entire data cache in cache coherency domain of the calling
|
||||
CPU.
|
||||
|
||||
Invalidates the entire data cache in cache coherency domain of the calling
|
||||
CPU. This function must be used with care because dirty cache lines are not
|
||||
written back to system memory. It is typically used for cache diagnostics. If
|
||||
the CPU does not support invalidation of the entire data cache, then a write
|
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back and invalidate operation should be performed on the entire data cache.
|
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|
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**/
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VOID
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EFIAPI
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InvalidateDataCache (
|
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VOID
|
||||
)
|
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{
|
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WriteBackInvalidateDataCache ();
|
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}
|
||||
|
||||
/**
|
||||
Invalidates a range of data cache lines in the cache coherency domain of the
|
||||
calling CPU.
|
||||
|
||||
Invalidates the data cache lines specified by Address and Length. If Address
|
||||
is not aligned on a cache line boundary, then entire data cache line
|
||||
containing Address is invalidated. If Address + Length is not aligned on a
|
||||
cache line boundary, then the entire data cache line containing Address +
|
||||
Length -1 is invalidated. This function must never invalidate any cache lines
|
||||
outside the specified range. If Length is 0, the no data cache lines are
|
||||
invalidated. Address is returned. This function must be used with care
|
||||
because dirty cache lines are not written back to system memory. It is
|
||||
typically used for cache diagnostics. If the CPU does not support
|
||||
invalidation of a data cache range, then a write back and invalidate
|
||||
operation should be performed on the data cache range.
|
||||
|
||||
If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
|
||||
|
||||
@param Address The base address of the data cache lines to invalidate. If
|
||||
the CPU is in a physical addressing mode, then Address is a
|
||||
physical address. If the CPU is in a virtual addressing mode,
|
||||
then Address is a virtual address.
|
||||
@param Length The number of bytes to invalidate from the data cache.
|
||||
|
||||
@return Address
|
||||
|
||||
**/
|
||||
VOID *
|
||||
EFIAPI
|
||||
InvalidateDataCacheRange (
|
||||
|
@ -91,5 +257,5 @@ InvalidateDataCacheRange (
|
|||
IN UINTN Length
|
||||
)
|
||||
{
|
||||
return Address;
|
||||
return WriteBackInvalidateDataCacheRange (Address, Length);
|
||||
}
|
||||
|
|
|
@ -14,15 +14,47 @@
|
|||
|
||||
**/
|
||||
|
||||
/**
|
||||
Invalidates the entire instruction cache in cache coherency domain of the
|
||||
calling CPU.
|
||||
|
||||
Invalidates the entire instruction cache in cache coherency domain of the
|
||||
calling CPU.
|
||||
|
||||
**/
|
||||
VOID
|
||||
EFIAPI
|
||||
InvalidateInstructionCache (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
Invalidates a range of instruction cache lines in the cache coherency domain
|
||||
of the calling CPU.
|
||||
|
||||
Invalidates the instruction cache lines specified by Address and Length. If
|
||||
Address is not aligned on a cache line boundary, then entire instruction
|
||||
cache line containing Address is invalidated. If Address + Length is not
|
||||
aligned on a cache line boundary, then the entire instruction cache line
|
||||
containing Address + Length -1 is invalidated. This function may choose to
|
||||
invalidate the entire instruction cache if that is more efficient than
|
||||
invalidating the specified range. If Length is 0, the no instruction cache
|
||||
lines are invalidated. Address is returned.
|
||||
|
||||
If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
|
||||
|
||||
@param Address The base address of the instruction cache lines to
|
||||
invalidate. If the CPU is in a physical addressing mode, then
|
||||
Address is a physical address. If the CPU is in a virtual
|
||||
addressing mode, then Address is a virtual address.
|
||||
|
||||
@param Length The number of bytes to invalidate from the instruction cache.
|
||||
|
||||
@return Address
|
||||
|
||||
**/
|
||||
VOID *
|
||||
EFIAPI
|
||||
InvalidateInstructionCacheRange (
|
||||
|
@ -30,9 +62,20 @@ InvalidateInstructionCacheRange (
|
|||
IN UINTN Length
|
||||
)
|
||||
{
|
||||
ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
|
||||
return Address;
|
||||
}
|
||||
|
||||
/**
|
||||
Writes Back and Invalidates the entire data cache in cache coherency domain
|
||||
of the calling CPU.
|
||||
|
||||
Writes Back and Invalidates the entire data cache in cache coherency domain
|
||||
of the calling CPU. This function guarantees that all dirty cache lines are
|
||||
written back to system memory, and also invalidates all the data cache lines
|
||||
in the cache coherency domain of the calling CPU.
|
||||
|
||||
**/
|
||||
VOID
|
||||
EFIAPI
|
||||
WriteBackInvalidateDataCache (
|
||||
|
@ -42,6 +85,32 @@ WriteBackInvalidateDataCache (
|
|||
AsmWbinvd ();
|
||||
}
|
||||
|
||||
/**
|
||||
Writes Back and Invalidates a range of data cache lines in the cache
|
||||
coherency domain of the calling CPU.
|
||||
|
||||
Writes Back and Invalidate the data cache lines specified by Address and
|
||||
Length. If Address is not aligned on a cache line boundary, then entire data
|
||||
cache line containing Address is written back and invalidated. If Address +
|
||||
Length is not aligned on a cache line boundary, then the entire data cache
|
||||
line containing Address + Length -1 is written back and invalidated. This
|
||||
function may choose to write back and invalidate the entire data cache if
|
||||
that is more efficient than writing back and invalidating the specified
|
||||
range. If Length is 0, the no data cache lines are written back and
|
||||
invalidated. Address is returned.
|
||||
|
||||
If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
|
||||
|
||||
@param Address The base address of the data cache lines to write back and
|
||||
invalidate. If the CPU is in a physical addressing mode, then
|
||||
Address is a physical address. If the CPU is in a virtual
|
||||
addressing mode, then Address is a virtual address.
|
||||
@param Length The number of bytes to write back and invalidate from the
|
||||
data cache.
|
||||
|
||||
@return Address
|
||||
|
||||
**/
|
||||
VOID *
|
||||
EFIAPI
|
||||
WriteBackInvalidateDataCacheRange (
|
||||
|
@ -49,21 +118,66 @@ WriteBackInvalidateDataCacheRange (
|
|||
IN UINTN Length
|
||||
)
|
||||
{
|
||||
if (Length != 0) {
|
||||
AsmWbinvd ();
|
||||
UINT8 (*Uint8Ptr)[32];
|
||||
|
||||
ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
|
||||
|
||||
Uint8Ptr = Address;
|
||||
while (Length > sizeof (*Uint8Ptr)) {
|
||||
AsmFlushCacheLine (Uint8Ptr++);
|
||||
Length -= sizeof (*Uint8Ptr);
|
||||
}
|
||||
if (Length > 0) {
|
||||
AsmFlushCacheLine (Uint8Ptr);
|
||||
AsmFlushCacheLine (&(*Uint8Ptr)[Length - 1]);
|
||||
}
|
||||
return Address;
|
||||
}
|
||||
|
||||
/**
|
||||
Writes Back the entire data cache in cache coherency domain of the calling
|
||||
CPU.
|
||||
|
||||
Writes Back the entire data cache in cache coherency domain of the calling
|
||||
CPU. This function guarantees that all dirty cache lines are written back to
|
||||
system memory. This function may also invalidate all the data cache lines in
|
||||
the cache coherency domain of the calling CPU.
|
||||
|
||||
**/
|
||||
VOID
|
||||
EFIAPI
|
||||
WriteBackDataCache (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
AsmWbinvd ();
|
||||
WriteBackInvalidateDataCache ();
|
||||
}
|
||||
|
||||
/**
|
||||
Writes Back a range of data cache lines in the cache coherency domain of the
|
||||
calling CPU.
|
||||
|
||||
Writes Back the data cache lines specified by Address and Length. If Address
|
||||
is not aligned on a cache line boundary, then entire data cache line
|
||||
containing Address is written back. If Address + Length is not aligned on a
|
||||
cache line boundary, then the entire data cache line containing Address +
|
||||
Length -1 is written back. This function may choose to write back the entire
|
||||
data cache if that is more efficient than writing back the specified range.
|
||||
If Length is 0, the no data cache lines are written back. This function may
|
||||
also invalidate all the data cache lines in the specified range of the cache
|
||||
coherency domain of the calling CPU. Address is returned.
|
||||
|
||||
If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
|
||||
|
||||
@param Address The base address of the data cache lines to write back. If
|
||||
the CPU is in a physical addressing mode, then Address is a
|
||||
physical address. If the CPU is in a virtual addressing
|
||||
mode, then Address is a virtual address.
|
||||
@param Length The number of bytes to write back from the data cache.
|
||||
|
||||
@return Address
|
||||
|
||||
**/
|
||||
VOID *
|
||||
EFIAPI
|
||||
WriteBackDataCacheRange (
|
||||
|
@ -71,10 +185,20 @@ WriteBackDataCacheRange (
|
|||
IN UINTN Length
|
||||
)
|
||||
{
|
||||
AsmWbinvd ();
|
||||
return Address;
|
||||
return WriteBackInvalidateDataCacheRange (Address, Length);
|
||||
}
|
||||
|
||||
/**
|
||||
Invalidates the entire data cache in cache coherency domain of the calling
|
||||
CPU.
|
||||
|
||||
Invalidates the entire data cache in cache coherency domain of the calling
|
||||
CPU. This function must be used with care because dirty cache lines are not
|
||||
written back to system memory. It is typically used for cache diagnostics. If
|
||||
the CPU does not support invalidation of the entire data cache, then a write
|
||||
back and invalidate operation should be performed on the entire data cache.
|
||||
|
||||
**/
|
||||
VOID
|
||||
EFIAPI
|
||||
InvalidateDataCache (
|
||||
|
@ -84,6 +208,33 @@ InvalidateDataCache (
|
|||
AsmInvd ();
|
||||
}
|
||||
|
||||
/**
|
||||
Invalidates a range of data cache lines in the cache coherency domain of the
|
||||
calling CPU.
|
||||
|
||||
Invalidates the data cache lines specified by Address and Length. If Address
|
||||
is not aligned on a cache line boundary, then entire data cache line
|
||||
containing Address is invalidated. If Address + Length is not aligned on a
|
||||
cache line boundary, then the entire data cache line containing Address +
|
||||
Length -1 is invalidated. This function must never invalidate any cache lines
|
||||
outside the specified range. If Length is 0, the no data cache lines are
|
||||
invalidated. Address is returned. This function must be used with care
|
||||
because dirty cache lines are not written back to system memory. It is
|
||||
typically used for cache diagnostics. If the CPU does not support
|
||||
invalidation of a data cache range, then a write back and invalidate
|
||||
operation should be performed on the data cache range.
|
||||
|
||||
If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
|
||||
|
||||
@param Address The base address of the data cache lines to invalidate. If
|
||||
the CPU is in a physical addressing mode, then Address is a
|
||||
physical address. If the CPU is in a virtual addressing mode,
|
||||
then Address is a virtual address.
|
||||
@param Length The number of bytes to invalidate from the data cache.
|
||||
|
||||
@return Address
|
||||
|
||||
**/
|
||||
VOID *
|
||||
EFIAPI
|
||||
InvalidateDataCacheRange (
|
||||
|
@ -91,5 +242,5 @@ InvalidateDataCacheRange (
|
|||
IN UINTN Length
|
||||
)
|
||||
{
|
||||
return Address;
|
||||
return WriteBackInvalidateDataCacheRange (Address, Length);
|
||||
}
|
||||
|
|
Loading…
Reference in New Issue