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UefiCpuPkg/Include: Update MSEG structure comments 

Add comments to describe fields of MSEG_HEADER and
add define values for the MonitorFeatures field.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
This commit is contained in:
Michael Kinney 2016-12-06 23:22:24 -08:00 committed by Feng Tian
parent 5f16ecdb02
commit a03bb3d2a9
1 changed files with 22 additions and 3 deletions
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25
UefiCpuPkg/Include/Register/ArchitecturalMsr.h
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@ -520,7 +520,19 @@ typedef union {
field of #MSR_IA32_SMM_MONITOR_CTL_REGISTER.
**/
typedef struct {
///
/// Different processors may use different MSEG revision identifiers. These
/// identifiers enable software to avoid using an MSEG header formatted for
/// one processor on a processor that uses a different format. Software can
/// discover the MSEG revision identifier that a processor uses by reading
/// the VMX capability MSR IA32_VMX_MISC.
//
UINT32 MsegHeaderRevision;
///
/// Bits 31:1 of this field are reserved and must be zero. Bit 0 of the field
/// is the IA-32e mode SMM feature bit. It indicates whether the logical
/// processor will be in IA-32e mode after the STM is activated.
///
UINT32 MonitorFeatures;
UINT32 GdtrLimit;
UINT32 GdtrBaseOffset;
@ -528,12 +540,19 @@ typedef struct {
UINT32 EipOffset;
UINT32 EspOffset;
UINT32 Cr3Offset;
//
// Pad header so total size is 2KB
//
///
/// Pad header so total size is 2KB
///
UINT8 Reserved[SIZE_2KB - 8 * sizeof (UINT32)];
} MSEG_HEADER;
///
/// @{ Define values for the MonitorFeatures field of #MSEG_HEADER
///
#define STM_FEATURES_IA32E 0x1
///
/// @}
///
/**
Base address of the logical processor's SMRAM image (RO, SMM only). If