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MdePkg: Rename the LoongArch CSR 0x20 register

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Added a new name for CSR 0x20 because LoongArch SPEC has adjustd the CSR
0x20 register name.

Ref: LoongArch Reference Manual Vol 1, Seciton 7.1.
https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#control-and-status-registers

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Chao Li <lichao@loongson.cn>
This commit is contained in:
Chao Li 2024-08-29 15:24:53 +08:00 committed by mergify[bot]
parent d5c7bba504
commit a066ca16d3
2 changed files with 13 additions and 12 deletions
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1
MdePkg/Include/Register/LoongArch64/Csr.h
View File

@ -113,6 +113,7 @@
// Config CSR registers // Config CSR registers
// //
#define LOONGARCH_CSR_CPUNUM 0x20 // CPU core number #define LOONGARCH_CSR_CPUNUM 0x20 // CPU core number
#define LOONGARCH_CSR_CPUID 0x20 // CPU core ID
#define LOONGARCH_CSR_PRCFG1 0x21 // Config1 #define LOONGARCH_CSR_PRCFG1 0x21 // Config1
#define LOONGARCH_CSR_PRCFG2 0x22 // Config2 #define LOONGARCH_CSR_PRCFG2 0x22 // Config2
#define LOONGARCH_CSR_PRCFG3 0x23 // Config3 #define LOONGARCH_CSR_PRCFG3 0x23 // Config3

24
MdePkg/Library/BaseLib/LoongArch64/AsmCsr.S
View File

@ -50,12 +50,12 @@ TlbCsrRd:
jirl $zero, $t0, 0 jirl $zero, $t0, 0
CfgCsrRd: CfgCsrRd:
li.w $t0, LOONGARCH_CSR_CPUNUM li.w $t0, LOONGARCH_CSR_CPUID
bltu $a0, $t0, ReadSelNumErr bltu $a0, $t0, ReadSelNumErr
li.w $t0, LOONGARCH_CSR_PRCFG3 li.w $t0, LOONGARCH_CSR_PRCFG3
bltu $t0, $a0, KcsCsrRd bltu $t0, $a0, KcsCsrRd
la.pcrel $t0, CfgCsrRead la.pcrel $t0, CfgCsrRead
addi.w $t1, $a0, -LOONGARCH_CSR_CPUNUM addi.w $t1, $a0, -LOONGARCH_CSR_CPUID
alsl.d $t0, $t1, $t0, 3 alsl.d $t0, $t1, $t0, 3
jirl $zero, $t0, 0 jirl $zero, $t0, 0
@ -117,8 +117,8 @@ TlbCsrRead:
.endr .endr
CfgCsrRead: CfgCsrRead:
CsrSel = LOONGARCH_CSR_CPUNUM CsrSel = LOONGARCH_CSR_CPUID
.rept LOONGARCH_CSR_PRCFG3 - LOONGARCH_CSR_CPUNUM + 1 .rept LOONGARCH_CSR_PRCFG3 - LOONGARCH_CSR_CPUID + 1
AsmCsrRd CsrSel AsmCsrRd CsrSel
CsrSel = CsrSel + 1 CsrSel = CsrSel + 1
.endr .endr
@ -174,12 +174,12 @@ TlbCsrWr:
jirl $zero, $t0, 0 jirl $zero, $t0, 0
CfgCsrWr: CfgCsrWr:
li.w $t0, LOONGARCH_CSR_CPUNUM li.w $t0, LOONGARCH_CSR_CPUID
bltu $a0, $t0, WriteSelNumErr bltu $a0, $t0, WriteSelNumErr
li.w $t0, LOONGARCH_CSR_PRCFG3 li.w $t0, LOONGARCH_CSR_PRCFG3
bltu $t0, $a0, KcsCsrWr bltu $t0, $a0, KcsCsrWr
la.pcrel $t0, CfgCsrWrite la.pcrel $t0, CfgCsrWrite
addi.w $t1, $a0, -LOONGARCH_CSR_CPUNUM addi.w $t1, $a0, -LOONGARCH_CSR_CPUID
alsl.d $t0, $t1, $t0, 3 alsl.d $t0, $t1, $t0, 3
move $a0, $a1 move $a0, $a1
jirl $zero, $t0, 0 jirl $zero, $t0, 0
@ -246,8 +246,8 @@ TlbCsrWrite:
.endr .endr
CfgCsrWrite: CfgCsrWrite:
CsrSel = LOONGARCH_CSR_CPUNUM CsrSel = LOONGARCH_CSR_CPUID
.rept LOONGARCH_CSR_PRCFG3 - LOONGARCH_CSR_CPUNUM + 1 .rept LOONGARCH_CSR_PRCFG3 - LOONGARCH_CSR_CPUID + 1
AsmCsrWr CsrSel AsmCsrWr CsrSel
CsrSel = CsrSel + 1 CsrSel = CsrSel + 1
.endr .endr
@ -306,12 +306,12 @@ TlbCsrXchg:
jirl $zero, $t0, 0 jirl $zero, $t0, 0
CfgCsrXchg: CfgCsrXchg:
li.w $t0, LOONGARCH_CSR_CPUNUM li.w $t0, LOONGARCH_CSR_CPUID
bltu $a0, $t0, XchgSelNumErr bltu $a0, $t0, XchgSelNumErr
li.w $t0, LOONGARCH_CSR_PRCFG3 li.w $t0, LOONGARCH_CSR_PRCFG3
bltu $t0, $a0, KcsCsrXchg bltu $t0, $a0, KcsCsrXchg
la.pcrel $t0, CfgCsrXchange la.pcrel $t0, CfgCsrXchange
addi.w $t1, $a0, -LOONGARCH_CSR_CPUNUM addi.w $t1, $a0, -LOONGARCH_CSR_CPUID
alsl.d $t0, $t1, $t0, 3 alsl.d $t0, $t1, $t0, 3
move $a0, $a1 move $a0, $a1
move $a1, $a2 move $a1, $a2
@ -383,8 +383,8 @@ TlbCsrXchange:
.endr .endr
CfgCsrXchange: CfgCsrXchange:
CsrSel = LOONGARCH_CSR_CPUNUM CsrSel = LOONGARCH_CSR_CPUID
.rept LOONGARCH_CSR_PRCFG3 - LOONGARCH_CSR_CPUNUM + 1 .rept LOONGARCH_CSR_PRCFG3 - LOONGARCH_CSR_CPUID + 1
AsmCsrXChange CsrSel AsmCsrXChange CsrSel
CsrSel = CsrSel + 1 CsrSel = CsrSel + 1
.endr .endr