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MdeModulePkg/DxeIpl: Create 5-level page table for long mode
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2008 Correct the logic about whether 5-level paging is supported. Signed-off-by: Jason Lou <yun.lou@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Dandan Bi <dandan.bi@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn>
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@ -15,7 +15,7 @@
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2) IA-32 Intel(R) Architecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel
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2) IA-32 Intel(R) Architecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel
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3) IA-32 Intel(R) Architecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel
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3) IA-32 Intel(R) Architecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel
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Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
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Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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SPDX-License-Identifier: BSD-2-Clause-Patent
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@ -748,8 +748,8 @@ CreateIdentityMappingPageTables (
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CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,
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CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,
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CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO,
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CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO,
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NULL,
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NULL,
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&EcxFlags.Uint32,
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NULL,
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NULL,
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&EcxFlags.Uint32,
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NULL
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NULL
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);
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);
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if (EcxFlags.Bits.FiveLevelPage != 0) {
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if (EcxFlags.Bits.FiveLevelPage != 0) {
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