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ArmPkg/PL390Gic: Populate the GIC Distributor Target Register with the GIC CPU ID retrieved from the GIC 

The GIC CPU Id (the GIC CPU interface the CPU is connected to) can be retrieved by reading the first
registers of the GIC CPU Target Registers.
The first GIC Distributor Target registers correspond to the SGIs.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14479 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Olivier Martin 2013-07-17 06:25:15 +00:00 committed by oliviermartin
parent 0b342ffb76
commit a1cca63885
1 changed files with 20 additions and 5 deletions
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25
ArmPkg/Drivers/PL390Gic/PL390GicDxe.c
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@ -371,11 +371,26 @@ InterruptDxeInitialize (
);
}
// Configure interrupts for Primary Cpu
CpuTarget = (1 << PcdGet32 (PcdGicPrimaryCoreId));
CpuTarget |= (CpuTarget << 24) | (CpuTarget << 16) | (CpuTarget << 8);
for (Index = 0; Index < (mGicNumInterrupts / 4); Index++) {
MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDIPTR + (Index*4), CpuTarget);
//
// Targets the interrupts to the Primary Cpu
//
// Only Primary CPU will run this code. We can identify our GIC CPU ID by reading
// the GIC Distributor Target register. The 8 first GICD_ITARGETSRn are banked to each
// connected CPU. These 8 registers hold the CPU targets fields for interrupts 0-31.
// More Info in the GIC Specification about "Interrupt Processor Targets Registers"
//
// Read the first Interrupt Processor Targets Register (that corresponds to the 4
// first SGIs)
CpuTarget = MmioRead32 (PcdGet32 (PcdGicDistributorBase) + ARM_GIC_ICDIPTR);
// The CPU target is a bit field mapping each CPU to a GIC CPU Interface. This value
// cannot be 0.
ASSERT (CpuTarget != 0);
// The 8 first Interrupt Processor Targets Registers are read-only
for (Index = 8; Index < (mGicNumInterrupts / 4); Index++) {
MmioWrite32 (PcdGet32 (PcdGicDistributorBase) + ARM_GIC_ICDIPTR + (Index * 4), CpuTarget);
}
// Set binary point reg to 0x7 (no preemption)