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MdeModulePkg/SdMmcPciHcDxe: Refactor command error detection
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1140 Error detection function will now check if the command failure has been caused by one of the errors that can appear randomly on link(CRC error + end bit error). If such an error has been a cause of failure, function will return EFI_CRC_ERROR instead of EFI_DEVICE_ERROR to indicate to the higher level that command has a chance of succeeding if resent. Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Marcin Wojtas <mw@semihalf.com> Cc: Zhichao Gao <zhichao.gao@intel.com> Cc: Liming Gao <liming.gao@intel.com> Signed-off-by: Mateusz Albecki <mateusz.albecki@intel.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
This commit is contained in:
Albecki, Mateusz
mergify[bot]
parent
4e2ac8062c
commit
a22f4c34df
@ -2137,6 +2137,137 @@ SdMmcExecTrb (
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return Status;
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return Status;
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}
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}
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/**
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Performs SW reset based on passed error status mask.
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@param[in] Private Pointer to driver private data.
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@param[in] Slot Index of the slot to reset.
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@param[in] ErrIntStatus Error interrupt status mask.
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@retval EFI_SUCCESS Software reset performed successfully.
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@retval Other Software reset failed.
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**/
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EFI_STATUS
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SdMmcSoftwareReset (
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IN SD_MMC_HC_PRIVATE_DATA *Private,
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IN UINT8 Slot,
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IN UINT16 ErrIntStatus
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)
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{
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UINT8 SwReset;
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EFI_STATUS Status;
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SwReset = 0;
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if ((ErrIntStatus & 0x0F) != 0) {
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SwReset |= BIT1;
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}
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if ((ErrIntStatus & 0x70) != 0) {
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SwReset |= BIT2;
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}
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Status = SdMmcHcRwMmio (
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Private->PciIo,
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Slot,
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SD_MMC_HC_SW_RST,
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FALSE,
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sizeof (SwReset),
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&SwReset
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);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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Status = SdMmcHcWaitMmioSet (
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Private->PciIo,
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Slot,
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SD_MMC_HC_SW_RST,
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sizeof (SwReset),
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0xFF,
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0,
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SD_MMC_HC_GENERIC_TIMEOUT
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);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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return EFI_SUCCESS;
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}
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/**
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Checks the error status in error status register
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and issues appropriate software reset as described in
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SD specification section 3.10.
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@param[in] Private Pointer to driver private data.
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@param[in] Trb Pointer to currently executing TRB.
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@param[in] IntStatus Normal interrupt status mask.
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@retval EFI_CRC_ERROR CRC error happened during CMD execution.
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@retval EFI_SUCCESS No error reported.
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@retval Others Some other error happened.
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**/
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EFI_STATUS
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SdMmcCheckAndRecoverErrors (
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IN SD_MMC_HC_PRIVATE_DATA *Private,
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IN UINT8 Slot,
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IN UINT16 IntStatus
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)
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{
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UINT16 ErrIntStatus;
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EFI_STATUS Status;
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EFI_STATUS ErrorStatus;
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if ((IntStatus & BIT15) == 0) {
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return EFI_SUCCESS;
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}
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Status = SdMmcHcRwMmio (
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Private->PciIo,
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Slot,
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SD_MMC_HC_ERR_INT_STS,
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TRUE,
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sizeof (ErrIntStatus),
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&ErrIntStatus
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);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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//
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// If the data timeout error is reported
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// but data transfer is signaled as completed we
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// have to ignore data timeout. We also assume that no
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// other error is present on the link since data transfer
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// completed successfully. Error interrupt status
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// register is going to be reset when the next command
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// is started.
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//
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if (((ErrIntStatus & BIT4) != 0) && ((IntStatus & BIT1) != 0)) {
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return EFI_SUCCESS;
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}
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//
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// We treat both CMD and DAT CRC errors and
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// end bits errors as EFI_CRC_ERROR. This will
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// let higher layer know that the error possibly
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// happened due to random bus condition and the
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// command can be retried.
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//
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if ((ErrIntStatus & (BIT1 | BIT2 | BIT5 | BIT6)) != 0) {
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ErrorStatus = EFI_CRC_ERROR;
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} else {
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ErrorStatus = EFI_DEVICE_ERROR;
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}
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Status = SdMmcSoftwareReset (Private, Slot, ErrIntStatus);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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return ErrorStatus;
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}
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/**
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/**
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Check the TRB execution result.
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Check the TRB execution result.
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@ -2160,10 +2291,8 @@ SdMmcCheckTrbResult (
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UINT32 Response[4];
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UINT32 Response[4];
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UINT64 SdmaAddr;
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UINT64 SdmaAddr;
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UINT8 Index;
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UINT8 Index;
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UINT8 SwReset;
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UINT32 PioLength;
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UINT32 PioLength;
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SwReset = 0;
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Packet = Trb->Packet;
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Packet = Trb->Packet;
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//
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//
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// Check Trb execution result by reading Normal Interrupt Status register.
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// Check Trb execution result by reading Normal Interrupt Status register.
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@ -2179,87 +2308,23 @@ SdMmcCheckTrbResult (
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if (EFI_ERROR (Status)) {
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if (EFI_ERROR (Status)) {
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goto Done;
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goto Done;
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}
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}
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//
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// Check if there are any errors reported by host controller
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// and if neccessary recover the controller before next command is executed.
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//
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Status = SdMmcCheckAndRecoverErrors (Private, Trb->Slot, IntStatus);
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if (EFI_ERROR (Status)) {
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goto Done;
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}
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//
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//
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// Check Transfer Complete bit is set or not.
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// Check Transfer Complete bit is set or not.
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//
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//
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if ((IntStatus & BIT1) == BIT1) {
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if ((IntStatus & BIT1) == BIT1) {
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if ((IntStatus & BIT15) == BIT15) {
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//
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// Read Error Interrupt Status register to check if the error is
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// Data Timeout Error.
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// If yes, treat it as success as Transfer Complete has higher
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// priority than Data Timeout Error.
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//
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Status = SdMmcHcRwMmio (
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Private->PciIo,
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Trb->Slot,
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SD_MMC_HC_ERR_INT_STS,
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TRUE,
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sizeof (IntStatus),
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&IntStatus
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);
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if (!EFI_ERROR (Status)) {
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if ((IntStatus & BIT4) == BIT4) {
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Status = EFI_SUCCESS;
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} else {
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Status = EFI_DEVICE_ERROR;
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}
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}
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}
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goto Done;
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goto Done;
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}
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}
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//
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// Check if there is a error happened during cmd execution.
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// If yes, then do error recovery procedure to follow SD Host Controller
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// Simplified Spec 3.0 section 3.10.1.
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//
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if ((IntStatus & BIT15) == BIT15) {
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Status = SdMmcHcRwMmio (
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Private->PciIo,
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Trb->Slot,
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SD_MMC_HC_ERR_INT_STS,
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TRUE,
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sizeof (IntStatus),
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&IntStatus
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);
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if (EFI_ERROR (Status)) {
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goto Done;
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}
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if ((IntStatus & 0x0F) != 0) {
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SwReset |= BIT1;
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}
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if ((IntStatus & 0x70) != 0) {
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SwReset |= BIT2;
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}
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Status = SdMmcHcRwMmio (
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Private->PciIo,
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Trb->Slot,
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SD_MMC_HC_SW_RST,
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FALSE,
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sizeof (SwReset),
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&SwReset
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);
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if (EFI_ERROR (Status)) {
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goto Done;
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}
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Status = SdMmcHcWaitMmioSet (
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Private->PciIo,
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Trb->Slot,
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SD_MMC_HC_SW_RST,
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sizeof (SwReset),
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0xFF,
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0,
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SD_MMC_HC_GENERIC_TIMEOUT
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);
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if (EFI_ERROR (Status)) {
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goto Done;
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}
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Status = EFI_DEVICE_ERROR;
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goto Done;
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}
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//
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//
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// Check if DMA interrupt is signalled for the SDMA transfer.
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// Check if DMA interrupt is signalled for the SDMA transfer.
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//
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//
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