tyler.durden/audk
1
0
Fork 0
mirror of https://github.com/acidanthera/audk.git synced 2025-04-08 17:05:09 +02:00
Code Issues Packages Projects Releases Wiki Activity

code cleanup:

Browse Source 
1. remove unused macro/remove unnecessary included header file
2. for those values defined by PCI spec, use the naming of definition in IndustryStandard/Pci.h
3. use BITX macro in Base.h rather than define one by self.

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@8992 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
eric_tian 2009-07-24 05:34:55 +00:00
parent 15a865075c
commit a261044cf5
8 changed files with 41 additions and 59 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
MdeModulePkg/Bus/Pci/EhciDxe/Ehci.c
View File

@ -46,12 +46,6 @@ gEhciDriverBinding = {
NULL
};
///
/// USB host controller Programming Interface.
///
#define PCI_CLASSC_PI_UHCI 0x00
#define PCI_CLASSC_PI_EHCI 0x20
/**
Retrieves the capability of root hub ports.
@ -1347,7 +1341,7 @@ EhcDriverBindingSupported (
Status = PciIo->Pci.Read (
PciIo,
EfiPciIoWidthUint8,
EHC_PCI_CLASSC,
PCI_CLASSCODE_OFFSET,
sizeof (USB_CLASSC) / sizeof (UINT8),
&UsbClassCReg
);
@ -1361,7 +1355,7 @@ EhcDriverBindingSupported (
// Test whether the controller belongs to Ehci type
//
if ((UsbClassCReg.BaseCode != PCI_CLASS_SERIAL) || (UsbClassCReg.SubClassCode != PCI_CLASS_SERIAL_USB)
|| ((UsbClassCReg.PI != EHC_PCI_CLASSC_PI) && (UsbClassCReg.PI !=PCI_CLASSC_PI_UHCI))) {
|| ((UsbClassCReg.PI != PCI_IF_EHCI) && (UsbClassCReg.PI !=PCI_IF_UHCI))) {
Status = EFI_UNSUPPORTED;
}
@ -1579,7 +1573,7 @@ EhcDriverBindingStart (
Status = PciIo->Pci.Read (
PciIo,
EfiPciIoWidthUint8,
EHC_PCI_CLASSC,
PCI_CLASSCODE_OFFSET,
sizeof (USB_CLASSC) / sizeof (UINT8),
&UsbClassCReg
);
@ -1589,7 +1583,7 @@ EhcDriverBindingStart (
goto CLOSE_PCIIO;
}
if ((UsbClassCReg.PI == PCI_CLASSC_PI_UHCI) &&
if ((UsbClassCReg.PI == PCI_IF_UHCI) &&
(UsbClassCReg.BaseCode == PCI_CLASS_SERIAL) &&
(UsbClassCReg.SubClassCode == PCI_CLASS_SERIAL_USB)) {
Status = PciIo->GetLocation (
@ -1628,7 +1622,7 @@ EhcDriverBindingStart (
Status = Instance->Pci.Read (
Instance,
EfiPciIoWidthUint8,
EHC_PCI_CLASSC,
PCI_CLASSCODE_OFFSET,
sizeof (USB_CLASSC) / sizeof (UINT8),
&UsbClassCReg
);
@ -1638,7 +1632,7 @@ EhcDriverBindingStart (
goto CLOSE_PCIIO;
}
if ((UsbClassCReg.PI == PCI_CLASSC_PI_EHCI) &&
if ((UsbClassCReg.PI == PCI_IF_EHCI) &&
(UsbClassCReg.BaseCode == PCI_CLASS_SERIAL) &&
(UsbClassCReg.SubClassCode == PCI_CLASS_SERIAL_USB)) {
Status = Instance->GetLocation (

2
MdeModulePkg/Bus/Pci/EhciDxe/Ehci.h
View File

@ -33,7 +33,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#include <Library/MemoryAllocationLib.h>
#include <Library/PcdLib.h>
#include <IndustryStandard/Pci22.h>
#include <IndustryStandard/Pci.h>
typedef struct _USB2_HC_DEV USB2_HC_DEV;

2
MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.h
View File

@ -83,8 +83,6 @@ typedef enum {
//
// PCI Configuration Registers
//
EHC_PCI_CLASSC = 0x09,
EHC_PCI_CLASSC_PI = 0x20,
EHC_BAR_INDEX = 0 /* how many bytes away from USB_BASE to 0x10 */
}EHCI_REGISTER_OFFSET;

3
MdeModulePkg/Bus/Pci/EhciDxe/UsbHcMem.h
View File

@ -16,9 +16,6 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#ifndef _EFI_EHCI_MEM_H_
#define _EFI_EHCI_MEM_H_
#include <IndustryStandard/Pci22.h>
#define USB_HC_BIT(a) ((UINTN)(1 << (a)))
#define USB_HC_BIT_IS_SET(Data, Bit) \

4
MdeModulePkg/Bus/Pci/UhciDxe/Uhci.c
View File

@ -1391,7 +1391,7 @@ UhciDriverBindingSupported (
Status = PciIo->Pci.Read (
PciIo,
EfiPciIoWidthUint8,
CLASSC_OFFSET,
PCI_CLASSCODE_OFFSET,
sizeof (USB_CLASSC) / sizeof (UINT8),
&UsbClassCReg
);
@ -1406,7 +1406,7 @@ UhciDriverBindingSupported (
//
if ((UsbClassCReg.BaseCode != PCI_CLASS_SERIAL) ||
(UsbClassCReg.SubClassCode != PCI_CLASS_SERIAL_USB) ||
(UsbClassCReg.PI != PCI_CLASSC_PI_UHCI)
(UsbClassCReg.PI != PCI_IF_UHCI)
) {
Status = EFI_UNSUPPORTED;

2
MdeModulePkg/Bus/Pci/UhciDxe/Uhci.h
View File

@ -34,7 +34,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#include <Library/MemoryAllocationLib.h>
#include <Library/PcdLib.h>
#include <IndustryStandard/Pci22.h>
#include <IndustryStandard/Pci.h>
typedef struct _USB_HC_DEV USB_HC_DEV;

67
MdeModulePkg/Bus/Pci/UhciDxe/UhciReg.h
View File

@ -16,18 +16,13 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#ifndef _EFI_UHCI_REG_H_
#define _EFI_UHCI_REG_H_
#define BIT(a) (1 << (a))
typedef enum {
UHCI_FRAME_NUM = 1024,
//
// Register offset and PCI related staff
//
CLASSC_OFFSET = 0x09,
USBBASE_OFFSET = 0x20,
USB_BAR_INDEX = 4,
PCI_CLASSC_PI_UHCI = 0x00,
USBCMD_OFFSET = 0,
USBSTS_OFFSET = 2,
@ -48,16 +43,16 @@ typedef enum {
//
// USB port status and control bit definition.
//
USBPORTSC_CCS = BIT(0), // Current Connect Status
USBPORTSC_CSC = BIT(1), // Connect Status Change
USBPORTSC_PED = BIT(2), // Port Enable / Disable
USBPORTSC_PEDC = BIT(3), // Port Enable / Disable Change
USBPORTSC_LSL = BIT(4), // Line Status Low BIT
USBPORTSC_LSH = BIT(5), // Line Status High BIT
USBPORTSC_RD = BIT(6), // Resume Detect
USBPORTSC_LSDA = BIT(8), // Low Speed Device Attached
USBPORTSC_PR = BIT(9), // Port Reset
USBPORTSC_SUSP = BIT(12), // Suspend
USBPORTSC_CCS = BIT0, // Current Connect Status
USBPORTSC_CSC = BIT1, // Connect Status Change
USBPORTSC_PED = BIT2, // Port Enable / Disable
USBPORTSC_PEDC = BIT3, // Port Enable / Disable Change
USBPORTSC_LSL = BIT4, // Line Status Low BIT
USBPORTSC_LSH = BIT5, // Line Status High BIT
USBPORTSC_RD = BIT6, // Resume Detect
USBPORTSC_LSDA = BIT8, // Low Speed Device Attached
USBPORTSC_PR = BIT9, // Port Reset
USBPORTSC_SUSP = BIT12, // Suspend
//
// UHCI Spec said it must implement 2 ports each host at least,
@ -69,32 +64,32 @@ typedef enum {
//
// Command register bit definitions
//
USBCMD_RS = BIT(0), // Run/Stop
USBCMD_HCRESET = BIT(1), // Host reset
USBCMD_GRESET = BIT(2), // Global reset
USBCMD_EGSM = BIT(3), // Global Suspend Mode
USBCMD_FGR = BIT(4), // Force Global Resume
USBCMD_SWDBG = BIT(5), // SW Debug mode
USBCMD_CF = BIT(6), // Config Flag (sw only)
USBCMD_MAXP = BIT(7), // Max Packet (0 = 32, 1 = 64)
USBCMD_RS = BIT0, // Run/Stop
USBCMD_HCRESET = BIT1, // Host reset
USBCMD_GRESET = BIT2, // Global reset
USBCMD_EGSM = BIT3, // Global Suspend Mode
USBCMD_FGR = BIT4, // Force Global Resume
USBCMD_SWDBG = BIT5, // SW Debug mode
USBCMD_CF = BIT6, // Config Flag (sw only)
USBCMD_MAXP = BIT7, // Max Packet (0 = 32, 1 = 64)
//
// USB Status register bit definitions
//
USBSTS_USBINT = BIT(0), // Interrupt due to IOC
USBSTS_ERROR = BIT(1), // Interrupt due to error
USBSTS_RD = BIT(2), // Resume Detect
USBSTS_HSE = BIT(3), // Host System Error
USBSTS_HCPE = BIT(4), // Host Controller Process Error
USBSTS_HCH = BIT(5), // HC Halted
USBSTS_USBINT = BIT0, // Interrupt due to IOC
USBSTS_ERROR = BIT1, // Interrupt due to error
USBSTS_RD = BIT2, // Resume Detect
USBSTS_HSE = BIT3, // Host System Error
USBSTS_HCPE = BIT4, // Host Controller Process Error
USBSTS_HCH = BIT5, // HC Halted
USBTD_ACTIVE = BIT(7), // TD is still active
USBTD_STALLED = BIT(6), // TD is stalled
USBTD_BUFFERR = BIT(5), // Buffer underflow or overflow
USBTD_BABBLE = BIT(4), // Babble condition
USBTD_NAK = BIT(3), // NAK is received
USBTD_CRC = BIT(2), // CRC/Time out error
USBTD_BITSTUFF = BIT(1) // Bit stuff error
USBTD_ACTIVE = BIT7, // TD is still active
USBTD_STALLED = BIT6, // TD is stalled
USBTD_BUFFERR = BIT5, // Buffer underflow or overflow
USBTD_BABBLE = BIT4, // Babble condition
USBTD_NAK = BIT3, // NAK is received
USBTD_CRC = BIT2, // CRC/Time out error
USBTD_BITSTUFF = BIT1 // Bit stuff error
}UHCI_REGISTER_OFFSET;

2
MdeModulePkg/Bus/Pci/UhciDxe/UsbHcMem.h
View File

@ -16,8 +16,6 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#ifndef _EFI_EHCI_MEM_H_
#define _EFI_EHCI_MEM_H_
#include <IndustryStandard/Pci22.h>
#define USB_HC_BIT(a) ((UINTN)(1 << (a)))
#define USB_HC_BIT_IS_SET(Data, Bit) \