mirror of https://github.com/acidanthera/audk.git
ArmPkg/ArmLib: ASSERT on set/way cache ops being used with MMU on
On ARMv7 and up, doing cache maintenance by set/way is only permitted in the context of on/offlining a core, and any other uses should be avoided. Add ASSERT()s in the right place to ensure that any uses with the MMU enabled are caught in DEBUG builds. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
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@ -10,6 +10,7 @@
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#include <Base.h>
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#include <Library/ArmLib.h>
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#include <Library/DebugLib.h>
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#include <Chipset/AArch64.h>
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@ -41,6 +42,8 @@ ArmInvalidateDataCache (
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VOID
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)
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{
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ASSERT (!ArmMmuEnabled ());
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ArmDataSynchronizationBarrier ();
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AArch64DataCacheOperation (ArmInvalidateDataCacheEntryBySetWay);
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}
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@ -51,6 +54,8 @@ ArmCleanInvalidateDataCache (
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VOID
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)
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{
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ASSERT (!ArmMmuEnabled ());
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ArmDataSynchronizationBarrier ();
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AArch64DataCacheOperation (ArmCleanInvalidateDataCacheEntryBySetWay);
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}
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@ -61,6 +66,8 @@ ArmCleanDataCache (
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VOID
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)
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{
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ASSERT (!ArmMmuEnabled ());
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ArmDataSynchronizationBarrier ();
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AArch64DataCacheOperation (ArmCleanDataCacheEntryBySetWay);
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}
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@ -10,6 +10,7 @@
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#include <Base.h>
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#include <Library/ArmLib.h>
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#include <Library/DebugLib.h>
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#include <Chipset/ArmV7.h>
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@ -41,6 +42,8 @@ ArmInvalidateDataCache (
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VOID
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)
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{
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ASSERT (!ArmMmuEnabled ());
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ArmDataSynchronizationBarrier ();
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ArmV7DataCacheOperation (ArmInvalidateDataCacheEntryBySetWay);
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}
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@ -51,6 +54,8 @@ ArmCleanInvalidateDataCache (
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VOID
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)
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{
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ASSERT (!ArmMmuEnabled ());
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ArmDataSynchronizationBarrier ();
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ArmV7DataCacheOperation (ArmCleanInvalidateDataCacheEntryBySetWay);
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}
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@ -61,6 +66,8 @@ ArmCleanDataCache (
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VOID
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)
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{
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ASSERT (!ArmMmuEnabled ());
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ArmDataSynchronizationBarrier ();
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ArmV7DataCacheOperation (ArmCleanDataCacheEntryBySetWay);
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}
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@ -44,6 +44,9 @@
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AArch64/AArch64Support.S
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AArch64/AArch64ArchTimerSupport.S
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[LibraryClasses]
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DebugLib
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[Packages]
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ArmPkg/ArmPkg.dec
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MdePkg/MdePkg.dec
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