mirror of https://github.com/acidanthera/audk.git
Add CPU DXE driver for IA32 & X64 processor architectures.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@8395 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
jljusten
parent
e50466da24
commit
a47463f283
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/** @file
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CPU DXE Module.
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Copyright (c) 2008 - 2009, Intel Corporation
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All rights reserved. This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef _CPU_DXE_H
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#define _CPU_DXE_H
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#include <PiDxe.h>
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#include <Protocol/Cpu.h>
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#include <Library/UefiDriverEntryPoint.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <Library/DxeServicesTableLib.h>
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#include <Library/BaseLib.h>
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#include <Library/CpuLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/DebugLib.h>
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#include <Library/MtrrLib.h>
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//
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//
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//
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#define INTERRUPT_VECTOR_NUMBER 256
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#define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC | \
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EFI_MEMORY_WC | \
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EFI_MEMORY_WT | \
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EFI_MEMORY_WB | \
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EFI_MEMORY_UCE \
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)
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//
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// Function declarations
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//
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EFI_STATUS
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EFIAPI
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CpuFlushCpuDataCache (
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IN EFI_CPU_ARCH_PROTOCOL *This,
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IN EFI_PHYSICAL_ADDRESS Start,
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IN UINT64 Length,
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IN EFI_CPU_FLUSH_TYPE FlushType
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);
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EFI_STATUS
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EFIAPI
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CpuEnableInterrupt (
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IN EFI_CPU_ARCH_PROTOCOL *This
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);
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EFI_STATUS
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EFIAPI
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CpuDisableInterrupt (
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IN EFI_CPU_ARCH_PROTOCOL *This
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);
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EFI_STATUS
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EFIAPI
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CpuGetInterruptState (
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IN EFI_CPU_ARCH_PROTOCOL *This,
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OUT BOOLEAN *State
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);
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EFI_STATUS
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EFIAPI
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CpuInit (
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IN EFI_CPU_ARCH_PROTOCOL *This,
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IN EFI_CPU_INIT_TYPE InitType
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);
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EFI_STATUS
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EFIAPI
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CpuRegisterInterruptHandler (
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IN EFI_CPU_ARCH_PROTOCOL *This,
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IN EFI_EXCEPTION_TYPE InterruptType,
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IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
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);
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EFI_STATUS
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EFIAPI
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CpuGetTimerValue (
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IN EFI_CPU_ARCH_PROTOCOL *This,
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IN UINT32 TimerIndex,
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OUT UINT64 *TimerValue,
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OUT UINT64 *TimerPeriod OPTIONAL
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);
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EFI_STATUS
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EFIAPI
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CpuSetMemoryAttributes (
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IN EFI_CPU_ARCH_PROTOCOL *This,
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IN EFI_PHYSICAL_ADDRESS BaseAddress,
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IN UINT64 Length,
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IN UINT64 Attributes
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);
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VOID
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EFIAPI
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AsmIdtVector00 (
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VOID
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);
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VOID
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EFIAPI
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InitializeExternalVectorTablePtr (
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EFI_CPU_INTERRUPT_HANDLER *VectorTable
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);
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VOID
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InitGlobalDescriptorTable (
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VOID
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);
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VOID
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EFIAPI
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SetCodeSelector (
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UINT16 Selector
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);
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VOID
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EFIAPI
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SetDataSelectors (
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UINT16 Selector
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);
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#endif
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@ -0,0 +1,67 @@
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#/** @file
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#
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# Component description file for simple CPU driver
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#
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# Copyright (c) 2008 - 2009, Intel Corporation. <BR>
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# All rights reserved. This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#**/
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[Defines]
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INF_VERSION = 0x00010005
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BASE_NAME = CpuDxe
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FILE_GUID = 62D171CB-78CD-4480-8678-C6A2A797A8DE
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MODULE_TYPE = DXE_DRIVER
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VERSION_STRING = 1.0
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EDK_RELEASE_VERSION = 0x00020000
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EFI_SPECIFICATION_VERSION = 0x0002000A
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ENTRY_POINT = InitializeCpu
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[Packages]
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OvmfPkg/OvmfPkg.dec
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MdePkg/MdePkg.dec
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UefiCpuPkg/UefiCpuPkg.dec
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[LibraryClasses]
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BaseLib
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BaseMemoryLib
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CpuLib
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DebugLib
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DxeServicesTableLib
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MemoryAllocationLib
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MtrrLib
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UefiBootServicesTableLib
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UefiDriverEntryPoint
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[Sources]
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CpuDxe.c
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CpuDxe.h
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CpuGdt.c
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Ia32/IvtAsm.asm | MSFT
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Ia32/IvtAsm.asm | INTEL
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Ia32/IvtAsm.S | GCC
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[Sources.IA32]
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Ia32/CpuAsm.asm | MSFT
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Ia32/CpuAsm.asm | INTEL
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Ia32/CpuAsm.S | GCC
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[Sources.X64]
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X64/CpuAsm.asm | MSFT
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X64/CpuAsm.asm | INTEL
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X64/CpuAsm.S | GCC
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[Protocols]
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gEfiCpuArchProtocolGuid
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[Depex]
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TRUE
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/** @file
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C based implemention of IA32 interrupt handling only
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requiring a minimal assembly interrupt entry point.
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Copyright (c) 2006 - 2009, Intel Corporation
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All rights reserved. This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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|
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include "CpuDxe.h"
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//
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// Local structure definitions
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//
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#pragma pack (1)
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//
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// Global Descriptor Entry structures
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//
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typedef
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struct _GDT_ENTRY {
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UINT16 limit15_0;
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UINT16 base15_0;
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UINT8 base23_16;
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UINT8 type;
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UINT8 limit19_16_and_flags;
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UINT8 base31_24;
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} GDT_ENTRY;
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typedef
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struct _GDT_ENTRIES {
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GDT_ENTRY Null;
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GDT_ENTRY Linear;
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GDT_ENTRY LinearCode;
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GDT_ENTRY SysData;
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GDT_ENTRY SysCode;
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GDT_ENTRY LinearCode64;
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GDT_ENTRY Spare4;
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GDT_ENTRY Spare5;
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} GDT_ENTRIES;
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#define NULL_SEL OFFSET_OF (GDT_ENTRIES, Null)
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#define LINEAR_SEL OFFSET_OF (GDT_ENTRIES, Linear)
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#define LINEAR_CODE_SEL OFFSET_OF (GDT_ENTRIES, LinearCode)
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#define SYS_DATA_SEL OFFSET_OF (GDT_ENTRIES, SysData)
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#define SYS_CODE_SEL OFFSET_OF (GDT_ENTRIES, SysCode)
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#define LINEAR_CODE64_SEL OFFSET_OF (GDT_ENTRIES, LinearCode64)
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#define SPARE4_SEL OFFSET_OF (GDT_ENTRIES, Spare4)
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#define SPARE5_SEL OFFSET_OF (GDT_ENTRIES, Spare5)
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#if defined (MDE_CPU_IA32)
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#define CPU_CODE_SEL LINEAR_CODE_SEL
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#define CPU_DATA_SEL LINEAR_SEL
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#elif defined (MDE_CPU_X64)
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#define CPU_CODE_SEL LINEAR_CODE64_SEL
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#define CPU_DATA_SEL LINEAR_SEL
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#else
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#error CPU type not supported for CPU GDT initialization!
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#endif
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//
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// Global descriptor table (GDT) Template
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//
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STATIC GDT_ENTRIES GdtTemplate = {
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//
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// NULL_SEL
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//
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{
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0x0, // limit 15:0
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0x0, // base 15:0
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0x0, // base 23:16
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0x0, // type
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0x0, // limit 19:16, flags
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0x0, // base 31:24
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},
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//
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// LINEAR_SEL
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//
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{
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0x0FFFF, // limit 0xFFFFF
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0x0, // base 0
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0x0,
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0x092, // present, ring 0, data, expand-up, writable
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0x0CF, // page-granular, 32-bit
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0x0,
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},
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//
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// LINEAR_CODE_SEL
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//
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{
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0x0FFFF, // limit 0xFFFFF
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0x0, // base 0
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0x0,
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0x09A, // present, ring 0, data, expand-up, writable
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0x0CF, // page-granular, 32-bit
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0x0,
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},
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//
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// SYS_DATA_SEL
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//
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{
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0x0FFFF, // limit 0xFFFFF
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0x0, // base 0
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0x0,
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0x092, // present, ring 0, data, expand-up, writable
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0x0CF, // page-granular, 32-bit
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0x0,
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},
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//
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// SYS_CODE_SEL
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//
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{
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0x0FFFF, // limit 0xFFFFF
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0x0, // base 0
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0x0,
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0x09A, // present, ring 0, data, expand-up, writable
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0x0CF, // page-granular, 32-bit
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0x0,
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},
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//
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// LINEAR_CODE64_SEL
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//
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{
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0x0FFFF, // limit 0xFFFFF
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0x0, // base 0
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0x0,
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0x09B, // present, ring 0, code, expand-up, writable
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0x0AF, // LimitHigh (CS.L=1, CS.D=0)
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0x0, // base (high)
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},
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//
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// SPARE4_SEL
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//
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{
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0x0, // limit 0
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0x0, // base 0
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0x0,
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0x0, // present, ring 0, data, expand-up, writable
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0x0, // page-granular, 32-bit
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0x0,
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},
|
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//
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// SPARE5_SEL
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//
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{
|
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0x0, // limit 0
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0x0, // base 0
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0x0,
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0x0, // present, ring 0, data, expand-up, writable
|
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0x0, // page-granular, 32-bit
|
||||
0x0,
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},
|
||||
};
|
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|
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/**
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Initialize Global Descriptor Table
|
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|
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**/
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VOID
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InitGlobalDescriptorTable (
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)
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{
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GDT_ENTRIES *gdt;
|
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IA32_DESCRIPTOR gdtPtr;
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|
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//
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// Allocate Runtime Data for the GDT
|
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//
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gdt = AllocateRuntimePool (sizeof (GdtTemplate) + 8);
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ASSERT (gdt != NULL);
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gdt = ALIGN_POINTER (gdt, 8);
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|
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//
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// Initialize all GDT entries
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//
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CopyMem (gdt, &GdtTemplate, sizeof (GdtTemplate));
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|
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//
|
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// Write GDT register
|
||||
//
|
||||
gdtPtr.Base = (UINT32)(UINTN)(VOID*) gdt;
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gdtPtr.Limit = sizeof (GdtTemplate) - 1;
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AsmWriteGdtr (&gdtPtr);
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|
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//
|
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// Update selector (segment) registers base on new GDT
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//
|
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SetCodeSelector ((UINT16)CPU_CODE_SEL);
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SetDataSelectors ((UINT16)CPU_DATA_SEL);
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}
|
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|
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|
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@ -0,0 +1,395 @@
|
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#
|
||||
# ConvertAsm.py: Automatically generated from CpuAsm.asm
|
||||
#
|
||||
# TITLE CpuAsm.asm:
|
||||
|
||||
#------------------------------------------------------------------------------
|
||||
#*
|
||||
#* Copyright 2006 - 2009, Intel Corporation
|
||||
#* All rights reserved. This program and the accompanying materials
|
||||
#* are licensed and made available under the terms and conditions of the BSD License
|
||||
#* which accompanies this distribution. The full text of the license may be found at
|
||||
#* http://opensource.org/licenses/bsd-license.php
|
||||
#*
|
||||
#* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
#* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
#*
|
||||
#* CpuAsm.S
|
||||
#*
|
||||
#* Abstract:
|
||||
#*
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
|
||||
#.MMX
|
||||
#.XMM
|
||||
|
||||
#EXTRN ASM_PFX(mErrorCodeFlag):DWORD # Error code flags for exceptions
|
||||
|
||||
|
||||
#
|
||||
# point to the external interrupt vector table
|
||||
#
|
||||
ExternalVectorTablePtr:
|
||||
.byte 0, 0, 0, 0
|
||||
|
||||
.intel_syntax
|
||||
ASM_GLOBAL ASM_PFX(InitializeExternalVectorTablePtr)
|
||||
ASM_PFX(InitializeExternalVectorTablePtr):
|
||||
mov eax, [esp+4]
|
||||
mov ExternalVectorTablePtr, eax
|
||||
ret
|
||||
|
||||
#------------------------------------------------------------------------------
|
||||
# VOID
|
||||
# SetCodeSelector (
|
||||
# UINT16 Selector
|
||||
# );
|
||||
#------------------------------------------------------------------------------
|
||||
.intel_syntax
|
||||
ASM_GLOBAL ASM_PFX(SetCodeSelector)
|
||||
ASM_PFX(SetCodeSelector):
|
||||
mov %ecx, [%esp+4]
|
||||
sub %esp, 0x10
|
||||
lea %eax, setCodeSelectorLongJump
|
||||
mov [%esp], %eax
|
||||
mov [%esp+4], %cx
|
||||
jmp fword ptr [%esp]
|
||||
setCodeSelectorLongJump:
|
||||
add %esp, 0x10
|
||||
ret
|
||||
|
||||
#------------------------------------------------------------------------------
|
||||
# VOID
|
||||
# SetDataSelectors (
|
||||
# UINT16 Selector
|
||||
# );
|
||||
#------------------------------------------------------------------------------
|
||||
.intel_syntax
|
||||
ASM_GLOBAL ASM_PFX(SetDataSelectors)
|
||||
ASM_PFX(SetDataSelectors):
|
||||
mov %ecx, [%esp+4]
|
||||
mov %ss, %cx
|
||||
mov %ds, %cx
|
||||
mov %es, %cx
|
||||
mov %fs, %cx
|
||||
mov %gs, %cx
|
||||
ret
|
||||
|
||||
#---------------------------------------;
|
||||
# CommonInterruptEntry ;
|
||||
#---------------------------------------;
|
||||
# The follow algorithm is used for the common interrupt routine.
|
||||
|
||||
.intel_syntax
|
||||
ASM_GLOBAL ASM_PFX(CommonInterruptEntry)
|
||||
ASM_PFX(CommonInterruptEntry):
|
||||
cli
|
||||
#
|
||||
# All interrupt handlers are invoked through interrupt gates, so
|
||||
# IF flag automatically cleared at the entry point
|
||||
#
|
||||
|
||||
#
|
||||
# Calculate vector number
|
||||
#
|
||||
# Get the return address of call, actually, it is the
|
||||
# address of vector number.
|
||||
#
|
||||
xchg ecx, [esp]
|
||||
mov cx, [ecx]
|
||||
and ecx, 0x0FFFF
|
||||
cmp ecx, 32 # Intel reserved vector for exceptions?
|
||||
jae NoErrorCode
|
||||
bt ASM_PFX(mErrorCodeFlag), ecx
|
||||
jc HasErrorCode
|
||||
|
||||
NoErrorCode:
|
||||
|
||||
#
|
||||
# Stack:
|
||||
# +---------------------+
|
||||
# + EFlags +
|
||||
# +---------------------+
|
||||
# + CS +
|
||||
# +---------------------+
|
||||
# + EIP +
|
||||
# +---------------------+
|
||||
# + ECX +
|
||||
# +---------------------+ <-- ESP
|
||||
#
|
||||
# Registers:
|
||||
# ECX - Vector Number
|
||||
#
|
||||
|
||||
#
|
||||
# Put Vector Number on stack
|
||||
#
|
||||
push ecx
|
||||
|
||||
#
|
||||
# Put 0 (dummy) error code on stack, and restore ECX
|
||||
#
|
||||
xor ecx, ecx # ECX = 0
|
||||
xchg ecx, [esp+4]
|
||||
|
||||
jmp ErrorCodeAndVectorOnStack
|
||||
|
||||
HasErrorCode:
|
||||
|
||||
#
|
||||
# Stack:
|
||||
# +---------------------+
|
||||
# + EFlags +
|
||||
# +---------------------+
|
||||
# + CS +
|
||||
# +---------------------+
|
||||
# + EIP +
|
||||
# +---------------------+
|
||||
# + Error Code +
|
||||
# +---------------------+
|
||||
# + ECX +
|
||||
# +---------------------+ <-- ESP
|
||||
#
|
||||
# Registers:
|
||||
# ECX - Vector Number
|
||||
#
|
||||
|
||||
#
|
||||
# Put Vector Number on stack and restore ECX
|
||||
#
|
||||
xchg ecx, [esp]
|
||||
|
||||
#
|
||||
# Fall through to join main routine code
|
||||
# at ErrorCodeAndVectorOnStack
|
||||
#
|
||||
CommonInterruptEntry_al_0000:
|
||||
jmp CommonInterruptEntry_al_0000
|
||||
|
||||
ErrorCodeAndVectorOnStack:
|
||||
push ebp
|
||||
mov ebp, esp
|
||||
|
||||
#
|
||||
# Stack:
|
||||
# +---------------------+
|
||||
# + EFlags +
|
||||
# +---------------------+
|
||||
# + CS +
|
||||
# +---------------------+
|
||||
# + EIP +
|
||||
# +---------------------+
|
||||
# + Error Code +
|
||||
# +---------------------+
|
||||
# + Vector Number +
|
||||
# +---------------------+
|
||||
# + EBP +
|
||||
# +---------------------+ <-- EBP
|
||||
#
|
||||
|
||||
#
|
||||
# Align stack to make sure that EFI_FX_SAVE_STATE_IA32 of EFI_SYSTEM_CONTEXT_IA32
|
||||
# is 16-byte aligned
|
||||
#
|
||||
and esp, 0x0fffffff0
|
||||
sub esp, 12
|
||||
|
||||
#; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
|
||||
push eax
|
||||
push ecx
|
||||
push edx
|
||||
push ebx
|
||||
lea ecx, [ebp + 6 * 4]
|
||||
push ecx # ESP
|
||||
push dword ptr [ebp] # EBP
|
||||
push esi
|
||||
push edi
|
||||
|
||||
#; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
|
||||
mov eax, ss
|
||||
push eax
|
||||
movzx eax, word ptr [ebp + 4 * 4]
|
||||
push eax
|
||||
mov eax, ds
|
||||
push eax
|
||||
mov eax, es
|
||||
push eax
|
||||
mov eax, fs
|
||||
push eax
|
||||
mov eax, gs
|
||||
push eax
|
||||
|
||||
#; UINT32 Eip;
|
||||
mov eax, [ebp + 3 * 4]
|
||||
push eax
|
||||
|
||||
#; UINT32 Gdtr[2], Idtr[2];
|
||||
sub esp, 8
|
||||
sidt [esp]
|
||||
mov eax, [esp + 2]
|
||||
xchg eax, [esp]
|
||||
and eax, 0x0FFFF
|
||||
mov [esp+4], eax
|
||||
|
||||
sub esp, 8
|
||||
sgdt [esp]
|
||||
mov eax, [esp + 2]
|
||||
xchg eax, [esp]
|
||||
and eax, 0x0FFFF
|
||||
mov [esp+4], eax
|
||||
|
||||
#; UINT32 Ldtr, Tr;
|
||||
xor eax, eax
|
||||
str ax
|
||||
push eax
|
||||
sldt ax
|
||||
push eax
|
||||
|
||||
#; UINT32 EFlags;
|
||||
mov eax, [ebp + 5 * 4]
|
||||
push eax
|
||||
|
||||
#; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
|
||||
mov eax, cr4
|
||||
or eax, 0x208
|
||||
mov cr4, eax
|
||||
push eax
|
||||
mov eax, cr3
|
||||
push eax
|
||||
mov eax, cr2
|
||||
push eax
|
||||
xor eax, eax
|
||||
push eax
|
||||
mov eax, cr0
|
||||
push eax
|
||||
|
||||
#; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
|
||||
mov eax, dr7
|
||||
push eax
|
||||
#; clear Dr7 while executing debugger itself
|
||||
xor eax, eax
|
||||
mov dr7, eax
|
||||
|
||||
mov eax, dr6
|
||||
push eax
|
||||
#; insure all status bits in dr6 are clear...
|
||||
xor eax, eax
|
||||
mov dr6, eax
|
||||
|
||||
mov eax, dr3
|
||||
push eax
|
||||
mov eax, dr2
|
||||
push eax
|
||||
mov eax, dr1
|
||||
push eax
|
||||
mov eax, dr0
|
||||
push eax
|
||||
|
||||
#; FX_SAVE_STATE_IA32 FxSaveState;
|
||||
sub esp, 512
|
||||
mov edi, esp
|
||||
.byte 0x0f, 0x0ae, 0x07 #fxsave [edi]
|
||||
|
||||
#; UINT32 ExceptionData;
|
||||
push dword ptr [ebp + 2 * 4]
|
||||
|
||||
#; call into exception handler
|
||||
mov eax, ExternalVectorTablePtr # get the interrupt vectors base
|
||||
or eax, eax # NULL?
|
||||
jz nullExternalExceptionHandler
|
||||
|
||||
mov ecx, [ebp + 4]
|
||||
mov eax, [eax + ecx * 4]
|
||||
or eax, eax # NULL?
|
||||
jz nullExternalExceptionHandler
|
||||
|
||||
#; Prepare parameter and call
|
||||
mov edx, esp
|
||||
push edx
|
||||
mov edx, dword ptr [ebp + 1 * 4]
|
||||
push edx
|
||||
|
||||
#
|
||||
# Call External Exception Handler
|
||||
#
|
||||
call eax
|
||||
add esp, 8
|
||||
|
||||
nullExternalExceptionHandler:
|
||||
|
||||
cli
|
||||
#; UINT32 ExceptionData;
|
||||
add esp, 4
|
||||
|
||||
#; FX_SAVE_STATE_IA32 FxSaveState;
|
||||
mov esi, esp
|
||||
.byte 0x0f, 0x0ae, 0x0e # fxrstor [esi]
|
||||
add esp, 512
|
||||
|
||||
#; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
|
||||
pop eax
|
||||
mov dr0, eax
|
||||
pop eax
|
||||
mov dr1, eax
|
||||
pop eax
|
||||
mov dr2, eax
|
||||
pop eax
|
||||
mov dr3, eax
|
||||
#; skip restore of dr6. We cleared dr6 during the context save.
|
||||
add esp, 4
|
||||
pop eax
|
||||
mov dr7, eax
|
||||
|
||||
#; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
|
||||
pop eax
|
||||
mov cr0, eax
|
||||
add esp, 4 # not for Cr1
|
||||
pop eax
|
||||
mov cr2, eax
|
||||
pop eax
|
||||
mov cr3, eax
|
||||
pop eax
|
||||
mov cr4, eax
|
||||
|
||||
#; UINT32 EFlags;
|
||||
pop dword ptr [ebp + 5 * 4]
|
||||
|
||||
#; UINT32 Ldtr, Tr;
|
||||
#; UINT32 Gdtr[2], Idtr[2];
|
||||
#; Best not let anyone mess with these particular registers...
|
||||
add esp, 24
|
||||
|
||||
#; UINT32 Eip;
|
||||
pop dword ptr [ebp + 3 * 4]
|
||||
|
||||
#; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
|
||||
#; NOTE - modified segment registers could hang the debugger... We
|
||||
#; could attempt to insulate ourselves against this possibility,
|
||||
#; but that poses risks as well.
|
||||
#;
|
||||
pop gs
|
||||
pop fs
|
||||
pop es
|
||||
pop ds
|
||||
pop dword ptr [ebp + 4 * 4]
|
||||
pop ss
|
||||
|
||||
#; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
|
||||
pop edi
|
||||
pop esi
|
||||
add esp, 4 # not for ebp
|
||||
add esp, 4 # not for esp
|
||||
pop ebx
|
||||
pop edx
|
||||
pop ecx
|
||||
pop eax
|
||||
|
||||
mov esp, ebp
|
||||
pop ebp
|
||||
add esp, 8
|
||||
iretd
|
||||
|
||||
|
||||
#END
|
||||
|
||||
|
|
@ -0,0 +1,384 @@
|
|||
TITLE CpuAsm.asm:
|
||||
;------------------------------------------------------------------------------
|
||||
;*
|
||||
;* Copyright 2006 - 2009, Intel Corporation
|
||||
;* All rights reserved. This program and the accompanying materials
|
||||
;* are licensed and made available under the terms and conditions of the BSD License
|
||||
;* which accompanies this distribution. The full text of the license may be found at
|
||||
;* http://opensource.org/licenses/bsd-license.php
|
||||
;*
|
||||
;* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
;* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
;*
|
||||
;* CpuAsm.asm
|
||||
;*
|
||||
;* Abstract:
|
||||
;*
|
||||
;------------------------------------------------------------------------------
|
||||
|
||||
.686
|
||||
.model flat,C
|
||||
.code
|
||||
|
||||
EXTRN mErrorCodeFlag:DWORD ; Error code flags for exceptions
|
||||
|
||||
;
|
||||
; point to the external interrupt vector table
|
||||
;
|
||||
ExternalVectorTablePtr DWORD 0
|
||||
|
||||
InitializeExternalVectorTablePtr PROC PUBLIC
|
||||
mov eax, [esp+4]
|
||||
mov ExternalVectorTablePtr, eax
|
||||
ret
|
||||
InitializeExternalVectorTablePtr ENDP
|
||||
|
||||
;------------------------------------------------------------------------------
|
||||
; VOID
|
||||
; SetCodeSelector (
|
||||
; UINT16 Selector
|
||||
; );
|
||||
;------------------------------------------------------------------------------
|
||||
SetCodeSelector PROC PUBLIC
|
||||
mov ecx, [esp+4]
|
||||
sub esp, 0x10
|
||||
lea eax, setCodeSelectorLongJump
|
||||
mov [esp], eax
|
||||
mov [esp+4], cx
|
||||
jmp fword ptr [esp]
|
||||
setCodeSelectorLongJump:
|
||||
add esp, 0x10
|
||||
ret
|
||||
SetCodeSelector ENDP
|
||||
|
||||
;------------------------------------------------------------------------------
|
||||
; VOID
|
||||
; SetDataSelectors (
|
||||
; UINT16 Selector
|
||||
; );
|
||||
;------------------------------------------------------------------------------
|
||||
SetDataSelectors PROC PUBLIC
|
||||
mov ecx, [esp+4]
|
||||
mov ss, cx
|
||||
mov ds, cx
|
||||
mov es, cx
|
||||
mov fs, cx
|
||||
mov gs, cx
|
||||
ret
|
||||
SetDataSelectors ENDP
|
||||
|
||||
;---------------------------------------;
|
||||
; CommonInterruptEntry ;
|
||||
;---------------------------------------;
|
||||
; The follow algorithm is used for the common interrupt routine.
|
||||
|
||||
CommonInterruptEntry PROC PUBLIC
|
||||
cli
|
||||
;
|
||||
; All interrupt handlers are invoked through interrupt gates, so
|
||||
; IF flag automatically cleared at the entry point
|
||||
;
|
||||
|
||||
;
|
||||
; Calculate vector number
|
||||
;
|
||||
; Get the return address of call, actually, it is the
|
||||
; address of vector number.
|
||||
;
|
||||
xchg ecx, [esp]
|
||||
mov cx, [ecx]
|
||||
and ecx, 0FFFFh
|
||||
cmp ecx, 32 ; Intel reserved vector for exceptions?
|
||||
jae NoErrorCode
|
||||
bt mErrorCodeFlag, ecx
|
||||
jc HasErrorCode
|
||||
|
||||
NoErrorCode:
|
||||
|
||||
;
|
||||
; Stack:
|
||||
; +---------------------+
|
||||
; + EFlags +
|
||||
; +---------------------+
|
||||
; + CS +
|
||||
; +---------------------+
|
||||
; + EIP +
|
||||
; +---------------------+
|
||||
; + ECX +
|
||||
; +---------------------+ <-- ESP
|
||||
;
|
||||
; Registers:
|
||||
; ECX - Vector Number
|
||||
;
|
||||
|
||||
;
|
||||
; Put Vector Number on stack
|
||||
;
|
||||
push ecx
|
||||
|
||||
;
|
||||
; Put 0 (dummy) error code on stack, and restore ECX
|
||||
;
|
||||
xor ecx, ecx ; ECX = 0
|
||||
xchg ecx, [esp+4]
|
||||
|
||||
jmp ErrorCodeAndVectorOnStack
|
||||
|
||||
HasErrorCode:
|
||||
|
||||
;
|
||||
; Stack:
|
||||
; +---------------------+
|
||||
; + EFlags +
|
||||
; +---------------------+
|
||||
; + CS +
|
||||
; +---------------------+
|
||||
; + EIP +
|
||||
; +---------------------+
|
||||
; + Error Code +
|
||||
; +---------------------+
|
||||
; + ECX +
|
||||
; +---------------------+ <-- ESP
|
||||
;
|
||||
; Registers:
|
||||
; ECX - Vector Number
|
||||
;
|
||||
|
||||
;
|
||||
; Put Vector Number on stack and restore ECX
|
||||
;
|
||||
xchg ecx, [esp]
|
||||
|
||||
;
|
||||
; Fall through to join main routine code
|
||||
; at ErrorCodeAndVectorOnStack
|
||||
;
|
||||
@@:
|
||||
jmp @B
|
||||
|
||||
ErrorCodeAndVectorOnStack:
|
||||
push ebp
|
||||
mov ebp, esp
|
||||
|
||||
;
|
||||
; Stack:
|
||||
; +---------------------+
|
||||
; + EFlags +
|
||||
; +---------------------+
|
||||
; + CS +
|
||||
; +---------------------+
|
||||
; + EIP +
|
||||
; +---------------------+
|
||||
; + Error Code +
|
||||
; +---------------------+
|
||||
; + Vector Number +
|
||||
; +---------------------+
|
||||
; + EBP +
|
||||
; +---------------------+ <-- EBP
|
||||
;
|
||||
|
||||
;
|
||||
; Align stack to make sure that EFI_FX_SAVE_STATE_IA32 of EFI_SYSTEM_CONTEXT_IA32
|
||||
; is 16-byte aligned
|
||||
;
|
||||
and esp, 0fffffff0h
|
||||
sub esp, 12
|
||||
|
||||
;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
|
||||
push eax
|
||||
push ecx
|
||||
push edx
|
||||
push ebx
|
||||
lea ecx, [ebp + 6 * 4]
|
||||
push ecx ; ESP
|
||||
push dword ptr [ebp] ; EBP
|
||||
push esi
|
||||
push edi
|
||||
|
||||
;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
|
||||
mov eax, ss
|
||||
push eax
|
||||
movzx eax, word ptr [ebp + 4 * 4]
|
||||
push eax
|
||||
mov eax, ds
|
||||
push eax
|
||||
mov eax, es
|
||||
push eax
|
||||
mov eax, fs
|
||||
push eax
|
||||
mov eax, gs
|
||||
push eax
|
||||
|
||||
;; UINT32 Eip;
|
||||
mov eax, [ebp + 3 * 4]
|
||||
push eax
|
||||
|
||||
;; UINT32 Gdtr[2], Idtr[2];
|
||||
sub esp, 8
|
||||
sidt [esp]
|
||||
mov eax, [esp + 2]
|
||||
xchg eax, [esp]
|
||||
and eax, 0FFFFh
|
||||
mov [esp+4], eax
|
||||
|
||||
sub esp, 8
|
||||
sgdt [esp]
|
||||
mov eax, [esp + 2]
|
||||
xchg eax, [esp]
|
||||
and eax, 0FFFFh
|
||||
mov [esp+4], eax
|
||||
|
||||
;; UINT32 Ldtr, Tr;
|
||||
xor eax, eax
|
||||
str ax
|
||||
push eax
|
||||
sldt ax
|
||||
push eax
|
||||
|
||||
;; UINT32 EFlags;
|
||||
mov eax, [ebp + 5 * 4]
|
||||
push eax
|
||||
|
||||
;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
|
||||
mov eax, cr4
|
||||
or eax, 208h
|
||||
mov cr4, eax
|
||||
push eax
|
||||
mov eax, cr3
|
||||
push eax
|
||||
mov eax, cr2
|
||||
push eax
|
||||
xor eax, eax
|
||||
push eax
|
||||
mov eax, cr0
|
||||
push eax
|
||||
|
||||
;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
|
||||
mov eax, dr7
|
||||
push eax
|
||||
;; clear Dr7 while executing debugger itself
|
||||
xor eax, eax
|
||||
mov dr7, eax
|
||||
|
||||
mov eax, dr6
|
||||
push eax
|
||||
;; insure all status bits in dr6 are clear...
|
||||
xor eax, eax
|
||||
mov dr6, eax
|
||||
|
||||
mov eax, dr3
|
||||
push eax
|
||||
mov eax, dr2
|
||||
push eax
|
||||
mov eax, dr1
|
||||
push eax
|
||||
mov eax, dr0
|
||||
push eax
|
||||
|
||||
;; FX_SAVE_STATE_IA32 FxSaveState;
|
||||
sub esp, 512
|
||||
mov edi, esp
|
||||
db 0fh, 0aeh, 07h ;fxsave [edi]
|
||||
|
||||
;; UINT32 ExceptionData;
|
||||
push dword ptr [ebp + 2 * 4]
|
||||
|
||||
;; call into exception handler
|
||||
mov eax, ExternalVectorTablePtr ; get the interrupt vectors base
|
||||
or eax, eax ; NULL?
|
||||
jz nullExternalExceptionHandler
|
||||
|
||||
mov ecx, [ebp + 4]
|
||||
mov eax, [eax + ecx * 4]
|
||||
or eax, eax ; NULL?
|
||||
jz nullExternalExceptionHandler
|
||||
|
||||
;; Prepare parameter and call
|
||||
mov edx, esp
|
||||
push edx
|
||||
mov edx, dword ptr [ebp + 1 * 4]
|
||||
push edx
|
||||
|
||||
;
|
||||
; Call External Exception Handler
|
||||
;
|
||||
call eax
|
||||
add esp, 8
|
||||
|
||||
nullExternalExceptionHandler:
|
||||
|
||||
cli
|
||||
;; UINT32 ExceptionData;
|
||||
add esp, 4
|
||||
|
||||
;; FX_SAVE_STATE_IA32 FxSaveState;
|
||||
mov esi, esp
|
||||
db 0fh, 0aeh, 0eh ; fxrstor [esi]
|
||||
add esp, 512
|
||||
|
||||
;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
|
||||
pop eax
|
||||
mov dr0, eax
|
||||
pop eax
|
||||
mov dr1, eax
|
||||
pop eax
|
||||
mov dr2, eax
|
||||
pop eax
|
||||
mov dr3, eax
|
||||
;; skip restore of dr6. We cleared dr6 during the context save.
|
||||
add esp, 4
|
||||
pop eax
|
||||
mov dr7, eax
|
||||
|
||||
;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
|
||||
pop eax
|
||||
mov cr0, eax
|
||||
add esp, 4 ; not for Cr1
|
||||
pop eax
|
||||
mov cr2, eax
|
||||
pop eax
|
||||
mov cr3, eax
|
||||
pop eax
|
||||
mov cr4, eax
|
||||
|
||||
;; UINT32 EFlags;
|
||||
pop dword ptr [ebp + 5 * 4]
|
||||
|
||||
;; UINT32 Ldtr, Tr;
|
||||
;; UINT32 Gdtr[2], Idtr[2];
|
||||
;; Best not let anyone mess with these particular registers...
|
||||
add esp, 24
|
||||
|
||||
;; UINT32 Eip;
|
||||
pop dword ptr [ebp + 3 * 4]
|
||||
|
||||
;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
|
||||
;; NOTE - modified segment registers could hang the debugger... We
|
||||
;; could attempt to insulate ourselves against this possibility,
|
||||
;; but that poses risks as well.
|
||||
;;
|
||||
pop gs
|
||||
pop fs
|
||||
pop es
|
||||
pop ds
|
||||
pop dword ptr [ebp + 4 * 4]
|
||||
pop ss
|
||||
|
||||
;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
|
||||
pop edi
|
||||
pop esi
|
||||
add esp, 4 ; not for ebp
|
||||
add esp, 4 ; not for esp
|
||||
pop ebx
|
||||
pop edx
|
||||
pop ecx
|
||||
pop eax
|
||||
|
||||
mov esp, ebp
|
||||
pop ebp
|
||||
add esp, 8
|
||||
iretd
|
||||
|
||||
CommonInterruptEntry ENDP
|
||||
|
||||
END
|
||||
|
|
@ -0,0 +1,66 @@
|
|||
#------------------------------------------------------------------------------
|
||||
#
|
||||
# Copyright (c) 2006 - 2009, Intel Corporation
|
||||
# All rights reserved. This program and the accompanying materials
|
||||
# are licensed and made available under the terms and conditions of the BSD License
|
||||
# which accompanies this distribution. The full text of the license may be found at
|
||||
# http://opensource.org/licenses/bsd-license.php
|
||||
#
|
||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
#
|
||||
# Module Name:
|
||||
#
|
||||
# IvtAsm.S
|
||||
#
|
||||
# Abstract:
|
||||
#
|
||||
# Interrupt Vector Table
|
||||
#
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
#
|
||||
# Interrupt Vector Table
|
||||
#
|
||||
|
||||
.macro SingleIdtVectorMacro vectorNum
|
||||
.intel_syntax
|
||||
call ASM_PFX(CommonInterruptEntry)
|
||||
.short \vectorNum
|
||||
nop
|
||||
.endm
|
||||
|
||||
.macro EightIdtVectors firstVectorNum
|
||||
SingleIdtVectorMacro \firstVectorNum
|
||||
SingleIdtVectorMacro "(\firstVectorNum+1)"
|
||||
SingleIdtVectorMacro "(\firstVectorNum+2)"
|
||||
SingleIdtVectorMacro "(\firstVectorNum+3)"
|
||||
SingleIdtVectorMacro "(\firstVectorNum+4)"
|
||||
SingleIdtVectorMacro "(\firstVectorNum+5)"
|
||||
SingleIdtVectorMacro "(\firstVectorNum+6)"
|
||||
SingleIdtVectorMacro "(\firstVectorNum+7)"
|
||||
.endm
|
||||
|
||||
.macro SixtyFourIdtVectors firstVectorNum
|
||||
EightIdtVectors \firstVectorNum
|
||||
EightIdtVectors "(\firstVectorNum+0x08)"
|
||||
EightIdtVectors "(\firstVectorNum+0x10)"
|
||||
EightIdtVectors "(\firstVectorNum+0x18)"
|
||||
EightIdtVectors "(\firstVectorNum+0x20)"
|
||||
EightIdtVectors "(\firstVectorNum+0x28)"
|
||||
EightIdtVectors "(\firstVectorNum+0x30)"
|
||||
EightIdtVectors "(\firstVectorNum+0x38)"
|
||||
.endm
|
||||
|
||||
ASM_GLOBAL ASM_PFX(AsmIdtVector00)
|
||||
.align 8
|
||||
ASM_PFX(AsmIdtVector00):
|
||||
SixtyFourIdtVectors 0x00
|
||||
SixtyFourIdtVectors 0x40
|
||||
SixtyFourIdtVectors 0x80
|
||||
SixtyFourIdtVectors 0xC0
|
||||
ASM_GLOBAL ASM_PFX(AsmCommonIdtEnd)
|
||||
ASM_PFX(AsmCommonIdtEnd):
|
||||
.byte 0
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,51 @@
|
|||
TITLE IvtAsm.asm:
|
||||
;------------------------------------------------------------------------------
|
||||
;*
|
||||
;* Copyright 2008 - 2009, Intel Corporation
|
||||
;* All rights reserved. This program and the accompanying materials
|
||||
;* are licensed and made available under the terms and conditions of the BSD License
|
||||
;* which accompanies this distribution. The full text of the license may be found at
|
||||
;* http://opensource.org/licenses/bsd-license.php
|
||||
;*
|
||||
;* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
;* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
;*
|
||||
;* IvtAsm.asm
|
||||
;*
|
||||
;* Abstract:
|
||||
;*
|
||||
;------------------------------------------------------------------------------
|
||||
|
||||
#include <Base.h>
|
||||
|
||||
#ifdef MDE_CPU_IA32
|
||||
.686
|
||||
.model flat,C
|
||||
#endif
|
||||
.code
|
||||
|
||||
;------------------------------------------------------------------------------
|
||||
; Generic IDT Vector Handlers for the Host. They are all the same so they
|
||||
; will compress really well.
|
||||
;
|
||||
; By knowing the return address for Vector 00 you can can calculate the
|
||||
; vector number by looking at the call CommonInterruptEntry return address.
|
||||
; (return address - (AsmIdtVector00 + 5))/8 == IDT index
|
||||
;
|
||||
;------------------------------------------------------------------------------
|
||||
|
||||
EXTRN CommonInterruptEntry:PROC
|
||||
|
||||
ALIGN 8
|
||||
|
||||
PUBLIC AsmIdtVector00
|
||||
|
||||
AsmIdtVector00 LABEL BYTE
|
||||
REPEAT 256
|
||||
call CommonInterruptEntry
|
||||
dw ($ - AsmIdtVector00 - 5) / 8 ; vector number
|
||||
nop
|
||||
ENDM
|
||||
|
||||
END
|
||||
|
||||
|
|
@ -0,0 +1,363 @@
|
|||
# TITLE CpuAsm.asm:
|
||||
|
||||
#------------------------------------------------------------------------------
|
||||
#*
|
||||
#* Copyright 2008 - 2009, Intel Corporation
|
||||
#* All rights reserved. This program and the accompanying materials
|
||||
#* are licensed and made available under the terms and conditions of the BSD License
|
||||
#* which accompanies this distribution. The full text of the license may be found at
|
||||
#* http://opensource.org/licenses/bsd-license.php
|
||||
#*
|
||||
#* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
#* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
#*
|
||||
#* CpuAsm.S
|
||||
#*
|
||||
#* Abstract:
|
||||
#*
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
|
||||
#text SEGMENT
|
||||
|
||||
|
||||
#EXTRN ASM_PFX(mErrorCodeFlag):DWORD # Error code flags for exceptions
|
||||
|
||||
|
||||
#
|
||||
# point to the external interrupt vector table
|
||||
#
|
||||
ExternalVectorTablePtr:
|
||||
.byte 0, 0, 0, 0, 0, 0, 0, 0
|
||||
|
||||
.intel_syntax
|
||||
ASM_GLOBAL ASM_PFX(InitializeExternalVectorTablePtr)
|
||||
ASM_PFX(InitializeExternalVectorTablePtr):
|
||||
lea %rax, [%rip+ExternalVectorTablePtr] # save vector number
|
||||
mov [%rax], %rcx
|
||||
ret
|
||||
|
||||
|
||||
#------------------------------------------------------------------------------
|
||||
# VOID
|
||||
# SetCodeSelector (
|
||||
# UINT16 Selector
|
||||
# );
|
||||
#------------------------------------------------------------------------------
|
||||
.intel_syntax
|
||||
ASM_GLOBAL ASM_PFX(SetCodeSelector)
|
||||
ASM_PFX(SetCodeSelector):
|
||||
sub %rsp, 0x10
|
||||
lea %rax, [%rip+setCodeSelectorLongJump]
|
||||
mov [%rsp], %rax
|
||||
mov [%rsp+4], %cx
|
||||
jmp fword ptr [%rsp]
|
||||
setCodeSelectorLongJump:
|
||||
add %rsp, 0x10
|
||||
ret
|
||||
|
||||
#------------------------------------------------------------------------------
|
||||
# VOID
|
||||
# SetDataSelectors (
|
||||
# UINT16 Selector
|
||||
# );
|
||||
#------------------------------------------------------------------------------
|
||||
.intel_syntax
|
||||
ASM_GLOBAL ASM_PFX(SetDataSelectors)
|
||||
ASM_PFX(SetDataSelectors):
|
||||
mov %ss, %cx
|
||||
mov %ds, %cx
|
||||
mov %es, %cx
|
||||
mov %fs, %cx
|
||||
mov %gs, %cx
|
||||
ret
|
||||
|
||||
#---------------------------------------;
|
||||
# CommonInterruptEntry ;
|
||||
#---------------------------------------;
|
||||
# The follow algorithm is used for the common interrupt routine.
|
||||
|
||||
.intel_syntax
|
||||
ASM_GLOBAL ASM_PFX(CommonInterruptEntry)
|
||||
ASM_PFX(CommonInterruptEntry):
|
||||
cli
|
||||
#
|
||||
# All interrupt handlers are invoked through interrupt gates, so
|
||||
# IF flag automatically cleared at the entry point
|
||||
#
|
||||
#
|
||||
# Calculate vector number
|
||||
#
|
||||
xchg %rcx, [%rsp] # get the return address of call, actually, it is the address of vector number.
|
||||
movzx %ecx, word ptr [%rcx]
|
||||
cmp %ecx, 32 # Intel reserved vector for exceptions?
|
||||
jae NoErrorCode
|
||||
push %rax
|
||||
lea %rax, [%rip+ASM_PFX(mErrorCodeFlag)]
|
||||
bt dword ptr [%rax], %ecx
|
||||
pop %rax
|
||||
jc CommonInterruptEntry_al_0000
|
||||
|
||||
NoErrorCode:
|
||||
|
||||
#
|
||||
# Push a dummy error code on the stack
|
||||
# to maintain coherent stack map
|
||||
#
|
||||
push [%rsp]
|
||||
mov qword ptr [%rsp + 8], 0
|
||||
CommonInterruptEntry_al_0000:
|
||||
push %rbp
|
||||
mov %rbp, %rsp
|
||||
|
||||
#
|
||||
# Stack:
|
||||
# +---------------------+ <-- 16-byte aligned ensured by processor
|
||||
# + Old SS +
|
||||
# +---------------------+
|
||||
# + Old RSP +
|
||||
# +---------------------+
|
||||
# + RFlags +
|
||||
# +---------------------+
|
||||
# + CS +
|
||||
# +---------------------+
|
||||
# + RIP +
|
||||
# +---------------------+
|
||||
# + Error Code +
|
||||
# +---------------------+
|
||||
# + RCX / Vector Number +
|
||||
# +---------------------+
|
||||
# + RBP +
|
||||
# +---------------------+ <-- RBP, 16-byte aligned
|
||||
#
|
||||
|
||||
|
||||
#
|
||||
# Since here the stack pointer is 16-byte aligned, so
|
||||
# EFI_FX_SAVE_STATE_X64 of EFI_SYSTEM_CONTEXT_x64
|
||||
# is 16-byte aligned
|
||||
#
|
||||
|
||||
#; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
|
||||
#; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
|
||||
push %r15
|
||||
push %r14
|
||||
push %r13
|
||||
push %r12
|
||||
push %r11
|
||||
push %r10
|
||||
push %r9
|
||||
push %r8
|
||||
push %rax
|
||||
push qword ptr [%rbp + 8] # RCX
|
||||
push %rdx
|
||||
push %rbx
|
||||
push qword ptr [%rbp + 48] # RSP
|
||||
push qword ptr [%rbp] # RBP
|
||||
push %rsi
|
||||
push %rdi
|
||||
|
||||
#; UINT64 Gs, Fs, Es, Ds, Cs, Ss; insure high 16 bits of each is zero
|
||||
movzx %rax, word ptr [%rbp + 56]
|
||||
push %rax # for ss
|
||||
movzx %rax, word ptr [%rbp + 32]
|
||||
push %rax # for cs
|
||||
mov %rax, %ds
|
||||
push %rax
|
||||
mov %rax, %es
|
||||
push %rax
|
||||
mov %rax, %fs
|
||||
push %rax
|
||||
mov %rax, %gs
|
||||
push %rax
|
||||
|
||||
mov [%rbp + 8], %rcx # save vector number
|
||||
|
||||
#; UINT64 Rip;
|
||||
push qword ptr [%rbp + 24]
|
||||
|
||||
#; UINT64 Gdtr[2], Idtr[2];
|
||||
xor %rax, %rax
|
||||
push %rax
|
||||
push %rax
|
||||
sidt [%rsp]
|
||||
xchg %rax, [%rsp + 2]
|
||||
xchg %rax, [%rsp]
|
||||
xchg %rax, [%rsp + 8]
|
||||
|
||||
xor %rax, %rax
|
||||
push %rax
|
||||
push %rax
|
||||
sgdt [%rsp]
|
||||
xchg %rax, [%rsp + 2]
|
||||
xchg %rax, [%rsp]
|
||||
xchg %rax, [%rsp + 8]
|
||||
|
||||
#; UINT64 Ldtr, Tr;
|
||||
xor %rax, %rax
|
||||
str %ax
|
||||
push %rax
|
||||
sldt %ax
|
||||
push %rax
|
||||
|
||||
#; UINT64 RFlags;
|
||||
push qword ptr [%rbp + 40]
|
||||
|
||||
#; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
|
||||
mov %rax, %cr8
|
||||
push %rax
|
||||
mov %rax, %cr4
|
||||
or %rax, 0x208
|
||||
mov %cr4, %rax
|
||||
push %rax
|
||||
mov %rax, %cr3
|
||||
push %rax
|
||||
mov %rax, %cr2
|
||||
push %rax
|
||||
xor %rax, %rax
|
||||
push %rax
|
||||
mov %rax, %cr0
|
||||
push %rax
|
||||
|
||||
#; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
|
||||
mov %rax, %dr7
|
||||
push %rax
|
||||
#; clear Dr7 while executing debugger itself
|
||||
xor %rax, %rax
|
||||
mov %dr7, %rax
|
||||
|
||||
mov %rax, %dr6
|
||||
push %rax
|
||||
#; insure all status bits in dr6 are clear...
|
||||
xor %rax, %rax
|
||||
mov %dr6, %rax
|
||||
|
||||
mov %rax, %dr3
|
||||
push %rax
|
||||
mov %rax, %dr2
|
||||
push %rax
|
||||
mov %rax, %dr1
|
||||
push %rax
|
||||
mov %rax, %dr0
|
||||
push %rax
|
||||
|
||||
#; FX_SAVE_STATE_X64 FxSaveState;
|
||||
sub %rsp, 512
|
||||
mov %rdi, %rsp
|
||||
.byte 0x0f, 0x0ae, 0x07 #fxsave [rdi]
|
||||
|
||||
#; UINT32 ExceptionData;
|
||||
push qword ptr [%rbp + 16]
|
||||
|
||||
#; call into exception handler
|
||||
mov %rcx, [%rbp + 8]
|
||||
lea %rax, [%rip+ExternalVectorTablePtr]
|
||||
mov %eax, [%eax]
|
||||
mov %rax, [%rax + %rcx * 8]
|
||||
or %rax, %rax # NULL?
|
||||
|
||||
je nonNullValue#
|
||||
|
||||
#; Prepare parameter and call
|
||||
# mov rcx, [rbp + 8]
|
||||
mov %rdx, %rsp
|
||||
#
|
||||
# Per X64 calling convention, allocate maximum parameter stack space
|
||||
# and make sure RSP is 16-byte aligned
|
||||
#
|
||||
sub %rsp, 4 * 8 + 8
|
||||
call %rax
|
||||
add %rsp, 4 * 8 + 8
|
||||
|
||||
nonNullValue:
|
||||
cli
|
||||
#; UINT64 ExceptionData;
|
||||
add %rsp, 8
|
||||
|
||||
#; FX_SAVE_STATE_X64 FxSaveState;
|
||||
|
||||
mov %rsi, %rsp
|
||||
.byte 0x0f, 0x0ae, 0x0E # fxrstor [rsi]
|
||||
add %rsp, 512
|
||||
|
||||
#; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
|
||||
pop %rax
|
||||
mov %dr0, %rax
|
||||
pop %rax
|
||||
mov %dr1, %rax
|
||||
pop %rax
|
||||
mov %dr2, %rax
|
||||
pop %rax
|
||||
mov %dr3, %rax
|
||||
#; skip restore of dr6. We cleared dr6 during the context save.
|
||||
add %rsp, 8
|
||||
pop %rax
|
||||
mov %dr7, %rax
|
||||
|
||||
#; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
|
||||
pop %rax
|
||||
mov %cr0, %rax
|
||||
add %rsp, 8 # not for Cr1
|
||||
pop %rax
|
||||
mov %cr2, %rax
|
||||
pop %rax
|
||||
mov %cr3, %rax
|
||||
pop %rax
|
||||
mov %cr4, %rax
|
||||
pop %rax
|
||||
mov %cr8, %rax
|
||||
|
||||
#; UINT64 RFlags;
|
||||
pop qword ptr [%rbp + 40]
|
||||
|
||||
#; UINT64 Ldtr, Tr;
|
||||
#; UINT64 Gdtr[2], Idtr[2];
|
||||
#; Best not let anyone mess with these particular registers...
|
||||
add %rsp, 48
|
||||
|
||||
#; UINT64 Rip;
|
||||
pop qword ptr [%rbp + 24]
|
||||
|
||||
#; UINT64 Gs, Fs, Es, Ds, Cs, Ss;
|
||||
pop %rax
|
||||
# mov gs, rax ; not for gs
|
||||
pop %rax
|
||||
# mov fs, rax ; not for fs
|
||||
# (X64 will not use fs and gs, so we do not restore it)
|
||||
pop %rax
|
||||
mov %es, %rax
|
||||
pop %rax
|
||||
mov %ds, %rax
|
||||
pop qword ptr [%rbp + 32] # for cs
|
||||
pop qword ptr [%rbp + 56] # for ss
|
||||
|
||||
#; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
|
||||
#; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
|
||||
pop %rdi
|
||||
pop %rsi
|
||||
add %rsp, 8 # not for rbp
|
||||
pop qword ptr [%rbp + 48] # for rsp
|
||||
pop %rbx
|
||||
pop %rdx
|
||||
pop %rcx
|
||||
pop %rax
|
||||
pop %r8
|
||||
pop %r9
|
||||
pop %r10
|
||||
pop %r11
|
||||
pop %r12
|
||||
pop %r13
|
||||
pop %r14
|
||||
pop %r15
|
||||
|
||||
mov %rsp, %rbp
|
||||
pop %rbp
|
||||
add %rsp, 16
|
||||
iretq
|
||||
|
||||
|
||||
#text ENDS
|
||||
|
||||
#END
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,345 @@
|
|||
TITLE CpuAsm.asm:
|
||||
;------------------------------------------------------------------------------
|
||||
;*
|
||||
;* Copyright 2008 - 2009, Intel Corporation
|
||||
;* All rights reserved. This program and the accompanying materials
|
||||
;* are licensed and made available under the terms and conditions of the BSD License
|
||||
;* which accompanies this distribution. The full text of the license may be found at
|
||||
;* http://opensource.org/licenses/bsd-license.php
|
||||
;*
|
||||
;* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
;* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
;*
|
||||
;* CpuAsm.asm
|
||||
;*
|
||||
;* Abstract:
|
||||
;*
|
||||
;------------------------------------------------------------------------------
|
||||
|
||||
.code
|
||||
|
||||
EXTRN mErrorCodeFlag:DWORD ; Error code flags for exceptions
|
||||
|
||||
;
|
||||
; point to the external interrupt vector table
|
||||
;
|
||||
ExternalVectorTablePtr QWORD 0
|
||||
|
||||
InitializeExternalVectorTablePtr PROC PUBLIC
|
||||
mov ExternalVectorTablePtr, rcx
|
||||
ret
|
||||
InitializeExternalVectorTablePtr ENDP
|
||||
|
||||
;------------------------------------------------------------------------------
|
||||
; VOID
|
||||
; SetCodeSelector (
|
||||
; UINT16 Selector
|
||||
; );
|
||||
;------------------------------------------------------------------------------
|
||||
SetCodeSelector PROC PUBLIC
|
||||
sub rsp, 0x10
|
||||
lea rax, setCodeSelectorLongJump
|
||||
mov [rsp], rax
|
||||
mov [rsp+4], cx
|
||||
jmp fword ptr [rsp]
|
||||
setCodeSelectorLongJump:
|
||||
add rsp, 0x10
|
||||
ret
|
||||
SetCodeSelector ENDP
|
||||
|
||||
;------------------------------------------------------------------------------
|
||||
; VOID
|
||||
; SetDataSelectors (
|
||||
; UINT16 Selector
|
||||
; );
|
||||
;------------------------------------------------------------------------------
|
||||
SetDataSelectors PROC PUBLIC
|
||||
mov ss, cx
|
||||
mov ds, cx
|
||||
mov es, cx
|
||||
mov fs, cx
|
||||
mov gs, cx
|
||||
ret
|
||||
SetDataSelectors ENDP
|
||||
|
||||
;---------------------------------------;
|
||||
; CommonInterruptEntry ;
|
||||
;---------------------------------------;
|
||||
; The follow algorithm is used for the common interrupt routine.
|
||||
|
||||
CommonInterruptEntry PROC PUBLIC
|
||||
cli
|
||||
;
|
||||
; All interrupt handlers are invoked through interrupt gates, so
|
||||
; IF flag automatically cleared at the entry point
|
||||
;
|
||||
;
|
||||
; Calculate vector number
|
||||
;
|
||||
xchg rcx, [rsp] ; get the return address of call, actually, it is the address of vector number.
|
||||
movzx ecx, word ptr [rcx]
|
||||
cmp ecx, 32 ; Intel reserved vector for exceptions?
|
||||
jae NoErrorCode
|
||||
bt mErrorCodeFlag, ecx
|
||||
jc @F
|
||||
|
||||
NoErrorCode:
|
||||
|
||||
;
|
||||
; Push a dummy error code on the stack
|
||||
; to maintain coherent stack map
|
||||
;
|
||||
push [rsp]
|
||||
mov qword ptr [rsp + 8], 0
|
||||
@@:
|
||||
push rbp
|
||||
mov rbp, rsp
|
||||
|
||||
;
|
||||
; Stack:
|
||||
; +---------------------+ <-- 16-byte aligned ensured by processor
|
||||
; + Old SS +
|
||||
; +---------------------+
|
||||
; + Old RSP +
|
||||
; +---------------------+
|
||||
; + RFlags +
|
||||
; +---------------------+
|
||||
; + CS +
|
||||
; +---------------------+
|
||||
; + RIP +
|
||||
; +---------------------+
|
||||
; + Error Code +
|
||||
; +---------------------+
|
||||
; + RCX / Vector Number +
|
||||
; +---------------------+
|
||||
; + RBP +
|
||||
; +---------------------+ <-- RBP, 16-byte aligned
|
||||
;
|
||||
|
||||
|
||||
;
|
||||
; Since here the stack pointer is 16-byte aligned, so
|
||||
; EFI_FX_SAVE_STATE_X64 of EFI_SYSTEM_CONTEXT_x64
|
||||
; is 16-byte aligned
|
||||
;
|
||||
|
||||
;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
|
||||
;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
|
||||
push r15
|
||||
push r14
|
||||
push r13
|
||||
push r12
|
||||
push r11
|
||||
push r10
|
||||
push r9
|
||||
push r8
|
||||
push rax
|
||||
push qword ptr [rbp + 8] ; RCX
|
||||
push rdx
|
||||
push rbx
|
||||
push qword ptr [rbp + 48] ; RSP
|
||||
push qword ptr [rbp] ; RBP
|
||||
push rsi
|
||||
push rdi
|
||||
|
||||
;; UINT64 Gs, Fs, Es, Ds, Cs, Ss; insure high 16 bits of each is zero
|
||||
movzx rax, word ptr [rbp + 56]
|
||||
push rax ; for ss
|
||||
movzx rax, word ptr [rbp + 32]
|
||||
push rax ; for cs
|
||||
mov rax, ds
|
||||
push rax
|
||||
mov rax, es
|
||||
push rax
|
||||
mov rax, fs
|
||||
push rax
|
||||
mov rax, gs
|
||||
push rax
|
||||
|
||||
mov [rbp + 8], rcx ; save vector number
|
||||
|
||||
;; UINT64 Rip;
|
||||
push qword ptr [rbp + 24]
|
||||
|
||||
;; UINT64 Gdtr[2], Idtr[2];
|
||||
xor rax, rax
|
||||
push rax
|
||||
push rax
|
||||
sidt [rsp]
|
||||
xchg rax, [rsp + 2]
|
||||
xchg rax, [rsp]
|
||||
xchg rax, [rsp + 8]
|
||||
|
||||
xor rax, rax
|
||||
push rax
|
||||
push rax
|
||||
sgdt [rsp]
|
||||
xchg rax, [rsp + 2]
|
||||
xchg rax, [rsp]
|
||||
xchg rax, [rsp + 8]
|
||||
|
||||
;; UINT64 Ldtr, Tr;
|
||||
xor rax, rax
|
||||
str ax
|
||||
push rax
|
||||
sldt ax
|
||||
push rax
|
||||
|
||||
;; UINT64 RFlags;
|
||||
push qword ptr [rbp + 40]
|
||||
|
||||
;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
|
||||
mov rax, cr8
|
||||
push rax
|
||||
mov rax, cr4
|
||||
or rax, 208h
|
||||
mov cr4, rax
|
||||
push rax
|
||||
mov rax, cr3
|
||||
push rax
|
||||
mov rax, cr2
|
||||
push rax
|
||||
xor rax, rax
|
||||
push rax
|
||||
mov rax, cr0
|
||||
push rax
|
||||
|
||||
;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
|
||||
mov rax, dr7
|
||||
push rax
|
||||
;; clear Dr7 while executing debugger itself
|
||||
xor rax, rax
|
||||
mov dr7, rax
|
||||
|
||||
mov rax, dr6
|
||||
push rax
|
||||
;; insure all status bits in dr6 are clear...
|
||||
xor rax, rax
|
||||
mov dr6, rax
|
||||
|
||||
mov rax, dr3
|
||||
push rax
|
||||
mov rax, dr2
|
||||
push rax
|
||||
mov rax, dr1
|
||||
push rax
|
||||
mov rax, dr0
|
||||
push rax
|
||||
|
||||
;; FX_SAVE_STATE_X64 FxSaveState;
|
||||
sub rsp, 512
|
||||
mov rdi, rsp
|
||||
db 0fh, 0aeh, 07h ;fxsave [rdi]
|
||||
|
||||
;; UINT32 ExceptionData;
|
||||
push qword ptr [rbp + 16]
|
||||
|
||||
;; call into exception handler
|
||||
mov rcx, [rbp + 8]
|
||||
mov rax, ExternalVectorTablePtr ; get the interrupt vectors base
|
||||
mov rax, [rax + rcx * 8]
|
||||
or rax, rax ; NULL?
|
||||
|
||||
je nonNullValue;
|
||||
|
||||
;; Prepare parameter and call
|
||||
; mov rcx, [rbp + 8]
|
||||
mov rdx, rsp
|
||||
;
|
||||
; Per X64 calling convention, allocate maximum parameter stack space
|
||||
; and make sure RSP is 16-byte aligned
|
||||
;
|
||||
sub rsp, 4 * 8 + 8
|
||||
call rax
|
||||
add rsp, 4 * 8 + 8
|
||||
|
||||
nonNullValue:
|
||||
cli
|
||||
;; UINT64 ExceptionData;
|
||||
add rsp, 8
|
||||
|
||||
;; FX_SAVE_STATE_X64 FxSaveState;
|
||||
|
||||
mov rsi, rsp
|
||||
db 0fh, 0aeh, 0Eh ; fxrstor [rsi]
|
||||
add rsp, 512
|
||||
|
||||
;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
|
||||
pop rax
|
||||
mov dr0, rax
|
||||
pop rax
|
||||
mov dr1, rax
|
||||
pop rax
|
||||
mov dr2, rax
|
||||
pop rax
|
||||
mov dr3, rax
|
||||
;; skip restore of dr6. We cleared dr6 during the context save.
|
||||
add rsp, 8
|
||||
pop rax
|
||||
mov dr7, rax
|
||||
|
||||
;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
|
||||
pop rax
|
||||
mov cr0, rax
|
||||
add rsp, 8 ; not for Cr1
|
||||
pop rax
|
||||
mov cr2, rax
|
||||
pop rax
|
||||
mov cr3, rax
|
||||
pop rax
|
||||
mov cr4, rax
|
||||
pop rax
|
||||
mov cr8, rax
|
||||
|
||||
;; UINT64 RFlags;
|
||||
pop qword ptr [rbp + 40]
|
||||
|
||||
;; UINT64 Ldtr, Tr;
|
||||
;; UINT64 Gdtr[2], Idtr[2];
|
||||
;; Best not let anyone mess with these particular registers...
|
||||
add rsp, 48
|
||||
|
||||
;; UINT64 Rip;
|
||||
pop qword ptr [rbp + 24]
|
||||
|
||||
;; UINT64 Gs, Fs, Es, Ds, Cs, Ss;
|
||||
pop rax
|
||||
; mov gs, rax ; not for gs
|
||||
pop rax
|
||||
; mov fs, rax ; not for fs
|
||||
; (X64 will not use fs and gs, so we do not restore it)
|
||||
pop rax
|
||||
mov es, rax
|
||||
pop rax
|
||||
mov ds, rax
|
||||
pop qword ptr [rbp + 32] ; for cs
|
||||
pop qword ptr [rbp + 56] ; for ss
|
||||
|
||||
;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
|
||||
;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
|
||||
pop rdi
|
||||
pop rsi
|
||||
add rsp, 8 ; not for rbp
|
||||
pop qword ptr [rbp + 48] ; for rsp
|
||||
pop rbx
|
||||
pop rdx
|
||||
pop rcx
|
||||
pop rax
|
||||
pop r8
|
||||
pop r9
|
||||
pop r10
|
||||
pop r11
|
||||
pop r12
|
||||
pop r13
|
||||
pop r14
|
||||
pop r15
|
||||
|
||||
mov rsp, rbp
|
||||
pop rbp
|
||||
add rsp, 16
|
||||
iretq
|
||||
|
||||
CommonInterruptEntry ENDP
|
||||
|
||||
END
|
||||
|
||||
Loading…
Reference in New Issue