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Add CPU DXE driver for IA32 & X64 processor architectures. 

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@8395 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
jljusten 2009-05-27 21:09:47 +00:00
parent e50466da24
commit a47463f283
10 changed files with 3119 additions and 0 deletions
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1108
UefiCpuPkg/CpuDxe/CpuDxe.c Normal file
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140
UefiCpuPkg/CpuDxe/CpuDxe.h Normal file
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/** @file
CPU DXE Module.
Copyright (c) 2008 - 2009, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _CPU_DXE_H
#define _CPU_DXE_H
#include <PiDxe.h>
#include <Protocol/Cpu.h>
#include <Library/UefiDriverEntryPoint.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/DxeServicesTableLib.h>
#include <Library/BaseLib.h>
#include <Library/CpuLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/DebugLib.h>
#include <Library/MtrrLib.h>
//
//
//
#define INTERRUPT_VECTOR_NUMBER 256
#define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC | \
EFI_MEMORY_WC | \
EFI_MEMORY_WT | \
EFI_MEMORY_WB | \
EFI_MEMORY_UCE \
)
//
// Function declarations
//
EFI_STATUS
EFIAPI
CpuFlushCpuDataCache (
IN EFI_CPU_ARCH_PROTOCOL *This,
IN EFI_PHYSICAL_ADDRESS Start,
IN UINT64 Length,
IN EFI_CPU_FLUSH_TYPE FlushType
);
EFI_STATUS
EFIAPI
CpuEnableInterrupt (
IN EFI_CPU_ARCH_PROTOCOL *This
);
EFI_STATUS
EFIAPI
CpuDisableInterrupt (
IN EFI_CPU_ARCH_PROTOCOL *This
);
EFI_STATUS
EFIAPI
CpuGetInterruptState (
IN EFI_CPU_ARCH_PROTOCOL *This,
OUT BOOLEAN *State
);
EFI_STATUS
EFIAPI
CpuInit (
IN EFI_CPU_ARCH_PROTOCOL *This,
IN EFI_CPU_INIT_TYPE InitType
);
EFI_STATUS
EFIAPI
CpuRegisterInterruptHandler (
IN EFI_CPU_ARCH_PROTOCOL *This,
IN EFI_EXCEPTION_TYPE InterruptType,
IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
);
EFI_STATUS
EFIAPI
CpuGetTimerValue (
IN EFI_CPU_ARCH_PROTOCOL *This,
IN UINT32 TimerIndex,
OUT UINT64 *TimerValue,
OUT UINT64 *TimerPeriod OPTIONAL
);
EFI_STATUS
EFIAPI
CpuSetMemoryAttributes (
IN EFI_CPU_ARCH_PROTOCOL *This,
IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length,
IN UINT64 Attributes
);
VOID
EFIAPI
AsmIdtVector00 (
VOID
);
VOID
EFIAPI
InitializeExternalVectorTablePtr (
EFI_CPU_INTERRUPT_HANDLER *VectorTable
);
VOID
InitGlobalDescriptorTable (
VOID
);
VOID
EFIAPI
SetCodeSelector (
UINT16 Selector
);
VOID
EFIAPI
SetDataSelectors (
UINT16 Selector
);
#endif

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UefiCpuPkg/CpuDxe/CpuDxe.inf Normal file
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#/** @file
#
# Component description file for simple CPU driver
#
# Copyright (c) 2008 - 2009, Intel Corporation. <BR>
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = CpuDxe
FILE_GUID = 62D171CB-78CD-4480-8678-C6A2A797A8DE
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
EDK_RELEASE_VERSION = 0x00020000
EFI_SPECIFICATION_VERSION = 0x0002000A
ENTRY_POINT = InitializeCpu
[Packages]
OvmfPkg/OvmfPkg.dec
MdePkg/MdePkg.dec
UefiCpuPkg/UefiCpuPkg.dec
[LibraryClasses]
BaseLib
BaseMemoryLib
CpuLib
DebugLib
DxeServicesTableLib
MemoryAllocationLib
MtrrLib
UefiBootServicesTableLib
UefiDriverEntryPoint
[Sources]
CpuDxe.c
CpuDxe.h
CpuGdt.c
Ia32/IvtAsm.asm | MSFT
Ia32/IvtAsm.asm | INTEL
Ia32/IvtAsm.S | GCC
[Sources.IA32]
Ia32/CpuAsm.asm | MSFT
Ia32/CpuAsm.asm | INTEL
Ia32/CpuAsm.S | GCC
[Sources.X64]
X64/CpuAsm.asm | MSFT
X64/CpuAsm.asm | INTEL
X64/CpuAsm.S | GCC
[Protocols]
gEfiCpuArchProtocolGuid
[Depex]
TRUE

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UefiCpuPkg/CpuDxe/CpuGdt.c Executable file
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/** @file
C based implemention of IA32 interrupt handling only
requiring a minimal assembly interrupt entry point.
Copyright (c) 2006 - 2009, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "CpuDxe.h"
//
// Local structure definitions
//
#pragma pack (1)
//
// Global Descriptor Entry structures
//
typedef
struct _GDT_ENTRY {
UINT16 limit15_0;
UINT16 base15_0;
UINT8 base23_16;
UINT8 type;
UINT8 limit19_16_and_flags;
UINT8 base31_24;
} GDT_ENTRY;
typedef
struct _GDT_ENTRIES {
GDT_ENTRY Null;
GDT_ENTRY Linear;
GDT_ENTRY LinearCode;
GDT_ENTRY SysData;
GDT_ENTRY SysCode;
GDT_ENTRY LinearCode64;
GDT_ENTRY Spare4;
GDT_ENTRY Spare5;
} GDT_ENTRIES;
#define NULL_SEL OFFSET_OF (GDT_ENTRIES, Null)
#define LINEAR_SEL OFFSET_OF (GDT_ENTRIES, Linear)
#define LINEAR_CODE_SEL OFFSET_OF (GDT_ENTRIES, LinearCode)
#define SYS_DATA_SEL OFFSET_OF (GDT_ENTRIES, SysData)
#define SYS_CODE_SEL OFFSET_OF (GDT_ENTRIES, SysCode)
#define LINEAR_CODE64_SEL OFFSET_OF (GDT_ENTRIES, LinearCode64)
#define SPARE4_SEL OFFSET_OF (GDT_ENTRIES, Spare4)
#define SPARE5_SEL OFFSET_OF (GDT_ENTRIES, Spare5)
#if defined (MDE_CPU_IA32)
#define CPU_CODE_SEL LINEAR_CODE_SEL
#define CPU_DATA_SEL LINEAR_SEL
#elif defined (MDE_CPU_X64)
#define CPU_CODE_SEL LINEAR_CODE64_SEL
#define CPU_DATA_SEL LINEAR_SEL
#else
#error CPU type not supported for CPU GDT initialization!
#endif
//
// Global descriptor table (GDT) Template
//
STATIC GDT_ENTRIES GdtTemplate = {
//
// NULL_SEL
//
{
0x0, // limit 15:0
0x0, // base 15:0
0x0, // base 23:16
0x0, // type
0x0, // limit 19:16, flags
0x0, // base 31:24
},
//
// LINEAR_SEL
//
{
0x0FFFF, // limit 0xFFFFF
0x0, // base 0
0x0,
0x092, // present, ring 0, data, expand-up, writable
0x0CF, // page-granular, 32-bit
0x0,
},
//
// LINEAR_CODE_SEL
//
{
0x0FFFF, // limit 0xFFFFF
0x0, // base 0
0x0,
0x09A, // present, ring 0, data, expand-up, writable
0x0CF, // page-granular, 32-bit
0x0,
},
//
// SYS_DATA_SEL
//
{
0x0FFFF, // limit 0xFFFFF
0x0, // base 0
0x0,
0x092, // present, ring 0, data, expand-up, writable
0x0CF, // page-granular, 32-bit
0x0,
},
//
// SYS_CODE_SEL
//
{
0x0FFFF, // limit 0xFFFFF
0x0, // base 0
0x0,
0x09A, // present, ring 0, data, expand-up, writable
0x0CF, // page-granular, 32-bit
0x0,
},
//
// LINEAR_CODE64_SEL
//
{
0x0FFFF, // limit 0xFFFFF
0x0, // base 0
0x0,
0x09B, // present, ring 0, code, expand-up, writable
0x0AF, // LimitHigh (CS.L=1, CS.D=0)
0x0, // base (high)
},
//
// SPARE4_SEL
//
{
0x0, // limit 0
0x0, // base 0
0x0,
0x0, // present, ring 0, data, expand-up, writable
0x0, // page-granular, 32-bit
0x0,
},
//
// SPARE5_SEL
//
{
0x0, // limit 0
0x0, // base 0
0x0,
0x0, // present, ring 0, data, expand-up, writable
0x0, // page-granular, 32-bit
0x0,
},
};
/**
Initialize Global Descriptor Table
**/
VOID
InitGlobalDescriptorTable (
)
{
GDT_ENTRIES *gdt;
IA32_DESCRIPTOR gdtPtr;
//
// Allocate Runtime Data for the GDT
//
gdt = AllocateRuntimePool (sizeof (GdtTemplate) + 8);
ASSERT (gdt != NULL);
gdt = ALIGN_POINTER (gdt, 8);
//
// Initialize all GDT entries
//
CopyMem (gdt, &GdtTemplate, sizeof (GdtTemplate));
//
// Write GDT register
//
gdtPtr.Base = (UINT32)(UINTN)(VOID*) gdt;
gdtPtr.Limit = sizeof (GdtTemplate) - 1;
AsmWriteGdtr (&gdtPtr);
//
// Update selector (segment) registers base on new GDT
//
SetCodeSelector ((UINT16)CPU_CODE_SEL);
SetDataSelectors ((UINT16)CPU_DATA_SEL);
}

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#
# ConvertAsm.py: Automatically generated from CpuAsm.asm
#
# TITLE CpuAsm.asm:
#------------------------------------------------------------------------------
#*
#* Copyright 2006 - 2009, Intel Corporation
#* All rights reserved. This program and the accompanying materials
#* are licensed and made available under the terms and conditions of the BSD License
#* which accompanies this distribution. The full text of the license may be found at
#* http://opensource.org/licenses/bsd-license.php
#*
#* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
#* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#*
#* CpuAsm.S
#*
#* Abstract:
#*
#------------------------------------------------------------------------------
#.MMX
#.XMM
#EXTRN ASM_PFX(mErrorCodeFlag):DWORD # Error code flags for exceptions
#
# point to the external interrupt vector table
#
ExternalVectorTablePtr:
.byte 0, 0, 0, 0
.intel_syntax
ASM_GLOBAL ASM_PFX(InitializeExternalVectorTablePtr)
ASM_PFX(InitializeExternalVectorTablePtr):
mov eax, [esp+4]
mov ExternalVectorTablePtr, eax
ret
#------------------------------------------------------------------------------
# VOID
# SetCodeSelector (
# UINT16 Selector
# );
#------------------------------------------------------------------------------
.intel_syntax
ASM_GLOBAL ASM_PFX(SetCodeSelector)
ASM_PFX(SetCodeSelector):
mov %ecx, [%esp+4]
sub %esp, 0x10
lea %eax, setCodeSelectorLongJump
mov [%esp], %eax
mov [%esp+4], %cx
jmp fword ptr [%esp]
setCodeSelectorLongJump:
add %esp, 0x10
ret
#------------------------------------------------------------------------------
# VOID
# SetDataSelectors (
# UINT16 Selector
# );
#------------------------------------------------------------------------------
.intel_syntax
ASM_GLOBAL ASM_PFX(SetDataSelectors)
ASM_PFX(SetDataSelectors):
mov %ecx, [%esp+4]
mov %ss, %cx
mov %ds, %cx
mov %es, %cx
mov %fs, %cx
mov %gs, %cx
ret
#---------------------------------------;
# CommonInterruptEntry ;
#---------------------------------------;
# The follow algorithm is used for the common interrupt routine.
.intel_syntax
ASM_GLOBAL ASM_PFX(CommonInterruptEntry)
ASM_PFX(CommonInterruptEntry):
cli
#
# All interrupt handlers are invoked through interrupt gates, so
# IF flag automatically cleared at the entry point
#
#
# Calculate vector number
#
# Get the return address of call, actually, it is the
# address of vector number.
#
xchg ecx, [esp]
mov cx, [ecx]
and ecx, 0x0FFFF
cmp ecx, 32 # Intel reserved vector for exceptions?
jae NoErrorCode
bt ASM_PFX(mErrorCodeFlag), ecx
jc HasErrorCode
NoErrorCode:
#
# Stack:
# +---------------------+
# + EFlags +
# +---------------------+
# + CS +
# +---------------------+
# + EIP +
# +---------------------+
# + ECX +
# +---------------------+ <-- ESP
#
# Registers:
# ECX - Vector Number
#
#
# Put Vector Number on stack
#
push ecx
#
# Put 0 (dummy) error code on stack, and restore ECX
#
xor ecx, ecx # ECX = 0
xchg ecx, [esp+4]
jmp ErrorCodeAndVectorOnStack
HasErrorCode:
#
# Stack:
# +---------------------+
# + EFlags +
# +---------------------+
# + CS +
# +---------------------+
# + EIP +
# +---------------------+
# + Error Code +
# +---------------------+
# + ECX +
# +---------------------+ <-- ESP
#
# Registers:
# ECX - Vector Number
#
#
# Put Vector Number on stack and restore ECX
#
xchg ecx, [esp]
#
# Fall through to join main routine code
# at ErrorCodeAndVectorOnStack
#
CommonInterruptEntry_al_0000:
jmp CommonInterruptEntry_al_0000
ErrorCodeAndVectorOnStack:
push ebp
mov ebp, esp
#
# Stack:
# +---------------------+
# + EFlags +
# +---------------------+
# + CS +
# +---------------------+
# + EIP +
# +---------------------+
# + Error Code +
# +---------------------+
# + Vector Number +
# +---------------------+
# + EBP +
# +---------------------+ <-- EBP
#
#
# Align stack to make sure that EFI_FX_SAVE_STATE_IA32 of EFI_SYSTEM_CONTEXT_IA32
# is 16-byte aligned
#
and esp, 0x0fffffff0
sub esp, 12
#; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
push eax
push ecx
push edx
push ebx
lea ecx, [ebp + 6 * 4]
push ecx # ESP
push dword ptr [ebp] # EBP
push esi
push edi
#; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
mov eax, ss
push eax
movzx eax, word ptr [ebp + 4 * 4]
push eax
mov eax, ds
push eax
mov eax, es
push eax
mov eax, fs
push eax
mov eax, gs
push eax
#; UINT32 Eip;
mov eax, [ebp + 3 * 4]
push eax
#; UINT32 Gdtr[2], Idtr[2];
sub esp, 8
sidt [esp]
mov eax, [esp + 2]
xchg eax, [esp]
and eax, 0x0FFFF
mov [esp+4], eax
sub esp, 8
sgdt [esp]
mov eax, [esp + 2]
xchg eax, [esp]
and eax, 0x0FFFF
mov [esp+4], eax
#; UINT32 Ldtr, Tr;
xor eax, eax
str ax
push eax
sldt ax
push eax
#; UINT32 EFlags;
mov eax, [ebp + 5 * 4]
push eax
#; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
mov eax, cr4
or eax, 0x208
mov cr4, eax
push eax
mov eax, cr3
push eax
mov eax, cr2
push eax
xor eax, eax
push eax
mov eax, cr0
push eax
#; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
mov eax, dr7
push eax
#; clear Dr7 while executing debugger itself
xor eax, eax
mov dr7, eax
mov eax, dr6
push eax
#; insure all status bits in dr6 are clear...
xor eax, eax
mov dr6, eax
mov eax, dr3
push eax
mov eax, dr2
push eax
mov eax, dr1
push eax
mov eax, dr0
push eax
#; FX_SAVE_STATE_IA32 FxSaveState;
sub esp, 512
mov edi, esp
.byte 0x0f, 0x0ae, 0x07 #fxsave [edi]
#; UINT32 ExceptionData;
push dword ptr [ebp + 2 * 4]
#; call into exception handler
mov eax, ExternalVectorTablePtr # get the interrupt vectors base
or eax, eax # NULL?
jz nullExternalExceptionHandler
mov ecx, [ebp + 4]
mov eax, [eax + ecx * 4]
or eax, eax # NULL?
jz nullExternalExceptionHandler
#; Prepare parameter and call
mov edx, esp
push edx
mov edx, dword ptr [ebp + 1 * 4]
push edx
#
# Call External Exception Handler
#
call eax
add esp, 8
nullExternalExceptionHandler:
cli
#; UINT32 ExceptionData;
add esp, 4
#; FX_SAVE_STATE_IA32 FxSaveState;
mov esi, esp
.byte 0x0f, 0x0ae, 0x0e # fxrstor [esi]
add esp, 512
#; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
pop eax
mov dr0, eax
pop eax
mov dr1, eax
pop eax
mov dr2, eax
pop eax
mov dr3, eax
#; skip restore of dr6. We cleared dr6 during the context save.
add esp, 4
pop eax
mov dr7, eax
#; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
pop eax
mov cr0, eax
add esp, 4 # not for Cr1
pop eax
mov cr2, eax
pop eax
mov cr3, eax
pop eax
mov cr4, eax
#; UINT32 EFlags;
pop dword ptr [ebp + 5 * 4]
#; UINT32 Ldtr, Tr;
#; UINT32 Gdtr[2], Idtr[2];
#; Best not let anyone mess with these particular registers...
add esp, 24
#; UINT32 Eip;
pop dword ptr [ebp + 3 * 4]
#; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
#; NOTE - modified segment registers could hang the debugger... We
#; could attempt to insulate ourselves against this possibility,
#; but that poses risks as well.
#;
pop gs
pop fs
pop es
pop ds
pop dword ptr [ebp + 4 * 4]
pop ss
#; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
pop edi
pop esi
add esp, 4 # not for ebp
add esp, 4 # not for esp
pop ebx
pop edx
pop ecx
pop eax
mov esp, ebp
pop ebp
add esp, 8
iretd
#END

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TITLE CpuAsm.asm:
;------------------------------------------------------------------------------
;*
;* Copyright 2006 - 2009, Intel Corporation
;* All rights reserved. This program and the accompanying materials
;* are licensed and made available under the terms and conditions of the BSD License
;* which accompanies this distribution. The full text of the license may be found at
;* http://opensource.org/licenses/bsd-license.php
;*
;* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
;* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;*
;* CpuAsm.asm
;*
;* Abstract:
;*
;------------------------------------------------------------------------------
.686
.model flat,C
.code
EXTRN mErrorCodeFlag:DWORD ; Error code flags for exceptions
;
; point to the external interrupt vector table
;
ExternalVectorTablePtr DWORD 0
InitializeExternalVectorTablePtr PROC PUBLIC
mov eax, [esp+4]
mov ExternalVectorTablePtr, eax
ret
InitializeExternalVectorTablePtr ENDP
;------------------------------------------------------------------------------
; VOID
; SetCodeSelector (
; UINT16 Selector
; );
;------------------------------------------------------------------------------
SetCodeSelector PROC PUBLIC
mov ecx, [esp+4]
sub esp, 0x10
lea eax, setCodeSelectorLongJump
mov [esp], eax
mov [esp+4], cx
jmp fword ptr [esp]
setCodeSelectorLongJump:
add esp, 0x10
ret
SetCodeSelector ENDP
;------------------------------------------------------------------------------
; VOID
; SetDataSelectors (
; UINT16 Selector
; );
;------------------------------------------------------------------------------
SetDataSelectors PROC PUBLIC
mov ecx, [esp+4]
mov ss, cx
mov ds, cx
mov es, cx
mov fs, cx
mov gs, cx
ret
SetDataSelectors ENDP
;---------------------------------------;
; CommonInterruptEntry ;
;---------------------------------------;
; The follow algorithm is used for the common interrupt routine.
CommonInterruptEntry PROC PUBLIC
cli
;
; All interrupt handlers are invoked through interrupt gates, so
; IF flag automatically cleared at the entry point
;
;
; Calculate vector number
;
; Get the return address of call, actually, it is the
; address of vector number.
;
xchg ecx, [esp]
mov cx, [ecx]
and ecx, 0FFFFh
cmp ecx, 32 ; Intel reserved vector for exceptions?
jae NoErrorCode
bt mErrorCodeFlag, ecx
jc HasErrorCode
NoErrorCode:
;
; Stack:
; +---------------------+
; + EFlags +
; +---------------------+
; + CS +
; +---------------------+
; + EIP +
; +---------------------+
; + ECX +
; +---------------------+ <-- ESP
;
; Registers:
; ECX - Vector Number
;
;
; Put Vector Number on stack
;
push ecx
;
; Put 0 (dummy) error code on stack, and restore ECX
;
xor ecx, ecx ; ECX = 0
xchg ecx, [esp+4]
jmp ErrorCodeAndVectorOnStack
HasErrorCode:
;
; Stack:
; +---------------------+
; + EFlags +
; +---------------------+
; + CS +
; +---------------------+
; + EIP +
; +---------------------+
; + Error Code +
; +---------------------+
; + ECX +
; +---------------------+ <-- ESP
;
; Registers:
; ECX - Vector Number
;
;
; Put Vector Number on stack and restore ECX
;
xchg ecx, [esp]
;
; Fall through to join main routine code
; at ErrorCodeAndVectorOnStack
;
@@:
jmp @B
ErrorCodeAndVectorOnStack:
push ebp
mov ebp, esp
;
; Stack:
; +---------------------+
; + EFlags +
; +---------------------+
; + CS +
; +---------------------+
; + EIP +
; +---------------------+
; + Error Code +
; +---------------------+
; + Vector Number +
; +---------------------+
; + EBP +
; +---------------------+ <-- EBP
;
;
; Align stack to make sure that EFI_FX_SAVE_STATE_IA32 of EFI_SYSTEM_CONTEXT_IA32
; is 16-byte aligned
;
and esp, 0fffffff0h
sub esp, 12
;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
push eax
push ecx
push edx
push ebx
lea ecx, [ebp + 6 * 4]
push ecx ; ESP
push dword ptr [ebp] ; EBP
push esi
push edi
;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
mov eax, ss
push eax
movzx eax, word ptr [ebp + 4 * 4]
push eax
mov eax, ds
push eax
mov eax, es
push eax
mov eax, fs
push eax
mov eax, gs
push eax
;; UINT32 Eip;
mov eax, [ebp + 3 * 4]
push eax
;; UINT32 Gdtr[2], Idtr[2];
sub esp, 8
sidt [esp]
mov eax, [esp + 2]
xchg eax, [esp]
and eax, 0FFFFh
mov [esp+4], eax
sub esp, 8
sgdt [esp]
mov eax, [esp + 2]
xchg eax, [esp]
and eax, 0FFFFh
mov [esp+4], eax
;; UINT32 Ldtr, Tr;
xor eax, eax
str ax
push eax
sldt ax
push eax
;; UINT32 EFlags;
mov eax, [ebp + 5 * 4]
push eax
;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
mov eax, cr4
or eax, 208h
mov cr4, eax
push eax
mov eax, cr3
push eax
mov eax, cr2
push eax
xor eax, eax
push eax
mov eax, cr0
push eax
;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
mov eax, dr7
push eax
;; clear Dr7 while executing debugger itself
xor eax, eax
mov dr7, eax
mov eax, dr6
push eax
;; insure all status bits in dr6 are clear...
xor eax, eax
mov dr6, eax
mov eax, dr3
push eax
mov eax, dr2
push eax
mov eax, dr1
push eax
mov eax, dr0
push eax
;; FX_SAVE_STATE_IA32 FxSaveState;
sub esp, 512
mov edi, esp
db 0fh, 0aeh, 07h ;fxsave [edi]
;; UINT32 ExceptionData;
push dword ptr [ebp + 2 * 4]
;; call into exception handler
mov eax, ExternalVectorTablePtr ; get the interrupt vectors base
or eax, eax ; NULL?
jz nullExternalExceptionHandler
mov ecx, [ebp + 4]
mov eax, [eax + ecx * 4]
or eax, eax ; NULL?
jz nullExternalExceptionHandler
;; Prepare parameter and call
mov edx, esp
push edx
mov edx, dword ptr [ebp + 1 * 4]
push edx
;
; Call External Exception Handler
;
call eax
add esp, 8
nullExternalExceptionHandler:
cli
;; UINT32 ExceptionData;
add esp, 4
;; FX_SAVE_STATE_IA32 FxSaveState;
mov esi, esp
db 0fh, 0aeh, 0eh ; fxrstor [esi]
add esp, 512
;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
pop eax
mov dr0, eax
pop eax
mov dr1, eax
pop eax
mov dr2, eax
pop eax
mov dr3, eax
;; skip restore of dr6. We cleared dr6 during the context save.
add esp, 4
pop eax
mov dr7, eax
;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
pop eax
mov cr0, eax
add esp, 4 ; not for Cr1
pop eax
mov cr2, eax
pop eax
mov cr3, eax
pop eax
mov cr4, eax
;; UINT32 EFlags;
pop dword ptr [ebp + 5 * 4]
;; UINT32 Ldtr, Tr;
;; UINT32 Gdtr[2], Idtr[2];
;; Best not let anyone mess with these particular registers...
add esp, 24
;; UINT32 Eip;
pop dword ptr [ebp + 3 * 4]
;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
;; NOTE - modified segment registers could hang the debugger... We
;; could attempt to insulate ourselves against this possibility,
;; but that poses risks as well.
;;
pop gs
pop fs
pop es
pop ds
pop dword ptr [ebp + 4 * 4]
pop ss
;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
pop edi
pop esi
add esp, 4 ; not for ebp
add esp, 4 ; not for esp
pop ebx
pop edx
pop ecx
pop eax
mov esp, ebp
pop ebp
add esp, 8
iretd
CommonInterruptEntry ENDP
END

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#------------------------------------------------------------------------------
#
# Copyright (c) 2006 - 2009, Intel Corporation
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
# Module Name:
#
# IvtAsm.S
#
# Abstract:
#
# Interrupt Vector Table
#
#------------------------------------------------------------------------------
#
# Interrupt Vector Table
#
.macro SingleIdtVectorMacro vectorNum
.intel_syntax
call ASM_PFX(CommonInterruptEntry)
.short \vectorNum
nop
.endm
.macro EightIdtVectors firstVectorNum
SingleIdtVectorMacro \firstVectorNum
SingleIdtVectorMacro "(\firstVectorNum+1)"
SingleIdtVectorMacro "(\firstVectorNum+2)"
SingleIdtVectorMacro "(\firstVectorNum+3)"
SingleIdtVectorMacro "(\firstVectorNum+4)"
SingleIdtVectorMacro "(\firstVectorNum+5)"
SingleIdtVectorMacro "(\firstVectorNum+6)"
SingleIdtVectorMacro "(\firstVectorNum+7)"
.endm
.macro SixtyFourIdtVectors firstVectorNum
EightIdtVectors \firstVectorNum
EightIdtVectors "(\firstVectorNum+0x08)"
EightIdtVectors "(\firstVectorNum+0x10)"
EightIdtVectors "(\firstVectorNum+0x18)"
EightIdtVectors "(\firstVectorNum+0x20)"
EightIdtVectors "(\firstVectorNum+0x28)"
EightIdtVectors "(\firstVectorNum+0x30)"
EightIdtVectors "(\firstVectorNum+0x38)"
.endm
ASM_GLOBAL ASM_PFX(AsmIdtVector00)
.align 8
ASM_PFX(AsmIdtVector00):
SixtyFourIdtVectors 0x00
SixtyFourIdtVectors 0x40
SixtyFourIdtVectors 0x80
SixtyFourIdtVectors 0xC0
ASM_GLOBAL ASM_PFX(AsmCommonIdtEnd)
ASM_PFX(AsmCommonIdtEnd):
.byte 0

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TITLE IvtAsm.asm:
;------------------------------------------------------------------------------
;*
;* Copyright 2008 - 2009, Intel Corporation
;* All rights reserved. This program and the accompanying materials
;* are licensed and made available under the terms and conditions of the BSD License
;* which accompanies this distribution. The full text of the license may be found at
;* http://opensource.org/licenses/bsd-license.php
;*
;* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
;* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;*
;* IvtAsm.asm
;*
;* Abstract:
;*
;------------------------------------------------------------------------------
#include <Base.h>
#ifdef MDE_CPU_IA32
.686
.model flat,C
#endif
.code
;------------------------------------------------------------------------------
; Generic IDT Vector Handlers for the Host. They are all the same so they
; will compress really well.
;
; By knowing the return address for Vector 00 you can can calculate the
; vector number by looking at the call CommonInterruptEntry return address.
; (return address - (AsmIdtVector00 + 5))/8 == IDT index
;
;------------------------------------------------------------------------------
EXTRN CommonInterruptEntry:PROC
ALIGN 8
PUBLIC AsmIdtVector00
AsmIdtVector00 LABEL BYTE
REPEAT 256
call CommonInterruptEntry
dw ($ - AsmIdtVector00 - 5) / 8 ; vector number
nop
ENDM
END

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# TITLE CpuAsm.asm:
#------------------------------------------------------------------------------
#*
#* Copyright 2008 - 2009, Intel Corporation
#* All rights reserved. This program and the accompanying materials
#* are licensed and made available under the terms and conditions of the BSD License
#* which accompanies this distribution. The full text of the license may be found at
#* http://opensource.org/licenses/bsd-license.php
#*
#* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
#* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#*
#* CpuAsm.S
#*
#* Abstract:
#*
#------------------------------------------------------------------------------
#text SEGMENT
#EXTRN ASM_PFX(mErrorCodeFlag):DWORD # Error code flags for exceptions
#
# point to the external interrupt vector table
#
ExternalVectorTablePtr:
.byte 0, 0, 0, 0, 0, 0, 0, 0
.intel_syntax
ASM_GLOBAL ASM_PFX(InitializeExternalVectorTablePtr)
ASM_PFX(InitializeExternalVectorTablePtr):
lea %rax, [%rip+ExternalVectorTablePtr] # save vector number
mov [%rax], %rcx
ret
#------------------------------------------------------------------------------
# VOID
# SetCodeSelector (
# UINT16 Selector
# );
#------------------------------------------------------------------------------
.intel_syntax
ASM_GLOBAL ASM_PFX(SetCodeSelector)
ASM_PFX(SetCodeSelector):
sub %rsp, 0x10
lea %rax, [%rip+setCodeSelectorLongJump]
mov [%rsp], %rax
mov [%rsp+4], %cx
jmp fword ptr [%rsp]
setCodeSelectorLongJump:
add %rsp, 0x10
ret
#------------------------------------------------------------------------------
# VOID
# SetDataSelectors (
# UINT16 Selector
# );
#------------------------------------------------------------------------------
.intel_syntax
ASM_GLOBAL ASM_PFX(SetDataSelectors)
ASM_PFX(SetDataSelectors):
mov %ss, %cx
mov %ds, %cx
mov %es, %cx
mov %fs, %cx
mov %gs, %cx
ret
#---------------------------------------;
# CommonInterruptEntry ;
#---------------------------------------;
# The follow algorithm is used for the common interrupt routine.
.intel_syntax
ASM_GLOBAL ASM_PFX(CommonInterruptEntry)
ASM_PFX(CommonInterruptEntry):
cli
#
# All interrupt handlers are invoked through interrupt gates, so
# IF flag automatically cleared at the entry point
#
#
# Calculate vector number
#
xchg %rcx, [%rsp] # get the return address of call, actually, it is the address of vector number.
movzx %ecx, word ptr [%rcx]
cmp %ecx, 32 # Intel reserved vector for exceptions?
jae NoErrorCode
push %rax
lea %rax, [%rip+ASM_PFX(mErrorCodeFlag)]
bt dword ptr [%rax], %ecx
pop %rax
jc CommonInterruptEntry_al_0000
NoErrorCode:
#
# Push a dummy error code on the stack
# to maintain coherent stack map
#
push [%rsp]
mov qword ptr [%rsp + 8], 0
CommonInterruptEntry_al_0000:
push %rbp
mov %rbp, %rsp
#
# Stack:
# +---------------------+ <-- 16-byte aligned ensured by processor
# + Old SS +
# +---------------------+
# + Old RSP +
# +---------------------+
# + RFlags +
# +---------------------+
# + CS +
# +---------------------+
# + RIP +
# +---------------------+
# + Error Code +
# +---------------------+
# + RCX / Vector Number +
# +---------------------+
# + RBP +
# +---------------------+ <-- RBP, 16-byte aligned
#
#
# Since here the stack pointer is 16-byte aligned, so
# EFI_FX_SAVE_STATE_X64 of EFI_SYSTEM_CONTEXT_x64
# is 16-byte aligned
#
#; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
#; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
push %r15
push %r14
push %r13
push %r12
push %r11
push %r10
push %r9
push %r8
push %rax
push qword ptr [%rbp + 8] # RCX
push %rdx
push %rbx
push qword ptr [%rbp + 48] # RSP
push qword ptr [%rbp] # RBP
push %rsi
push %rdi
#; UINT64 Gs, Fs, Es, Ds, Cs, Ss; insure high 16 bits of each is zero
movzx %rax, word ptr [%rbp + 56]
push %rax # for ss
movzx %rax, word ptr [%rbp + 32]
push %rax # for cs
mov %rax, %ds
push %rax
mov %rax, %es
push %rax
mov %rax, %fs
push %rax
mov %rax, %gs
push %rax
mov [%rbp + 8], %rcx # save vector number
#; UINT64 Rip;
push qword ptr [%rbp + 24]
#; UINT64 Gdtr[2], Idtr[2];
xor %rax, %rax
push %rax
push %rax
sidt [%rsp]
xchg %rax, [%rsp + 2]
xchg %rax, [%rsp]
xchg %rax, [%rsp + 8]
xor %rax, %rax
push %rax
push %rax
sgdt [%rsp]
xchg %rax, [%rsp + 2]
xchg %rax, [%rsp]
xchg %rax, [%rsp + 8]
#; UINT64 Ldtr, Tr;
xor %rax, %rax
str %ax
push %rax
sldt %ax
push %rax
#; UINT64 RFlags;
push qword ptr [%rbp + 40]
#; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
mov %rax, %cr8
push %rax
mov %rax, %cr4
or %rax, 0x208
mov %cr4, %rax
push %rax
mov %rax, %cr3
push %rax
mov %rax, %cr2
push %rax
xor %rax, %rax
push %rax
mov %rax, %cr0
push %rax
#; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
mov %rax, %dr7
push %rax
#; clear Dr7 while executing debugger itself
xor %rax, %rax
mov %dr7, %rax
mov %rax, %dr6
push %rax
#; insure all status bits in dr6 are clear...
xor %rax, %rax
mov %dr6, %rax
mov %rax, %dr3
push %rax
mov %rax, %dr2
push %rax
mov %rax, %dr1
push %rax
mov %rax, %dr0
push %rax
#; FX_SAVE_STATE_X64 FxSaveState;
sub %rsp, 512
mov %rdi, %rsp
.byte 0x0f, 0x0ae, 0x07 #fxsave [rdi]
#; UINT32 ExceptionData;
push qword ptr [%rbp + 16]
#; call into exception handler
mov %rcx, [%rbp + 8]
lea %rax, [%rip+ExternalVectorTablePtr]
mov %eax, [%eax]
mov %rax, [%rax + %rcx * 8]
or %rax, %rax # NULL?
je nonNullValue#
#; Prepare parameter and call
# mov rcx, [rbp + 8]
mov %rdx, %rsp
#
# Per X64 calling convention, allocate maximum parameter stack space
# and make sure RSP is 16-byte aligned
#
sub %rsp, 4 * 8 + 8
call %rax
add %rsp, 4 * 8 + 8
nonNullValue:
cli
#; UINT64 ExceptionData;
add %rsp, 8
#; FX_SAVE_STATE_X64 FxSaveState;
mov %rsi, %rsp
.byte 0x0f, 0x0ae, 0x0E # fxrstor [rsi]
add %rsp, 512
#; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
pop %rax
mov %dr0, %rax
pop %rax
mov %dr1, %rax
pop %rax
mov %dr2, %rax
pop %rax
mov %dr3, %rax
#; skip restore of dr6. We cleared dr6 during the context save.
add %rsp, 8
pop %rax
mov %dr7, %rax
#; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
pop %rax
mov %cr0, %rax
add %rsp, 8 # not for Cr1
pop %rax
mov %cr2, %rax
pop %rax
mov %cr3, %rax
pop %rax
mov %cr4, %rax
pop %rax
mov %cr8, %rax
#; UINT64 RFlags;
pop qword ptr [%rbp + 40]
#; UINT64 Ldtr, Tr;
#; UINT64 Gdtr[2], Idtr[2];
#; Best not let anyone mess with these particular registers...
add %rsp, 48
#; UINT64 Rip;
pop qword ptr [%rbp + 24]
#; UINT64 Gs, Fs, Es, Ds, Cs, Ss;
pop %rax
# mov gs, rax ; not for gs
pop %rax
# mov fs, rax ; not for fs
# (X64 will not use fs and gs, so we do not restore it)
pop %rax
mov %es, %rax
pop %rax
mov %ds, %rax
pop qword ptr [%rbp + 32] # for cs
pop qword ptr [%rbp + 56] # for ss
#; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
#; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
pop %rdi
pop %rsi
add %rsp, 8 # not for rbp
pop qword ptr [%rbp + 48] # for rsp
pop %rbx
pop %rdx
pop %rcx
pop %rax
pop %r8
pop %r9
pop %r10
pop %r11
pop %r12
pop %r13
pop %r14
pop %r15
mov %rsp, %rbp
pop %rbp
add %rsp, 16
iretq
#text ENDS
#END

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TITLE CpuAsm.asm:
;------------------------------------------------------------------------------
;*
;* Copyright 2008 - 2009, Intel Corporation
;* All rights reserved. This program and the accompanying materials
;* are licensed and made available under the terms and conditions of the BSD License
;* which accompanies this distribution. The full text of the license may be found at
;* http://opensource.org/licenses/bsd-license.php
;*
;* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
;* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;*
;* CpuAsm.asm
;*
;* Abstract:
;*
;------------------------------------------------------------------------------
.code
EXTRN mErrorCodeFlag:DWORD ; Error code flags for exceptions
;
; point to the external interrupt vector table
;
ExternalVectorTablePtr QWORD 0
InitializeExternalVectorTablePtr PROC PUBLIC
mov ExternalVectorTablePtr, rcx
ret
InitializeExternalVectorTablePtr ENDP
;------------------------------------------------------------------------------
; VOID
; SetCodeSelector (
; UINT16 Selector
; );
;------------------------------------------------------------------------------
SetCodeSelector PROC PUBLIC
sub rsp, 0x10
lea rax, setCodeSelectorLongJump
mov [rsp], rax
mov [rsp+4], cx
jmp fword ptr [rsp]
setCodeSelectorLongJump:
add rsp, 0x10
ret
SetCodeSelector ENDP
;------------------------------------------------------------------------------
; VOID
; SetDataSelectors (
; UINT16 Selector
; );
;------------------------------------------------------------------------------
SetDataSelectors PROC PUBLIC
mov ss, cx
mov ds, cx
mov es, cx
mov fs, cx
mov gs, cx
ret
SetDataSelectors ENDP
;---------------------------------------;
; CommonInterruptEntry ;
;---------------------------------------;
; The follow algorithm is used for the common interrupt routine.
CommonInterruptEntry PROC PUBLIC
cli
;
; All interrupt handlers are invoked through interrupt gates, so
; IF flag automatically cleared at the entry point
;
;
; Calculate vector number
;
xchg rcx, [rsp] ; get the return address of call, actually, it is the address of vector number.
movzx ecx, word ptr [rcx]
cmp ecx, 32 ; Intel reserved vector for exceptions?
jae NoErrorCode
bt mErrorCodeFlag, ecx
jc @F
NoErrorCode:
;
; Push a dummy error code on the stack
; to maintain coherent stack map
;
push [rsp]
mov qword ptr [rsp + 8], 0
@@:
push rbp
mov rbp, rsp
;
; Stack:
; +---------------------+ <-- 16-byte aligned ensured by processor
; + Old SS +
; +---------------------+
; + Old RSP +
; +---------------------+
; + RFlags +
; +---------------------+
; + CS +
; +---------------------+
; + RIP +
; +---------------------+
; + Error Code +
; +---------------------+
; + RCX / Vector Number +
; +---------------------+
; + RBP +
; +---------------------+ <-- RBP, 16-byte aligned
;
;
; Since here the stack pointer is 16-byte aligned, so
; EFI_FX_SAVE_STATE_X64 of EFI_SYSTEM_CONTEXT_x64
; is 16-byte aligned
;
;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
push r15
push r14
push r13
push r12
push r11
push r10
push r9
push r8
push rax
push qword ptr [rbp + 8] ; RCX
push rdx
push rbx
push qword ptr [rbp + 48] ; RSP
push qword ptr [rbp] ; RBP
push rsi
push rdi
;; UINT64 Gs, Fs, Es, Ds, Cs, Ss; insure high 16 bits of each is zero
movzx rax, word ptr [rbp + 56]
push rax ; for ss
movzx rax, word ptr [rbp + 32]
push rax ; for cs
mov rax, ds
push rax
mov rax, es
push rax
mov rax, fs
push rax
mov rax, gs
push rax
mov [rbp + 8], rcx ; save vector number
;; UINT64 Rip;
push qword ptr [rbp + 24]
;; UINT64 Gdtr[2], Idtr[2];
xor rax, rax
push rax
push rax
sidt [rsp]
xchg rax, [rsp + 2]
xchg rax, [rsp]
xchg rax, [rsp + 8]
xor rax, rax
push rax
push rax
sgdt [rsp]
xchg rax, [rsp + 2]
xchg rax, [rsp]
xchg rax, [rsp + 8]
;; UINT64 Ldtr, Tr;
xor rax, rax
str ax
push rax
sldt ax
push rax
;; UINT64 RFlags;
push qword ptr [rbp + 40]
;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
mov rax, cr8
push rax
mov rax, cr4
or rax, 208h
mov cr4, rax
push rax
mov rax, cr3
push rax
mov rax, cr2
push rax
xor rax, rax
push rax
mov rax, cr0
push rax
;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
mov rax, dr7
push rax
;; clear Dr7 while executing debugger itself
xor rax, rax
mov dr7, rax
mov rax, dr6
push rax
;; insure all status bits in dr6 are clear...
xor rax, rax
mov dr6, rax
mov rax, dr3
push rax
mov rax, dr2
push rax
mov rax, dr1
push rax
mov rax, dr0
push rax
;; FX_SAVE_STATE_X64 FxSaveState;
sub rsp, 512
mov rdi, rsp
db 0fh, 0aeh, 07h ;fxsave [rdi]
;; UINT32 ExceptionData;
push qword ptr [rbp + 16]
;; call into exception handler
mov rcx, [rbp + 8]
mov rax, ExternalVectorTablePtr ; get the interrupt vectors base
mov rax, [rax + rcx * 8]
or rax, rax ; NULL?
je nonNullValue;
;; Prepare parameter and call
; mov rcx, [rbp + 8]
mov rdx, rsp
;
; Per X64 calling convention, allocate maximum parameter stack space
; and make sure RSP is 16-byte aligned
;
sub rsp, 4 * 8 + 8
call rax
add rsp, 4 * 8 + 8
nonNullValue:
cli
;; UINT64 ExceptionData;
add rsp, 8
;; FX_SAVE_STATE_X64 FxSaveState;
mov rsi, rsp
db 0fh, 0aeh, 0Eh ; fxrstor [rsi]
add rsp, 512
;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
pop rax
mov dr0, rax
pop rax
mov dr1, rax
pop rax
mov dr2, rax
pop rax
mov dr3, rax
;; skip restore of dr6. We cleared dr6 during the context save.
add rsp, 8
pop rax
mov dr7, rax
;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
pop rax
mov cr0, rax
add rsp, 8 ; not for Cr1
pop rax
mov cr2, rax
pop rax
mov cr3, rax
pop rax
mov cr4, rax
pop rax
mov cr8, rax
;; UINT64 RFlags;
pop qword ptr [rbp + 40]
;; UINT64 Ldtr, Tr;
;; UINT64 Gdtr[2], Idtr[2];
;; Best not let anyone mess with these particular registers...
add rsp, 48
;; UINT64 Rip;
pop qword ptr [rbp + 24]
;; UINT64 Gs, Fs, Es, Ds, Cs, Ss;
pop rax
; mov gs, rax ; not for gs
pop rax
; mov fs, rax ; not for fs
; (X64 will not use fs and gs, so we do not restore it)
pop rax
mov es, rax
pop rax
mov ds, rax
pop qword ptr [rbp + 32] ; for cs
pop qword ptr [rbp + 56] ; for ss
;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
pop rdi
pop rsi
add rsp, 8 ; not for rbp
pop qword ptr [rbp + 48] ; for rsp
pop rbx
pop rdx
pop rcx
pop rax
pop r8
pop r9
pop r10
pop r11
pop r12
pop r13
pop r14
pop r15
mov rsp, rbp
pop rbp
add rsp, 16
iretq
CommonInterruptEntry ENDP
END